forked from Minki/linux
KVM: Enable MTRR for EPT
The effective memory type of EPT is the mixture of MSR_IA32_CR_PAT and memory type field of EPT entry. Signed-off-by: Sheng Yang <sheng@linux.intel.com> Signed-off-by: Avi Kivity <avi@redhat.com>
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@ -483,6 +483,7 @@ struct kvm_x86_ops {
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int (*set_tss_addr)(struct kvm *kvm, unsigned int addr);
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int (*get_tdp_level)(void);
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int (*get_mt_mask_shift)(void);
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};
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extern struct kvm_x86_ops *kvm_x86_ops;
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@ -496,7 +497,7 @@ int kvm_mmu_setup(struct kvm_vcpu *vcpu);
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void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte);
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void kvm_mmu_set_base_ptes(u64 base_pte);
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void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
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u64 dirty_mask, u64 nx_mask, u64 x_mask);
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u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 mt_mask);
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int kvm_mmu_reset_context(struct kvm_vcpu *vcpu);
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void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot);
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@ -168,6 +168,7 @@ static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
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static u64 __read_mostly shadow_user_mask;
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static u64 __read_mostly shadow_accessed_mask;
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static u64 __read_mostly shadow_dirty_mask;
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static u64 __read_mostly shadow_mt_mask;
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void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte)
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{
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@ -183,13 +184,14 @@ void kvm_mmu_set_base_ptes(u64 base_pte)
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EXPORT_SYMBOL_GPL(kvm_mmu_set_base_ptes);
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void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
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u64 dirty_mask, u64 nx_mask, u64 x_mask)
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u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 mt_mask)
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{
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shadow_user_mask = user_mask;
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shadow_accessed_mask = accessed_mask;
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shadow_dirty_mask = dirty_mask;
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shadow_nx_mask = nx_mask;
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shadow_x_mask = x_mask;
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shadow_mt_mask = mt_mask;
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}
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EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
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@ -1546,6 +1548,8 @@ static int set_spte(struct kvm_vcpu *vcpu, u64 *shadow_pte,
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{
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u64 spte;
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int ret = 0;
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u64 mt_mask = shadow_mt_mask;
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/*
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* We don't set the accessed bit, since we sometimes want to see
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* whether the guest actually used the pte (in order to detect
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@ -1564,6 +1568,11 @@ static int set_spte(struct kvm_vcpu *vcpu, u64 *shadow_pte,
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spte |= shadow_user_mask;
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if (largepage)
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spte |= PT_PAGE_SIZE_MASK;
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if (mt_mask) {
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mt_mask = get_memory_type(vcpu, gfn) <<
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kvm_x86_ops->get_mt_mask_shift();
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spte |= mt_mask;
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}
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spte |= (u64)pfn << PAGE_SHIFT;
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@ -1912,6 +1912,11 @@ static int get_npt_level(void)
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#endif
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}
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static int svm_get_mt_mask_shift(void)
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{
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return 0;
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}
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static struct kvm_x86_ops svm_x86_ops = {
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.cpu_has_kvm_support = has_svm,
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.disabled_by_bios = is_disabled,
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@ -1967,6 +1972,7 @@ static struct kvm_x86_ops svm_x86_ops = {
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.set_tss_addr = svm_set_tss_addr,
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.get_tdp_level = get_npt_level,
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.get_mt_mask_shift = svm_get_mt_mask_shift,
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};
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static int __init svm_init(void)
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@ -3574,6 +3574,11 @@ static int get_ept_level(void)
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return VMX_EPT_DEFAULT_GAW + 1;
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}
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static int vmx_get_mt_mask_shift(void)
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{
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return VMX_EPT_MT_EPTE_SHIFT;
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}
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static struct kvm_x86_ops vmx_x86_ops = {
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.cpu_has_kvm_support = cpu_has_kvm_support,
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.disabled_by_bios = vmx_disabled_by_bios,
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@ -3629,6 +3634,7 @@ static struct kvm_x86_ops vmx_x86_ops = {
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.set_tss_addr = vmx_set_tss_addr,
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.get_tdp_level = get_ept_level,
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.get_mt_mask_shift = vmx_get_mt_mask_shift,
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};
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static int __init vmx_init(void)
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@ -3685,10 +3691,10 @@ static int __init vmx_init(void)
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bypass_guest_pf = 0;
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kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
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VMX_EPT_WRITABLE_MASK |
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VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT |
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VMX_EPT_IGMT_BIT);
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kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
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VMX_EPT_EXECUTABLE_MASK);
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VMX_EPT_EXECUTABLE_MASK,
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VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT);
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kvm_enable_tdp();
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} else
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kvm_disable_tdp();
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@ -2615,7 +2615,7 @@ int kvm_arch_init(void *opaque)
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kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
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kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
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kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
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PT_DIRTY_MASK, PT64_NX_MASK, 0);
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PT_DIRTY_MASK, PT64_NX_MASK, 0, 0);
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return 0;
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out:
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