forked from Minki/linux
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel: drm/i915: Stop trying to use ACPI lid status to determine LVDS connection. drm/intel: fix up set_tiling for untiled->tiled transition drm/i915: Set up the documented clock gating on Sandybridge and Ironlake. agp/intel: Don't do the chipset flush on Sandybridge. agp/intel: Respect the GTT size on Sandybridge for scratch page setup. drm/i915: fix small leak on overlay error path drm/i915: Avoid NULL deref in get_pages() unwind after error. drm/i915: Fix check with IS_GEN6 drivers/gpu/drm/i915/intel_bios.c: fix continuation line formats drm/i915: Enable VS timer dispatch. drm/i915: Rename FBC_C3_IDLE to FBC_CTL_C3_IDLE to match other registers drm/i915: remove an unnecessary wait_request() drm/i915: Don't bother with the BKL for GEM ioctls.
This commit is contained in:
commit
6467a71c56
@ -97,6 +97,9 @@ EXPORT_SYMBOL(intel_agp_enabled);
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#define IS_PINEVIEW (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \
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agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB)
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#define IS_SNB (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || \
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agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB)
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#define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_EAGLELAKE_HB || \
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agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
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agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \
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@ -107,8 +110,7 @@ EXPORT_SYMBOL(intel_agp_enabled);
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agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB || \
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agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB || \
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agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB || \
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agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || \
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agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB)
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IS_SNB)
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extern int agp_memory_reserved;
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@ -175,6 +177,10 @@ extern int agp_memory_reserved;
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#define SNB_GMCH_GMS_STOLEN_448M (0xe << 3)
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#define SNB_GMCH_GMS_STOLEN_480M (0xf << 3)
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#define SNB_GMCH_GMS_STOLEN_512M (0x10 << 3)
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#define SNB_GTT_SIZE_0M (0 << 8)
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#define SNB_GTT_SIZE_1M (1 << 8)
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#define SNB_GTT_SIZE_2M (2 << 8)
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#define SNB_GTT_SIZE_MASK (3 << 8)
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static const struct aper_size_info_fixed intel_i810_sizes[] =
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{
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@ -1200,6 +1206,9 @@ static void intel_i9xx_setup_flush(void)
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if (intel_private.ifp_resource.start)
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return;
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if (IS_SNB)
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return;
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/* setup a resource for this object */
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intel_private.ifp_resource.name = "Intel Flush Page";
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intel_private.ifp_resource.flags = IORESOURCE_MEM;
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@ -1438,6 +1447,8 @@ static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
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static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
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{
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u16 snb_gmch_ctl;
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switch (agp_bridge->dev->device) {
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case PCI_DEVICE_ID_INTEL_GM45_HB:
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case PCI_DEVICE_ID_INTEL_EAGLELAKE_HB:
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@ -1449,9 +1460,26 @@ static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
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case PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB:
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case PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB:
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case PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB:
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*gtt_offset = *gtt_size = MB(2);
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break;
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case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB:
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case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB:
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*gtt_offset = *gtt_size = MB(2);
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*gtt_offset = MB(2);
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pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
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switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) {
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default:
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case SNB_GTT_SIZE_0M:
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printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl);
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*gtt_size = MB(0);
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break;
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case SNB_GTT_SIZE_1M:
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*gtt_size = MB(1);
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break;
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case SNB_GTT_SIZE_2M:
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*gtt_size = MB(2);
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break;
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}
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break;
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default:
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*gtt_offset = *gtt_size = KB(512);
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@ -1881,29 +1881,29 @@ struct drm_ioctl_desc i915_ioctls[] = {
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DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ),
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DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
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DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
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DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
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DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
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DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH),
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DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
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DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
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DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH),
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DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH),
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DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
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DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
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DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0),
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DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, 0),
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DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, 0),
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DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0),
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DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, 0),
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DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, 0),
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DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0),
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DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),
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DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),
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DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, 0),
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DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
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DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, 0),
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DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW),
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DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW),
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DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
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DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
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DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
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DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
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DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
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DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
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DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
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DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
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DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
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DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
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DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
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DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
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DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
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DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
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DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
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DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
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DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
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DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
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DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
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DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
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DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
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DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
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DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
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};
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int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
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@ -139,12 +139,12 @@ const static struct intel_device_info intel_ironlake_m_info = {
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const static struct intel_device_info intel_sandybridge_d_info = {
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.is_i965g = 1, .is_i9xx = 1, .need_gfx_hws = 1,
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.has_hotplug = 1,
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.has_hotplug = 1, .is_gen6 = 1,
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};
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const static struct intel_device_info intel_sandybridge_m_info = {
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.is_i965g = 1, .is_mobile = 1, .is_i9xx = 1, .need_gfx_hws = 1,
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.has_hotplug = 1,
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.has_hotplug = 1, .is_gen6 = 1,
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};
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const static struct pci_device_id pciidlist[] = {
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@ -205,6 +205,7 @@ struct intel_device_info {
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u8 is_g4x : 1;
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u8 is_pineview : 1;
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u8 is_ironlake : 1;
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u8 is_gen6 : 1;
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u8 has_fbc : 1;
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u8 has_rc6 : 1;
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u8 has_pipe_cxsr : 1;
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@ -1084,6 +1085,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
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#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
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#define IS_IRONLAKE(dev) (INTEL_INFO(dev)->is_ironlake)
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#define IS_I9XX(dev) (INTEL_INFO(dev)->is_i9xx)
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#define IS_GEN6(dev) (INTEL_INFO(dev)->is_gen6)
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#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
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#define IS_GEN3(dev) (IS_I915G(dev) || \
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@ -1107,8 +1109,6 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
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#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
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#define IS_GEN6(dev) ((dev)->pci_device == 0x0102)
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/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
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* rows, which changed the alignment requirements and fence programming.
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*/
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|
@ -1466,9 +1466,6 @@ i915_gem_object_put_pages(struct drm_gem_object *obj)
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obj_priv->dirty = 0;
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for (i = 0; i < page_count; i++) {
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if (obj_priv->pages[i] == NULL)
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break;
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||||
if (obj_priv->dirty)
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set_page_dirty(obj_priv->pages[i]);
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||||
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@ -2227,11 +2224,6 @@ i915_gem_evict_something(struct drm_device *dev, int min_size)
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seqno = i915_add_request(dev, NULL, obj->write_domain);
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if (seqno == 0)
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return -ENOMEM;
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|
||||
ret = i915_wait_request(dev, seqno);
|
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if (ret)
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return ret;
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continue;
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}
|
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}
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@ -2256,7 +2248,6 @@ i915_gem_object_get_pages(struct drm_gem_object *obj,
|
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struct address_space *mapping;
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struct inode *inode;
|
||||
struct page *page;
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int ret;
|
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|
||||
if (obj_priv->pages_refcount++ != 0)
|
||||
return 0;
|
||||
@ -2279,11 +2270,9 @@ i915_gem_object_get_pages(struct drm_gem_object *obj,
|
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mapping_gfp_mask (mapping) |
|
||||
__GFP_COLD |
|
||||
gfpmask);
|
||||
if (IS_ERR(page)) {
|
||||
ret = PTR_ERR(page);
|
||||
i915_gem_object_put_pages(obj);
|
||||
return ret;
|
||||
}
|
||||
if (IS_ERR(page))
|
||||
goto err_pages;
|
||||
|
||||
obj_priv->pages[i] = page;
|
||||
}
|
||||
|
||||
@ -2291,6 +2280,15 @@ i915_gem_object_get_pages(struct drm_gem_object *obj,
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i915_gem_object_do_bit_17_swizzle(obj);
|
||||
|
||||
return 0;
|
||||
|
||||
err_pages:
|
||||
while (i--)
|
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page_cache_release(obj_priv->pages[i]);
|
||||
|
||||
drm_free_large(obj_priv->pages);
|
||||
obj_priv->pages = NULL;
|
||||
obj_priv->pages_refcount--;
|
||||
return PTR_ERR(page);
|
||||
}
|
||||
|
||||
static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
|
||||
@ -4730,6 +4728,11 @@ i915_gem_init_ringbuffer(struct drm_device *dev)
|
||||
ring->space += ring->Size;
|
||||
}
|
||||
|
||||
if (IS_I9XX(dev) && !IS_GEN3(dev)) {
|
||||
I915_WRITE(MI_MODE,
|
||||
(VS_TIMER_DISPATCH) << 16 | VS_TIMER_DISPATCH);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -325,9 +325,12 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
|
||||
* need to ensure that any fence register is cleared.
|
||||
*/
|
||||
if (!i915_gem_object_fence_offset_ok(obj, args->tiling_mode))
|
||||
ret = i915_gem_object_unbind(obj);
|
||||
ret = i915_gem_object_unbind(obj);
|
||||
else if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
|
||||
ret = i915_gem_object_put_fence_reg(obj);
|
||||
else
|
||||
ret = i915_gem_object_put_fence_reg(obj);
|
||||
i915_gem_release_mmap(obj);
|
||||
|
||||
if (ret != 0) {
|
||||
WARN(ret != -ERESTARTSYS,
|
||||
"failed to reset object for tiling switch");
|
||||
|
@ -298,6 +298,10 @@
|
||||
#define INSTDONE 0x02090
|
||||
#define NOPID 0x02094
|
||||
#define HWSTAM 0x02098
|
||||
|
||||
#define MI_MODE 0x0209c
|
||||
# define VS_TIMER_DISPATCH (1 << 6)
|
||||
|
||||
#define SCPD0 0x0209c /* 915+ only */
|
||||
#define IER 0x020a0
|
||||
#define IIR 0x020a4
|
||||
@ -366,7 +370,7 @@
|
||||
#define FBC_CTL_PERIODIC (1<<30)
|
||||
#define FBC_CTL_INTERVAL_SHIFT (16)
|
||||
#define FBC_CTL_UNCOMPRESSIBLE (1<<14)
|
||||
#define FBC_C3_IDLE (1<<13)
|
||||
#define FBC_CTL_C3_IDLE (1<<13)
|
||||
#define FBC_CTL_STRIDE_SHIFT (5)
|
||||
#define FBC_CTL_FENCENO (1<<0)
|
||||
#define FBC_COMMAND 0x0320c
|
||||
@ -2172,6 +2176,14 @@
|
||||
#define DISPLAY_PORT_PLL_BIOS_1 0x46010
|
||||
#define DISPLAY_PORT_PLL_BIOS_2 0x46014
|
||||
|
||||
#define PCH_DSPCLK_GATE_D 0x42020
|
||||
# define DPFDUNIT_CLOCK_GATE_DISABLE (1 << 7)
|
||||
# define DPARBUNIT_CLOCK_GATE_DISABLE (1 << 5)
|
||||
|
||||
#define PCH_3DCGDIS0 0x46020
|
||||
# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
|
||||
# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
|
||||
|
||||
#define FDI_PLL_FREQ_CTL 0x46030
|
||||
#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
|
||||
#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
|
||||
|
@ -417,8 +417,9 @@ parse_edp(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
|
||||
edp = find_section(bdb, BDB_EDP);
|
||||
if (!edp) {
|
||||
if (SUPPORTS_EDP(dev_priv->dev) && dev_priv->edp_support) {
|
||||
DRM_DEBUG_KMS("No eDP BDB found but eDP panel supported,\
|
||||
assume 18bpp panel color depth.\n");
|
||||
DRM_DEBUG_KMS("No eDP BDB found but eDP panel "
|
||||
"supported, assume 18bpp panel color "
|
||||
"depth.\n");
|
||||
dev_priv->edp_bpp = 18;
|
||||
}
|
||||
return;
|
||||
|
@ -1032,7 +1032,7 @@ static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
|
||||
/* enable it... */
|
||||
fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
|
||||
if (IS_I945GM(dev))
|
||||
fbc_ctl |= FBC_C3_IDLE; /* 945 needs special SR handling */
|
||||
fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
|
||||
fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
|
||||
fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
|
||||
if (obj_priv->tiling_mode != I915_TILING_NONE)
|
||||
@ -4717,6 +4717,20 @@ void intel_init_clock_gating(struct drm_device *dev)
|
||||
* specs, but enable as much else as we can.
|
||||
*/
|
||||
if (HAS_PCH_SPLIT(dev)) {
|
||||
uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
|
||||
|
||||
if (IS_IRONLAKE(dev)) {
|
||||
/* Required for FBC */
|
||||
dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
|
||||
/* Required for CxSR */
|
||||
dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
|
||||
|
||||
I915_WRITE(PCH_3DCGDIS0,
|
||||
MARIUNIT_CLOCK_GATE_DISABLE |
|
||||
SVSMUNIT_CLOCK_GATE_DISABLE);
|
||||
}
|
||||
|
||||
I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
|
||||
return;
|
||||
} else if (IS_G4X(dev)) {
|
||||
uint32_t dspclk_gate;
|
||||
|
@ -607,53 +607,6 @@ static void intel_lvds_mode_set(struct drm_encoder *encoder,
|
||||
I915_WRITE(PFIT_CONTROL, lvds_priv->pfit_control);
|
||||
}
|
||||
|
||||
/* Some lid devices report incorrect lid status, assume they're connected */
|
||||
static const struct dmi_system_id bad_lid_status[] = {
|
||||
{
|
||||
.ident = "Compaq nx9020",
|
||||
.matches = {
|
||||
DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
|
||||
DMI_MATCH(DMI_BOARD_NAME, "3084"),
|
||||
},
|
||||
},
|
||||
{
|
||||
.ident = "Samsung SX20S",
|
||||
.matches = {
|
||||
DMI_MATCH(DMI_SYS_VENDOR, "Samsung Electronics"),
|
||||
DMI_MATCH(DMI_BOARD_NAME, "SX20S"),
|
||||
},
|
||||
},
|
||||
{
|
||||
.ident = "Aspire One",
|
||||
.matches = {
|
||||
DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
|
||||
DMI_MATCH(DMI_PRODUCT_NAME, "Aspire one"),
|
||||
},
|
||||
},
|
||||
{
|
||||
.ident = "Aspire 1810T",
|
||||
.matches = {
|
||||
DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
|
||||
DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 1810T"),
|
||||
},
|
||||
},
|
||||
{
|
||||
.ident = "PC-81005",
|
||||
.matches = {
|
||||
DMI_MATCH(DMI_SYS_VENDOR, "MALATA"),
|
||||
DMI_MATCH(DMI_PRODUCT_NAME, "PC-81005"),
|
||||
},
|
||||
},
|
||||
{
|
||||
.ident = "Clevo M5x0N",
|
||||
.matches = {
|
||||
DMI_MATCH(DMI_SYS_VENDOR, "CLEVO Co."),
|
||||
DMI_MATCH(DMI_BOARD_NAME, "M5x0N"),
|
||||
},
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/**
|
||||
* Detect the LVDS connection.
|
||||
*
|
||||
@ -669,12 +622,9 @@ static enum drm_connector_status intel_lvds_detect(struct drm_connector *connect
|
||||
/* ACPI lid methods were generally unreliable in this generation, so
|
||||
* don't even bother.
|
||||
*/
|
||||
if (IS_GEN2(dev))
|
||||
if (IS_GEN2(dev) || IS_GEN3(dev))
|
||||
return connector_status_connected;
|
||||
|
||||
if (!dmi_check_system(bad_lid_status) && !acpi_lid_open())
|
||||
status = connector_status_disconnected;
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
|
@ -1068,14 +1068,18 @@ int intel_overlay_put_image(struct drm_device *dev, void *data,
|
||||
|
||||
drmmode_obj = drm_mode_object_find(dev, put_image_rec->crtc_id,
|
||||
DRM_MODE_OBJECT_CRTC);
|
||||
if (!drmmode_obj)
|
||||
return -ENOENT;
|
||||
if (!drmmode_obj) {
|
||||
ret = -ENOENT;
|
||||
goto out_free;
|
||||
}
|
||||
crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
|
||||
|
||||
new_bo = drm_gem_object_lookup(dev, file_priv,
|
||||
put_image_rec->bo_handle);
|
||||
if (!new_bo)
|
||||
return -ENOENT;
|
||||
if (!new_bo) {
|
||||
ret = -ENOENT;
|
||||
goto out_free;
|
||||
}
|
||||
|
||||
mutex_lock(&dev->mode_config.mutex);
|
||||
mutex_lock(&dev->struct_mutex);
|
||||
@ -1165,6 +1169,7 @@ out_unlock:
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
mutex_unlock(&dev->mode_config.mutex);
|
||||
drm_gem_object_unreference_unlocked(new_bo);
|
||||
out_free:
|
||||
kfree(params);
|
||||
|
||||
return ret;
|
||||
|
Loading…
Reference in New Issue
Block a user