drm/amdgpu: move psp macro into amdgpu_psp header
Demangle amdgpu.h. Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1353,7 +1353,6 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
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#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
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#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
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#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
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#define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
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/* Common functions */
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int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
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@ -63,13 +63,16 @@ struct psp_funcs
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int (*prep_cmd_buf)(struct amdgpu_firmware_info *ucode,
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struct psp_gfx_cmd_resp *cmd);
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int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type);
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int (*ring_create)(struct psp_context *psp, enum psp_ring_type ring_type);
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int (*ring_create)(struct psp_context *psp,
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enum psp_ring_type ring_type);
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int (*ring_stop)(struct psp_context *psp,
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enum psp_ring_type ring_type);
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int (*ring_destroy)(struct psp_context *psp,
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enum psp_ring_type ring_type);
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int (*cmd_submit)(struct psp_context *psp, struct amdgpu_firmware_info *ucode,
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uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, int index);
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int (*cmd_submit)(struct psp_context *psp,
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struct amdgpu_firmware_info *ucode,
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uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
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int index);
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bool (*compare_sram_data)(struct psp_context *psp,
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struct amdgpu_firmware_info *ucode,
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enum AMDGPU_UCODE_ID ucode_type);
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@ -83,11 +86,11 @@ struct psp_context
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struct psp_ring km_ring;
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struct psp_gfx_cmd_resp *cmd;
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const struct psp_funcs *funcs;
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const struct psp_funcs *funcs;
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/* fence buffer */
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struct amdgpu_bo *fw_pri_bo;
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uint64_t fw_pri_mc_addr;
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struct amdgpu_bo *fw_pri_bo;
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uint64_t fw_pri_mc_addr;
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void *fw_pri_buf;
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/* sos firmware */
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@ -100,8 +103,8 @@ struct psp_context
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uint8_t *sos_start_addr;
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/* tmr buffer */
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struct amdgpu_bo *tmr_bo;
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uint64_t tmr_mc_addr;
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struct amdgpu_bo *tmr_bo;
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uint64_t tmr_mc_addr;
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void *tmr_buf;
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/* asd firmware and buffer */
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@ -110,13 +113,13 @@ struct psp_context
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uint32_t asd_feature_version;
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uint32_t asd_ucode_size;
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uint8_t *asd_start_addr;
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struct amdgpu_bo *asd_shared_bo;
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uint64_t asd_shared_mc_addr;
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struct amdgpu_bo *asd_shared_bo;
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uint64_t asd_shared_mc_addr;
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void *asd_shared_buf;
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/* fence buffer */
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struct amdgpu_bo *fence_buf_bo;
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uint64_t fence_buf_mc_addr;
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struct amdgpu_bo *fence_buf_bo;
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uint64_t fence_buf_mc_addr;
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void *fence_buf;
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/* cmd buffer */
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@ -150,6 +153,8 @@ struct amdgpu_psp_funcs {
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#define psp_mode1_reset(psp) \
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((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false)
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#define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
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extern const struct amd_ip_funcs psp_ip_funcs;
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extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;
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