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clk: renesas: r8a779f0: Add MSIOF clocks

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Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220824103515.54931-2-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Wolfram Sang 2022-08-24 12:35:12 +02:00 committed by Geert Uytterhoeven
parent 425e9e04ae
commit 644814c107
1 changed files with 4 additions and 0 deletions
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4
drivers/clk/renesas/r8a779f0-cpg-mssr.c
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@ -136,6 +136,10 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = {
DEF_MOD("i2c3", 521, R8A779F0_CLK_S0D6_PER),
DEF_MOD("i2c4", 522, R8A779F0_CLK_S0D6_PER),
DEF_MOD("i2c5", 523, R8A779F0_CLK_S0D6_PER),
DEF_MOD("msiof0", 618, R8A779F0_CLK_MSO),
DEF_MOD("msiof1", 619, R8A779F0_CLK_MSO),
DEF_MOD("msiof2", 620, R8A779F0_CLK_MSO),
DEF_MOD("msiof3", 621, R8A779F0_CLK_MSO),
DEF_MOD("pcie0", 624, R8A779F0_CLK_S0D2),
DEF_MOD("pcie1", 625, R8A779F0_CLK_S0D2),
DEF_MOD("scif0", 702, R8A779F0_CLK_S0D12_PER),