forked from Minki/linux
ASoC: da7219: Update PLL ranges and dividers to improve locking
The expected MCLK frequency ranges and the associated dividers are updated to improve PLL locking in a corner scenario, with low MCLK frequency near an input divider change boundary. Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -1079,21 +1079,21 @@ static int da7219_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
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dev_err(codec->dev, "PLL input clock %d below valid range\n",
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dev_err(codec->dev, "PLL input clock %d below valid range\n",
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da7219->mclk_rate);
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da7219->mclk_rate);
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return -EINVAL;
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return -EINVAL;
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} else if (da7219->mclk_rate <= 5000000) {
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} else if (da7219->mclk_rate <= 4500000) {
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indiv_bits = DA7219_PLL_INDIV_2_5_MHZ;
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indiv_bits = DA7219_PLL_INDIV_2_TO_4_5_MHZ;
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indiv = DA7219_PLL_INDIV_2_5_MHZ_VAL;
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indiv = DA7219_PLL_INDIV_2_TO_4_5_MHZ_VAL;
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} else if (da7219->mclk_rate <= 10000000) {
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} else if (da7219->mclk_rate <= 9000000) {
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indiv_bits = DA7219_PLL_INDIV_5_10_MHZ;
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indiv_bits = DA7219_PLL_INDIV_4_5_TO_9_MHZ;
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indiv = DA7219_PLL_INDIV_5_10_MHZ_VAL;
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indiv = DA7219_PLL_INDIV_4_5_TO_9_MHZ_VAL;
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} else if (da7219->mclk_rate <= 20000000) {
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} else if (da7219->mclk_rate <= 18000000) {
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indiv_bits = DA7219_PLL_INDIV_10_20_MHZ;
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indiv_bits = DA7219_PLL_INDIV_9_TO_18_MHZ;
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indiv = DA7219_PLL_INDIV_10_20_MHZ_VAL;
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indiv = DA7219_PLL_INDIV_9_TO_18_MHZ_VAL;
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} else if (da7219->mclk_rate <= 40000000) {
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} else if (da7219->mclk_rate <= 36000000) {
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indiv_bits = DA7219_PLL_INDIV_20_40_MHZ;
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indiv_bits = DA7219_PLL_INDIV_18_TO_36_MHZ;
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indiv = DA7219_PLL_INDIV_20_40_MHZ_VAL;
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indiv = DA7219_PLL_INDIV_18_TO_36_MHZ_VAL;
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} else if (da7219->mclk_rate <= 54000000) {
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} else if (da7219->mclk_rate <= 54000000) {
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indiv_bits = DA7219_PLL_INDIV_40_54_MHZ;
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indiv_bits = DA7219_PLL_INDIV_36_TO_54_MHZ;
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indiv = DA7219_PLL_INDIV_40_54_MHZ_VAL;
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indiv = DA7219_PLL_INDIV_36_TO_54_MHZ_VAL;
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} else {
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} else {
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dev_err(codec->dev, "PLL input clock %d above valid range\n",
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dev_err(codec->dev, "PLL input clock %d above valid range\n",
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da7219->mclk_rate);
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da7219->mclk_rate);
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@ -194,11 +194,11 @@
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/* DA7219_PLL_CTRL = 0x20 */
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/* DA7219_PLL_CTRL = 0x20 */
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#define DA7219_PLL_INDIV_SHIFT 2
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#define DA7219_PLL_INDIV_SHIFT 2
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#define DA7219_PLL_INDIV_MASK (0x7 << 2)
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#define DA7219_PLL_INDIV_MASK (0x7 << 2)
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#define DA7219_PLL_INDIV_2_5_MHZ (0x0 << 2)
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#define DA7219_PLL_INDIV_2_TO_4_5_MHZ (0x0 << 2)
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#define DA7219_PLL_INDIV_5_10_MHZ (0x1 << 2)
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#define DA7219_PLL_INDIV_4_5_TO_9_MHZ (0x1 << 2)
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#define DA7219_PLL_INDIV_10_20_MHZ (0x2 << 2)
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#define DA7219_PLL_INDIV_9_TO_18_MHZ (0x2 << 2)
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#define DA7219_PLL_INDIV_20_40_MHZ (0x3 << 2)
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#define DA7219_PLL_INDIV_18_TO_36_MHZ (0x3 << 2)
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#define DA7219_PLL_INDIV_40_54_MHZ (0x4 << 2)
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#define DA7219_PLL_INDIV_36_TO_54_MHZ (0x4 << 2)
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#define DA7219_PLL_MCLK_SQR_EN_SHIFT 5
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#define DA7219_PLL_MCLK_SQR_EN_SHIFT 5
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#define DA7219_PLL_MCLK_SQR_EN_MASK (0x1 << 5)
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#define DA7219_PLL_MCLK_SQR_EN_MASK (0x1 << 5)
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#define DA7219_PLL_MODE_SHIFT 6
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#define DA7219_PLL_MODE_SHIFT 6
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@ -761,11 +761,11 @@
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#define DA7219_PLL_FREQ_OUT_98304 98304000
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#define DA7219_PLL_FREQ_OUT_98304 98304000
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/* PLL Frequency Dividers */
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/* PLL Frequency Dividers */
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#define DA7219_PLL_INDIV_2_5_MHZ_VAL 1
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#define DA7219_PLL_INDIV_2_TO_4_5_MHZ_VAL 1
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#define DA7219_PLL_INDIV_5_10_MHZ_VAL 2
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#define DA7219_PLL_INDIV_4_5_TO_9_MHZ_VAL 2
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#define DA7219_PLL_INDIV_10_20_MHZ_VAL 4
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#define DA7219_PLL_INDIV_9_TO_18_MHZ_VAL 4
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#define DA7219_PLL_INDIV_20_40_MHZ_VAL 8
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#define DA7219_PLL_INDIV_18_TO_36_MHZ_VAL 8
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#define DA7219_PLL_INDIV_40_54_MHZ_VAL 16
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#define DA7219_PLL_INDIV_36_TO_54_MHZ_VAL 16
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/* SRM */
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/* SRM */
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#define DA7219_SRM_CHECK_RETRIES 8
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#define DA7219_SRM_CHECK_RETRIES 8
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