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staging: rtl8723bs: hal: sdio_halinit: fix spaces preferred around that unary operator

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This patch fixes below issues reported by checkpatch

CHECK: spaces preferred around that '+' (ctx:VxV)
CHECK: spaces preferred around that '<<' (ctx:VxV)
CHECK: spaces preferred around that '|' (ctx:VxV)

Signed-off-by: Hariprasad Kelam <hariprasad.kelam@gmail.com>
------
changes in v2:  Send proper patch without corruption
----
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Hariprasad Kelam 2019-06-14 08:24:59 +05:30 committed by Greg Kroah-Hartman
parent c11621ffd9
commit 639b6023be
1 changed files with 45 additions and 45 deletions
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90
drivers/staging/rtl8723bs/hal/sdio_halinit.c
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@ -112,17 +112,17 @@ u8 _InitPowerOn_8723BS(struct adapter *padapter)
/* all of these MUST be configured before power on */
#ifdef CONFIG_EXT_CLK
/* Use external crystal(XTAL) */
value8 = rtw_read8(padapter, REG_PAD_CTRL1_8723B+2);
value8 = rtw_read8(padapter, REG_PAD_CTRL1_8723B + 2);
value8 |= BIT(7);
rtw_write8(padapter, REG_PAD_CTRL1_8723B+2, value8);
rtw_write8(padapter, REG_PAD_CTRL1_8723B + 2, value8);
/* CLK_REQ High active or Low Active */
/* Request GPIO polarity: */
/* 0: low active */
/* 1: high active */
value8 = rtw_read8(padapter, REG_MULTI_FUNC_CTRL+1);
value8 = rtw_read8(padapter, REG_MULTI_FUNC_CTRL + 1);
value8 |= BIT(5);
rtw_write8(padapter, REG_MULTI_FUNC_CTRL+1, value8);
rtw_write8(padapter, REG_MULTI_FUNC_CTRL + 1, value8);
#endif /* CONFIG_EXT_CLK */
/* only cmd52 can be used before power on(card enable) */
@ -137,12 +137,12 @@ u8 _InitPowerOn_8723BS(struct adapter *padapter)
}
/* Radio-Off Pin Trigger */
value8 = rtw_read8(padapter, REG_GPIO_INTM+1);
value8 = rtw_read8(padapter, REG_GPIO_INTM + 1);
value8 |= BIT(1); /* Enable falling edge triggering interrupt */
rtw_write8(padapter, REG_GPIO_INTM+1, value8);
value8 = rtw_read8(padapter, REG_GPIO_IO_SEL_2+1);
rtw_write8(padapter, REG_GPIO_INTM + 1, value8);
value8 = rtw_read8(padapter, REG_GPIO_IO_SEL_2 + 1);
value8 |= BIT(1);
rtw_write8(padapter, REG_GPIO_IO_SEL_2+1, value8);
rtw_write8(padapter, REG_GPIO_IO_SEL_2 + 1, value8);
/* Enable power down and GPIO interrupt */
value16 = rtw_read16(padapter, REG_APS_FSMCO);
@ -203,13 +203,13 @@ static void _init_available_page_threshold(struct adapter *padapter, u8 numHQ, u
u16 HQ_threshold, NQ_threshold, LQ_threshold;
HQ_threshold = (numPubQ + numHQ + 1) >> 1;
HQ_threshold |= (HQ_threshold<<8);
HQ_threshold |= (HQ_threshold << 8);
NQ_threshold = (numPubQ + numNQ + 1) >> 1;
NQ_threshold |= (NQ_threshold<<8);
NQ_threshold |= (NQ_threshold << 8);
LQ_threshold = (numPubQ + numLQ + 1) >> 1;
LQ_threshold |= (LQ_threshold<<8);
LQ_threshold |= (LQ_threshold << 8);
rtw_write16(padapter, 0x218, HQ_threshold);
rtw_write16(padapter, 0x21A, NQ_threshold);
@ -271,7 +271,7 @@ static void _InitTxBufferBoundary(struct adapter *padapter)
rtw_write8(padapter, REG_TXPKTBUF_MGQ_BDNY_8723B, txpktbuf_bndy);
rtw_write8(padapter, REG_TXPKTBUF_WMAC_LBK_BF_HD_8723B, txpktbuf_bndy);
rtw_write8(padapter, REG_TRXFF_BNDY, txpktbuf_bndy);
rtw_write8(padapter, REG_TDECTRL+1, txpktbuf_bndy);
rtw_write8(padapter, REG_TDECTRL + 1, txpktbuf_bndy);
}
static void _InitNormalChipRegPriority(
@ -564,7 +564,7 @@ static void HalRxAggr8723BSdio(struct adapter *padapter)
valueDMAPageCount = 0x06;
}
rtw_write8(padapter, REG_RXDMA_AGG_PG_TH+1, valueDMATimeout);
rtw_write8(padapter, REG_RXDMA_AGG_PG_TH + 1, valueDMATimeout);
rtw_write8(padapter, REG_RXDMA_AGG_PG_TH, valueDMAPageCount);
}
@ -583,8 +583,8 @@ static void sdio_AggSettingRxUpdate(struct adapter *padapter)
rtw_write8(padapter, REG_TRXDMA_CTRL, valueDMA);
valueRxAggCtrl |= RXDMA_AGG_MODE_EN;
valueRxAggCtrl |= ((aggBurstNum<<2) & 0x0C);
valueRxAggCtrl |= ((aggBurstSize<<4) & 0x30);
valueRxAggCtrl |= ((aggBurstNum << 2) & 0x0C);
valueRxAggCtrl |= ((aggBurstSize << 4) & 0x30);
rtw_write8(padapter, REG_RXDMA_MODE_CTRL_8723B, valueRxAggCtrl);/* RxAggLowThresh = 4*1K */
}
@ -738,11 +738,11 @@ static u32 rtl8723bs_hal_init(struct adapter *padapter)
rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_orig);
/* ser rpwm */
val8 = rtw_read8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HRPWM1);
val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1);
val8 &= 0x80;
val8 += 0x80;
val8 |= BIT(6);
rtw_write8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HRPWM1, val8);
rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
DBG_871X("%s: write rpwm =%02x\n", __func__, val8);
adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
@ -772,7 +772,7 @@ static u32 rtl8723bs_hal_init(struct adapter *padapter)
}
#ifdef CONFIG_WOWLAN
if (rtw_read8(padapter, REG_MCUFWDL)&BIT7) {
if (rtw_read8(padapter, REG_MCUFWDL) & BIT7) {
u8 reg_val = 0;
DBG_871X("+Reset Entry+\n");
rtw_write8(padapter, REG_MCUFWDL, 0x00);
@ -786,12 +786,12 @@ static u32 rtl8723bs_hal_init(struct adapter *padapter)
/* reset TRX path */
rtw_write16(padapter, REG_CR, 0);
/* reset MAC, Digital Core */
reg_val = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
reg_val = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
reg_val &= ~(BIT(4) | BIT(7));
rtw_write8(padapter, REG_SYS_FUNC_EN+1, reg_val);
reg_val = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
rtw_write8(padapter, REG_SYS_FUNC_EN + 1, reg_val);
reg_val = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
reg_val |= BIT(4) | BIT(7);
rtw_write8(padapter, REG_SYS_FUNC_EN+1, reg_val);
rtw_write8(padapter, REG_SYS_FUNC_EN + 1, reg_val);
DBG_871X("-Reset Entry-\n");
}
#endif /* CONFIG_WOWLAN */
@ -939,7 +939,7 @@ static u32 rtl8723bs_hal_init(struct adapter *padapter)
/* Configure SDIO TxRx Control to enable Rx DMA timer masking. */
/* 2010.02.24. */
/* */
rtw_write32(padapter, SDIO_LOCAL_BASE|SDIO_REG_TX_CTRL, 0);
rtw_write32(padapter, SDIO_LOCAL_BASE | SDIO_REG_TX_CTRL, 0);
_RfPowerSave(padapter);
@ -963,7 +963,7 @@ static u32 rtl8723bs_hal_init(struct adapter *padapter)
rtw_hal_set_hwreg(padapter, HW_VAR_NAV_UPPER, (u8 *)&NavUpper);
/* ack for xmit mgmt frames. */
rtw_write32(padapter, REG_FWHW_TXQ_CTRL, rtw_read32(padapter, REG_FWHW_TXQ_CTRL)|BIT(12));
rtw_write32(padapter, REG_FWHW_TXQ_CTRL, rtw_read32(padapter, REG_FWHW_TXQ_CTRL) | BIT(12));
/* pHalData->PreRpwmVal = SdioLocalCmd52Read1Byte(padapter, SDIO_REG_HRPWM1) & 0x80; */
@ -1043,19 +1043,19 @@ static void CardDisableRTL8723BSdio(struct adapter *padapter)
rtl8723b_FirmwareSelfReset(padapter);
/* Reset MCU 0x2[10]= 0. Suggested by Filen. 2011.01.26. by tynli. */
u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
u1bTmp &= ~BIT(2); /* 0x2[10], FEN_CPUEN */
rtw_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp);
rtw_write8(padapter, REG_SYS_FUNC_EN + 1, u1bTmp);
/* MCUFWDL 0x80[1:0]= 0 */
/* reset MCU ready status */
rtw_write8(padapter, REG_MCUFWDL, 0);
/* Reset MCU IO Wrapper, added by Roger, 2011.08.30 */
u1bTmp = rtw_read8(padapter, REG_RSV_CTRL+1);
u1bTmp = rtw_read8(padapter, REG_RSV_CTRL + 1);
u1bTmp &= ~BIT(0);
rtw_write8(padapter, REG_RSV_CTRL+1, u1bTmp);
u1bTmp = rtw_read8(padapter, REG_RSV_CTRL+1);
rtw_write8(padapter, REG_RSV_CTRL + 1, u1bTmp);
u1bTmp = rtw_read8(padapter, REG_RSV_CTRL + 1);
u1bTmp |= BIT(0);
rtw_write8(padapter, REG_RSV_CTRL+1, u1bTmp);
@ -1094,10 +1094,10 @@ static u32 rtl8723bs_hal_deinit(struct adapter *padapter)
/* H2C done, enter 32k */
if (val8 == 0) {
/* ser rpwm to enter 32k */
val8 = rtw_read8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HRPWM1);
val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1);
val8 += 0x80;
val8 |= BIT(0);
rtw_write8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HRPWM1, val8);
rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
DBG_871X("%s: write rpwm =%02x\n", __func__, val8);
adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
cnt = val8 = 0;
@ -1189,7 +1189,7 @@ static void rtl8723bs_interface_configure(struct adapter *padapter)
switch (pHalData->OutEpNumber) {
case 3:
pHalData->OutEpQueueSel = TX_SELE_HQ | TX_SELE_LQ|TX_SELE_NQ;
pHalData->OutEpQueueSel = TX_SELE_HQ | TX_SELE_LQ | TX_SELE_NQ;
break;
case 2:
pHalData->OutEpQueueSel = TX_SELE_HQ | TX_SELE_NQ;
@ -1276,7 +1276,7 @@ static void Hal_EfuseParseBoardType_8723BS(
if (!AutoLoadFail) {
pHalData->BoardType = (hwinfo[EEPROM_RF_BOARD_OPTION_8723B] & 0xE0) >> 5;
if (pHalData->BoardType == 0xFF)
pHalData->BoardType = (EEPROM_DEFAULT_BOARD_OPTION&0xE0)>>5;
pHalData->BoardType = (EEPROM_DEFAULT_BOARD_OPTION & 0xE0) >> 5;
} else
pHalData->BoardType = 0;
RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Board Type: 0x%2x\n", pHalData->BoardType));
@ -1444,7 +1444,7 @@ static void SetHwReg8723BS(struct adapter *padapter, u8 variable, u8 *val)
{
val8 = *val;
val8 &= 0xC1;
rtw_write8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HRPWM1, val8);
rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
}
break;
case HW_VAR_SET_REQ_FW_PS:
@ -1480,9 +1480,9 @@ static void SetHwReg8723BS(struct adapter *padapter, u8 variable, u8 *val)
/* 2. RX DMA stop */
DBG_871X_LEVEL(_drv_always_, "Pause DMA\n");
rtw_write32(padapter, REG_RXPKT_NUM, (rtw_read32(padapter, REG_RXPKT_NUM)|RW_RELEASE_EN));
rtw_write32(padapter, REG_RXPKT_NUM, (rtw_read32(padapter, REG_RXPKT_NUM) | RW_RELEASE_EN));
do {
if ((rtw_read32(padapter, REG_RXPKT_NUM)&RXDMA_IDLE)) {
if ((rtw_read32(padapter, REG_RXPKT_NUM) & RXDMA_IDLE)) {
DBG_871X_LEVEL(_drv_always_, "RX_DMA_IDLE is true\n");
break;
} else {
@ -1514,7 +1514,7 @@ static void SetHwReg8723BS(struct adapter *padapter, u8 variable, u8 *val)
sdio_local_read(padapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
DBG_871X("DisableInterruptButCpwm28723BSdio(): Read SDIO_REG_HIMR: 0x%08x\n", tmp);
himr = cpu_to_le32(SDIO_HIMR_DISABLED)|SDIO_HIMR_CPWM2_MSK;
himr = cpu_to_le32(SDIO_HIMR_DISABLED) | SDIO_HIMR_CPWM2_MSK;
sdio_local_write(padapter, SDIO_REG_HIMR, 4, (u8 *)&himr);
sdio_local_read(padapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
@ -1529,7 +1529,7 @@ static void SetHwReg8723BS(struct adapter *padapter, u8 variable, u8 *val)
DBG_871X_LEVEL(_drv_always_, "Check EnableWoWlan CMD is ready\n");
mstatus = rtw_read8(padapter, REG_WOW_CTRL);
trycnt = 10;
while (!(mstatus&BIT1) && trycnt > 1) {
while (!(mstatus & BIT1) && trycnt > 1) {
mstatus = rtw_read8(padapter, REG_WOW_CTRL);
DBG_871X("Loop index: %d :0x%02x\n", trycnt, mstatus);
trycnt--;
@ -1587,7 +1587,7 @@ static void SetHwReg8723BS(struct adapter *padapter, u8 variable, u8 *val)
DBG_871X_LEVEL(_drv_always_, "Check DisableWoWlan CMD is ready\n");
mstatus = rtw_read8(padapter, REG_WOW_CTRL);
trycnt = 50;
while (mstatus&BIT1 && trycnt > 1) {
while (mstatus & BIT1 && trycnt > 1) {
mstatus = rtw_read8(padapter, REG_WOW_CTRL);
DBG_871X_LEVEL(_drv_always_, "Loop index: %d :0x%02x\n", trycnt, mstatus);
trycnt--;
@ -1597,9 +1597,9 @@ static void SetHwReg8723BS(struct adapter *padapter, u8 variable, u8 *val)
if (mstatus & BIT1) {
DBG_871X_LEVEL(_drv_always_, "Disable WOW mode fail!!\n");
DBG_871X("Set 0x690 = 0x00\n");
rtw_write8(padapter, REG_WOW_CTRL, (rtw_read8(padapter, REG_WOW_CTRL)&0xf0));
rtw_write8(padapter, REG_WOW_CTRL, (rtw_read8(padapter, REG_WOW_CTRL) & 0xf0));
DBG_871X_LEVEL(_drv_always_, "Release RXDMA\n");
rtw_write32(padapter, REG_RXPKT_NUM, (rtw_read32(padapter, REG_RXPKT_NUM)&(~RW_RELEASE_EN)));
rtw_write32(padapter, REG_RXPKT_NUM, (rtw_read32(padapter, REG_RXPKT_NUM) & (~RW_RELEASE_EN)));
}
/* 3.1 read fw iv */
@ -1690,9 +1690,9 @@ static void SetHwReg8723BS(struct adapter *padapter, u8 variable, u8 *val)
/* 2. RX DMA stop */
DBG_871X_LEVEL(_drv_always_, "Pause DMA\n");
rtw_write32(padapter, REG_RXPKT_NUM,
(rtw_read32(padapter, REG_RXPKT_NUM)|RW_RELEASE_EN));
(rtw_read32(padapter, REG_RXPKT_NUM) | RW_RELEASE_EN));
do {
if ((rtw_read32(padapter, REG_RXPKT_NUM)&RXDMA_IDLE)) {
if ((rtw_read32(padapter, REG_RXPKT_NUM) & RXDMA_IDLE)) {
DBG_871X_LEVEL(_drv_always_, "RX_DMA_IDLE is true\n");
break;
} else {
@ -1726,7 +1726,7 @@ static void SetHwReg8723BS(struct adapter *padapter, u8 variable, u8 *val)
sdio_local_read(padapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
DBG_871X("DisableInterruptButCpwm28723BSdio(): Read SDIO_REG_HIMR: 0x%08x\n", tmp);
himr = cpu_to_le32(SDIO_HIMR_DISABLED)|SDIO_HIMR_CPWM2_MSK;
himr = cpu_to_le32(SDIO_HIMR_DISABLED) | SDIO_HIMR_CPWM2_MSK;
sdio_local_write(padapter, SDIO_REG_HIMR, 4, (u8 *)&himr);
sdio_local_read(padapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
@ -1792,7 +1792,7 @@ static void GetHwReg8723BS(struct adapter *padapter, u8 variable, u8 *val)
{
switch (variable) {
case HW_VAR_CPWM:
*val = rtw_read8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HCPWM1_8723B);
*val = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HCPWM1_8723B);
break;
case HW_VAR_FW_PS_STATE: