staging: comedi: addi_apci_3120: use amcc_s5933.h defines
Use the defines for the AMCC 5933 PCI controller registers and bits instead of creating private defines in this driver. Move the generic AGCSTS_TC_ENABLE define from this driver to the header. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -44,29 +44,13 @@ This program is distributed in the hope that it will be useful, but WITHOUT ANY
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* ADDON RELATED ADDITIONS
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*/
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/* Constant */
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#define APCI3120_ENABLE_TRANSFER_ADD_ON 0x12000000
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#define APCI3120_A2P_FIFO_MANAGEMENT 0x04000400L
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#define APCI3120_AMWEN_ENABLE 0x02
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#define APCI3120_A2P_FIFO_WRITE_ENABLE 0x01
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#define APCI3120_FIFO_ADVANCE_ON_BYTE_2 0x20000000L
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#define APCI3120_ENABLE_WRITE_TC_INT 0x00004000L
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#define APCI3120_CLEAR_WRITE_TC_INT 0x00040000L
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#define APCI3120_DISABLE_AMWEN_AND_A2P_FIFO_WRITE 0x0
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#define APCI3120_DISABLE_BUS_MASTER_ADD_ON 0x0
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#define APCI3120_DISABLE_BUS_MASTER_PCI 0x0
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/* ADD_ON ::: this needed since apci supports 16 bit interface to add on */
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#define APCI3120_ADD_ON_MWAR 0x24
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#define APCI3120_ADD_ON_AGCSTS 0x3c
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#define APCI3120_ADD_ON_MWTC 0x58
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/* AMCC */
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#define APCI3120_AMCC_OP_MCSR 0x3C
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#define APCI3120_AMCC_OP_REG_INTCSR 0x38
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/* for transfer count enable bit */
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#define AGCSTS_TC_ENABLE 0x10000000
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#define APCI3120_START 1
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#define APCI3120_STOP 0
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@ -128,10 +112,10 @@ static int apci3120_cancel(struct comedi_device *dev,
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/* Disable A2P Fifo write and AMWEN signal */
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outw(0, devpriv->addon + 4);
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/* Disable Bus Master ADD ON */
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apci3120_addon_write(dev, 0, APCI3120_ADD_ON_AGCSTS);
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/* Add-On - disable bus master */
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apci3120_addon_write(dev, 0, AMCC_OP_REG_AGCSTS);
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/* Disable BUS Master PCI */
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/* AMCC - disable bus master */
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outl(0, devpriv->amcc + AMCC_OP_REG_MCSR);
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/* disable all counters, ext trigger, and reset scan */
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@ -220,11 +204,11 @@ static int apci3120_ai_cmdtest(struct comedi_device *dev,
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static void apci3120_init_dma(struct comedi_device *dev,
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struct apci3120_dmabuf *dmabuf)
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{
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/* DMA Start Address */
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apci3120_addon_write(dev, dmabuf->hw, APCI3120_ADD_ON_MWAR);
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/* Add-On - DMA start address */
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apci3120_addon_write(dev, dmabuf->hw, AMCC_OP_REG_AMWAR);
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/* Nbr of acquisition */
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apci3120_addon_write(dev, dmabuf->use_size, APCI3120_ADD_ON_MWTC);
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/* Add-On - Number of acquisitions */
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apci3120_addon_write(dev, dmabuf->use_size, AMCC_OP_REG_AMWTC);
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}
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static void apci3120_setup_dma(struct comedi_device *dev,
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@ -277,70 +261,32 @@ static void apci3120_setup_dma(struct comedi_device *dev,
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/* Initialize DMA */
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/*
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* Set Transfer count enable bit and A2P_fifo reset bit in AGCSTS
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* register 1
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*/
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/* AMCC- enable transfer count and reset A2P FIFO */
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outl(AGCSTS_TC_ENABLE | AGCSTS_RESET_A2P_FIFO,
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devpriv->amcc + AMCC_OP_REG_AGCSTS);
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/* ENABLE BUS MASTER */
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apci3120_addon_write(dev, APCI3120_ENABLE_TRANSFER_ADD_ON,
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APCI3120_ADD_ON_AGCSTS);
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/* Add-On - enable transfer count and reset A2P FIFO */
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apci3120_addon_write(dev, AGCSTS_TC_ENABLE | AGCSTS_RESET_A2P_FIFO,
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AMCC_OP_REG_AGCSTS);
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/*
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* TO VERIFIED BEGIN JK 07.05.04: Comparison between WIN32 and Linux
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* driver
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*/
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outw(0x1000, devpriv->addon + 2);
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/* END JK 07.05.04: Comparison between WIN32 and Linux driver */
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/* 2 No change */
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/* A2P FIFO MANAGEMENT */
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/* A2P fifo reset & transfer control enable */
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outl(APCI3120_A2P_FIFO_MANAGEMENT,
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devpriv->amcc + APCI3120_AMCC_OP_MCSR);
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/* AMCC - enable transfers and reset A2P flags */
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outl(RESET_A2P_FLAGS | EN_A2P_TRANSFERS,
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devpriv->amcc + AMCC_OP_REG_MCSR);
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apci3120_init_dma(dev, dmabuf0);
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/*
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* 5
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* To configure A2P FIFO testing outl(
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* FIFO_ADVANCE_ON_BYTE_2, devpriv->amcc + AMCC_OP_REG_INTCSR);
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*/
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/* AMCC- reset A2P flags */
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outl(RESET_A2P_FLAGS, devpriv->amcc + AMCC_OP_REG_MCSR);
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/* A2P FIFO RESET */
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/*
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* TO VERIFY BEGIN JK 07.05.04: Comparison between WIN32 and Linux
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* driver
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*/
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outl(0x04000000UL, devpriv->amcc + AMCC_OP_REG_MCSR);
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/* END JK 07.05.04: Comparison between WIN32 and Linux driver */
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/*
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* 6
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* ENABLE A2P FIFO WRITE AND ENABLE AMWEN AMWEN_ENABLE |
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* A2P_FIFO_WRITE_ENABLE (0x01|0x02)=0x03
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*/
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/*
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* 7
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* initialise end of dma interrupt AINT_WRITE_COMPL =
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* ENABLE_WRITE_TC_INT(ADDI)
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*/
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/* A2P FIFO CONFIGURATE, END OF DMA intERRUPT INIT */
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outl(APCI3120_FIFO_ADVANCE_ON_BYTE_2 | APCI3120_ENABLE_WRITE_TC_INT,
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/* AMCC - enable write complete (DMA) and set FIFO advance */
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outl(APCI3120_FIFO_ADVANCE_ON_BYTE_2 | AINT_WRITE_COMPL,
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devpriv->amcc + AMCC_OP_REG_INTCSR);
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/* BEGIN JK 07.05.04: Comparison between WIN32 and Linux driver */
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/* ENABLE A2P FIFO WRITE AND ENABLE AMWEN */
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outw(3, devpriv->addon + 4);
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/* END JK 07.05.04: Comparison between WIN32 and Linux driver */
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/* A2P FIFO RESET */
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/* BEGIN JK 07.05.04: Comparison between WIN32 and Linux driver */
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outl(0x04000000UL, devpriv->amcc + APCI3120_AMCC_OP_MCSR);
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/* END JK 07.05.04: Comparison between WIN32 and Linux driver */
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/* AMCC- reset A2P flags */
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outl(RESET_A2P_FLAGS, devpriv->amcc + AMCC_OP_REG_MCSR);
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}
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static int apci3120_ai_cmd(struct comedi_device *dev,
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@ -354,9 +300,8 @@ static int apci3120_ai_cmd(struct comedi_device *dev,
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devpriv->mode = APCI3120_MODE_TIMER2_CLK_OSC |
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APCI3120_MODE_TIMER2_AS_TIMER;
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/* Clear Timer Write TC int */
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outl(APCI3120_CLEAR_WRITE_TC_INT,
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devpriv->amcc + APCI3120_AMCC_OP_REG_INTCSR);
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/* AMCC- Clear write complete interrupt (DMA) */
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outl(AINT_WT_COMPLETE, devpriv->amcc + AMCC_OP_REG_INTCSR);
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devpriv->ui_DmaActualBuffer = 0;
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@ -438,7 +383,6 @@ static void apci3120_interrupt_dma(int irq, void *d)
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struct comedi_cmd *cmd = &s->async->cmd;
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struct apci3120_dmabuf *dmabuf;
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unsigned int samplesinbuf;
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unsigned int ui_Tmp;
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dmabuf = &devpriv->dmabuf[devpriv->ui_DmaActualBuffer];
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@ -458,11 +402,14 @@ static void apci3120_interrupt_dma(int irq, void *d)
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next_dmabuf = &devpriv->dmabuf[1 - devpriv->ui_DmaActualBuffer];
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ui_Tmp = AGCSTS_TC_ENABLE | AGCSTS_RESET_A2P_FIFO;
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outl(ui_Tmp, devpriv->amcc + AMCC_OP_REG_AGCSTS);
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/* AMCC - enable transfer count and reset A2P FIFO */
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outl(AGCSTS_TC_ENABLE | AGCSTS_RESET_A2P_FIFO,
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devpriv->amcc + AMCC_OP_REG_AGCSTS);
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apci3120_addon_write(dev, APCI3120_ENABLE_TRANSFER_ADD_ON,
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APCI3120_ADD_ON_AGCSTS);
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/* Add-On - enable transfer count and reset A2P FIFO */
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apci3120_addon_write(dev,
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AGCSTS_TC_ENABLE | AGCSTS_RESET_A2P_FIFO,
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AMCC_OP_REG_AGCSTS);
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apci3120_init_dma(dev, next_dmabuf);
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@ -472,9 +419,9 @@ static void apci3120_interrupt_dma(int irq, void *d)
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* AMWEN_ENABLE | A2P_FIFO_WRITE_ENABLE (0x01|0x02)=0x03
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*/
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outw(3, devpriv->addon + 4);
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/* initialise end of dma interrupt AINT_WRITE_COMPL = ENABLE_WRITE_TC_INT(ADDI) */
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outl(APCI3120_FIFO_ADVANCE_ON_BYTE_2 |
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APCI3120_ENABLE_WRITE_TC_INT,
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/* AMCC - enable write complete (DMA) and set FIFO advance */
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outl(APCI3120_FIFO_ADVANCE_ON_BYTE_2 | AINT_WRITE_COMPL,
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devpriv->amcc + AMCC_OP_REG_INTCSR);
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}
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@ -493,20 +440,19 @@ static void apci3120_interrupt_dma(int irq, void *d)
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if (devpriv->b_DmaDoubleBuffer) { /* switch dma buffers */
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devpriv->ui_DmaActualBuffer = 1 - devpriv->ui_DmaActualBuffer;
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} else {
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/*
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* restart DMA if is not used double buffering
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* ADDED REINITIALISE THE DMA
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*/
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/* restart DMA if is not using double buffering */
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/* AMCC - enable transfer count and reset A2P FIFO */
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outl(AGCSTS_TC_ENABLE | AGCSTS_RESET_A2P_FIFO,
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devpriv->amcc + AMCC_OP_REG_AGCSTS);
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apci3120_addon_write(dev, APCI3120_ENABLE_TRANSFER_ADD_ON,
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APCI3120_ADD_ON_AGCSTS);
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/*
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* A2P FIFO MANAGEMENT
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* A2P fifo reset & transfer control enable
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*/
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outl(APCI3120_A2P_FIFO_MANAGEMENT,
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/* Add-On - enable transfer count and reset A2P FIFO */
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apci3120_addon_write(dev,
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AGCSTS_TC_ENABLE | AGCSTS_RESET_A2P_FIFO,
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AMCC_OP_REG_AGCSTS);
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/* AMCC - enable transfers and reset A2P flags */
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outl(RESET_A2P_FLAGS | EN_A2P_TRANSFERS,
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devpriv->amcc + AMCC_OP_REG_MCSR);
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apci3120_init_dma(dev, dmabuf);
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@ -517,9 +463,9 @@ static void apci3120_interrupt_dma(int irq, void *d)
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* AMWEN_ENABLE | A2P_FIFO_WRITE_ENABLE (0x01|0x02)=0x03
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*/
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outw(3, devpriv->addon + 4);
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/* initialise end of dma interrupt AINT_WRITE_COMPL = ENABLE_WRITE_TC_INT(ADDI) */
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outl(APCI3120_FIFO_ADVANCE_ON_BYTE_2 |
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APCI3120_ENABLE_WRITE_TC_INT,
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/* AMCC - enable write complete (DMA) and set FIFO advance */
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outl(APCI3120_FIFO_ADVANCE_ON_BYTE_2 | AINT_WRITE_COMPL,
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devpriv->amcc + AMCC_OP_REG_INTCSR);
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}
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}
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@ -542,7 +488,7 @@ static irqreturn_t apci3120_interrupt(int irq, void *d)
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return IRQ_NONE;
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}
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outl(int_amcc | 0x00ff0000, devpriv->amcc + AMCC_OP_REG_INTCSR);
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outl(int_amcc | AINT_INT_MASK, devpriv->amcc + AMCC_OP_REG_INTCSR);
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if (devpriv->ctrl & APCI3120_CTRL_EXT_TRIG)
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apci3120_exttrig_enable(dev, false);
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@ -604,9 +550,8 @@ static irqreturn_t apci3120_interrupt(int irq, void *d)
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}
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if (status & APCI3120_STATUS_AMCC_INT) {
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/* Clear Timer Write TC int */
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outl(APCI3120_CLEAR_WRITE_TC_INT,
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devpriv->amcc + APCI3120_AMCC_OP_REG_INTCSR);
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/* AMCC- Clear write complete interrupt (DMA) */
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outl(AINT_WT_COMPLETE, devpriv->amcc + AMCC_OP_REG_INTCSR);
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apci3120_clr_timer2_interrupt(dev);
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@ -110,6 +110,8 @@
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#define AGCSTS_TCZERO_MASK 0x000000c0
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#define AGCSTS_FIFO_ST_MASK 0x0000003f
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#define AGCSTS_TC_ENABLE 0x10000000
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#define AGCSTS_RESET_MBFLAGS 0x08000000
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#define AGCSTS_RESET_P2A_FIFO 0x04000000
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#define AGCSTS_RESET_A2P_FIFO 0x02000000
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