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mtd: nand: fsmc: reduce number of arguments of fsmc_nand_setup()

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In preparation for the introduction of support for using SDR timings
exposed by the NAND flash instead of hard-coded timings, this commit
reworks the fsmc_nand_setup() function to take a "struct fsmc_nand_data"
as argument, which already contains the I/O registers base address, bank
and bus width information.

The timings is also currently contained in the "struct fsmc_nand_data",
but we still pass it as a separate argument because the support for
using SDR timings will pass a different value.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This commit is contained in:
Thomas Petazzoni 2017-04-29 10:52:34 +02:00 committed by Boris Brezillon
parent 19d8ccc42b
commit 6335b509b2
1 changed files with 8 additions and 10 deletions
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18
drivers/mtd/nand/fsmc_nand.c
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@ -302,11 +302,13 @@ static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
* This routine initializes timing parameters related to NAND memory access in * This routine initializes timing parameters related to NAND memory access in
* FSMC registers * FSMC registers
*/ */
static void fsmc_nand_setup(void __iomem *regs, uint32_t bank, static void fsmc_nand_setup(struct fsmc_nand_data *host,
uint32_t busw, struct fsmc_nand_timings *timings) struct fsmc_nand_timings *timings)
{ {
uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON; uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
uint32_t tclr, tar, thiz, thold, twait, tset; uint32_t tclr, tar, thiz, thold, twait, tset;
unsigned int bank = host->bank;
void __iomem *regs = host->regs_va;
struct fsmc_nand_timings *tims; struct fsmc_nand_timings *tims;
struct fsmc_nand_timings default_timings = { struct fsmc_nand_timings default_timings = {
.tclr = FSMC_TCLR_1, .tclr = FSMC_TCLR_1,
@ -318,7 +320,7 @@ static void fsmc_nand_setup(void __iomem *regs, uint32_t bank,
}; };
if (timings) if (timings)
tims = timings; tims = host->dev_timings;
else else
tims = &default_timings; tims = &default_timings;
@ -329,7 +331,7 @@ static void fsmc_nand_setup(void __iomem *regs, uint32_t bank,
twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT; twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT;
tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT; tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
if (busw) if (host->nand.options & NAND_BUSWIDTH_16)
writel_relaxed(value | FSMC_DEVWID_16, writel_relaxed(value | FSMC_DEVWID_16,
FSMC_NAND_REG(regs, bank, PC)); FSMC_NAND_REG(regs, bank, PC));
else else
@ -933,9 +935,7 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
break; break;
} }
fsmc_nand_setup(host->regs_va, host->bank, fsmc_nand_setup(host, host->dev_timings);
nand->options & NAND_BUSWIDTH_16,
host->dev_timings);
if (AMBA_REV_BITS(host->pid) >= 8) { if (AMBA_REV_BITS(host->pid) >= 8) {
nand->ecc.read_page = fsmc_read_page_hwecc; nand->ecc.read_page = fsmc_read_page_hwecc;
@ -1073,9 +1073,7 @@ static int fsmc_nand_resume(struct device *dev)
struct fsmc_nand_data *host = dev_get_drvdata(dev); struct fsmc_nand_data *host = dev_get_drvdata(dev);
if (host) { if (host) {
clk_prepare_enable(host->clk); clk_prepare_enable(host->clk);
fsmc_nand_setup(host->regs_va, host->bank, fsmc_nand_setup(host, host->dev_timings);
host->nand.options & NAND_BUSWIDTH_16,
host->dev_timings);
} }
return 0; return 0;
} }