forked from Minki/linux
crypto: aspeed - add HACE crypto driver
Add HACE crypto driver to support symmetric-key encryption and decryption with multiple modes of operation. Signed-off-by: Neal Liu <neal_liu@aspeedtech.com> Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Reviewed-by: Dhananjay Phadke <dphadke@linux.microsoft.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Neal Liu
Herbert Xu
parent
c3708e6562
commit
62f58b1637
@ -30,3 +30,20 @@ config CRYPTO_DEV_ASPEED_HACE_HASH
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hash driver.
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Supports multiple message digest standards, including
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SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, and so on.
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config CRYPTO_DEV_ASPEED_HACE_CRYPTO
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bool "Enable Aspeed Hash & Crypto Engine (HACE) crypto"
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depends on CRYPTO_DEV_ASPEED
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select CRYPTO_ENGINE
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select CRYPTO_AES
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select CRYPTO_DES
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select CRYPTO_ECB
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select CRYPTO_CBC
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select CRYPTO_CFB
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select CRYPTO_OFB
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select CRYPTO_CTR
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help
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Select here to enable Aspeed Hash & Crypto Engine (HACE)
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crypto driver.
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Supports AES/DES symmetric-key encryption and decryption
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with ECB/CBC/CFB/OFB/CTR options.
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@ -1,6 +1,9 @@
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obj-$(CONFIG_CRYPTO_DEV_ASPEED) += aspeed_crypto.o
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aspeed_crypto-objs := aspeed-hace.o \
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$(hace-hash-y)
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aspeed_crypto-objs := aspeed-hace.o \
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$(hace-hash-y) \
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$(hace-crypto-y)
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obj-$(CONFIG_CRYPTO_DEV_ASPEED_HACE_HASH) += aspeed-hace-hash.o
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hace-hash-$(CONFIG_CRYPTO_DEV_ASPEED_HACE_HASH) := aspeed-hace-hash.o
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obj-$(CONFIG_CRYPTO_DEV_ASPEED_HACE_CRYPTO) += aspeed-hace-crypto.o
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hace-crypto-$(CONFIG_CRYPTO_DEV_ASPEED_HACE_CRYPTO) := aspeed-hace-crypto.o
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1135
drivers/crypto/aspeed/aspeed-hace-crypto.c
Normal file
1135
drivers/crypto/aspeed/aspeed-hace-crypto.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -25,6 +25,7 @@
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static irqreturn_t aspeed_hace_irq(int irq, void *dev)
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{
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struct aspeed_hace_dev *hace_dev = (struct aspeed_hace_dev *)dev;
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struct aspeed_engine_crypto *crypto_engine = &hace_dev->crypto_engine;
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struct aspeed_engine_hash *hash_engine = &hace_dev->hash_engine;
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u32 sts;
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@ -40,9 +41,24 @@ static irqreturn_t aspeed_hace_irq(int irq, void *dev)
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dev_warn(hace_dev->dev, "HASH no active requests.\n");
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}
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if (sts & HACE_CRYPTO_ISR) {
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if (crypto_engine->flags & CRYPTO_FLAGS_BUSY)
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tasklet_schedule(&crypto_engine->done_task);
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else
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dev_warn(hace_dev->dev, "CRYPTO no active requests.\n");
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}
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return IRQ_HANDLED;
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}
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static void aspeed_hace_crypto_done_task(unsigned long data)
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{
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struct aspeed_hace_dev *hace_dev = (struct aspeed_hace_dev *)data;
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struct aspeed_engine_crypto *crypto_engine = &hace_dev->crypto_engine;
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crypto_engine->resume(hace_dev);
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}
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static void aspeed_hace_hash_done_task(unsigned long data)
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{
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struct aspeed_hace_dev *hace_dev = (struct aspeed_hace_dev *)data;
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@ -56,6 +72,9 @@ static void aspeed_hace_register(struct aspeed_hace_dev *hace_dev)
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#ifdef CONFIG_CRYPTO_DEV_ASPEED_HACE_HASH
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aspeed_register_hace_hash_algs(hace_dev);
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#endif
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#ifdef CONFIG_CRYPTO_DEV_ASPEED_HACE_CRYPTO
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aspeed_register_hace_crypto_algs(hace_dev);
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#endif
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}
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static void aspeed_hace_unregister(struct aspeed_hace_dev *hace_dev)
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@ -63,6 +82,9 @@ static void aspeed_hace_unregister(struct aspeed_hace_dev *hace_dev)
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#ifdef CONFIG_CRYPTO_DEV_ASPEED_HACE_HASH
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aspeed_unregister_hace_hash_algs(hace_dev);
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#endif
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#ifdef CONFIG_CRYPTO_DEV_ASPEED_HACE_CRYPTO
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aspeed_unregister_hace_crypto_algs(hace_dev);
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#endif
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}
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static const struct of_device_id aspeed_hace_of_matches[] = {
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@ -73,6 +95,7 @@ static const struct of_device_id aspeed_hace_of_matches[] = {
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static int aspeed_hace_probe(struct platform_device *pdev)
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{
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struct aspeed_engine_crypto *crypto_engine;
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const struct of_device_id *hace_dev_id;
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struct aspeed_engine_hash *hash_engine;
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struct aspeed_hace_dev *hace_dev;
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@ -93,6 +116,7 @@ static int aspeed_hace_probe(struct platform_device *pdev)
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hace_dev->dev = &pdev->dev;
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hace_dev->version = (unsigned long)hace_dev_id->data;
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hash_engine = &hace_dev->hash_engine;
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crypto_engine = &hace_dev->crypto_engine;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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@ -146,6 +170,21 @@ static int aspeed_hace_probe(struct platform_device *pdev)
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tasklet_init(&hash_engine->done_task, aspeed_hace_hash_done_task,
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(unsigned long)hace_dev);
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/* Initialize crypto hardware engine structure for crypto */
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hace_dev->crypt_engine_crypto = crypto_engine_alloc_init(hace_dev->dev,
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true);
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if (!hace_dev->crypt_engine_crypto) {
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rc = -ENOMEM;
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goto err_engine_hash_start;
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}
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rc = crypto_engine_start(hace_dev->crypt_engine_crypto);
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if (rc)
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goto err_engine_crypto_start;
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tasklet_init(&crypto_engine->done_task, aspeed_hace_crypto_done_task,
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(unsigned long)hace_dev);
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/* Allocate DMA buffer for hash engine input used */
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hash_engine->ahash_src_addr =
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dmam_alloc_coherent(&pdev->dev,
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@ -155,7 +194,45 @@ static int aspeed_hace_probe(struct platform_device *pdev)
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if (!hash_engine->ahash_src_addr) {
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dev_err(&pdev->dev, "Failed to allocate dma buffer\n");
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rc = -ENOMEM;
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goto err_engine_hash_start;
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goto err_engine_crypto_start;
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}
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/* Allocate DMA buffer for crypto engine context used */
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crypto_engine->cipher_ctx =
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dmam_alloc_coherent(&pdev->dev,
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PAGE_SIZE,
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&crypto_engine->cipher_ctx_dma,
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GFP_KERNEL);
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if (!crypto_engine->cipher_ctx) {
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dev_err(&pdev->dev, "Failed to allocate cipher ctx dma\n");
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rc = -ENOMEM;
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goto err_engine_crypto_start;
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}
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/* Allocate DMA buffer for crypto engine input used */
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crypto_engine->cipher_addr =
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dmam_alloc_coherent(&pdev->dev,
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ASPEED_CRYPTO_SRC_DMA_BUF_LEN,
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&crypto_engine->cipher_dma_addr,
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GFP_KERNEL);
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if (!crypto_engine->cipher_addr) {
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dev_err(&pdev->dev, "Failed to allocate cipher addr dma\n");
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rc = -ENOMEM;
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goto err_engine_crypto_start;
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}
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/* Allocate DMA buffer for crypto engine output used */
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if (hace_dev->version == AST2600_VERSION) {
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crypto_engine->dst_sg_addr =
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dmam_alloc_coherent(&pdev->dev,
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ASPEED_CRYPTO_DST_DMA_BUF_LEN,
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&crypto_engine->dst_sg_dma_addr,
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GFP_KERNEL);
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if (!crypto_engine->dst_sg_addr) {
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dev_err(&pdev->dev, "Failed to allocate dst_sg dma\n");
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rc = -ENOMEM;
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goto err_engine_crypto_start;
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}
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}
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aspeed_hace_register(hace_dev);
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@ -164,6 +241,8 @@ static int aspeed_hace_probe(struct platform_device *pdev)
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return 0;
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err_engine_crypto_start:
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crypto_engine_exit(hace_dev->crypt_engine_crypto);
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err_engine_hash_start:
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crypto_engine_exit(hace_dev->crypt_engine_hash);
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clk_exit:
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@ -175,13 +254,16 @@ clk_exit:
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static int aspeed_hace_remove(struct platform_device *pdev)
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{
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struct aspeed_hace_dev *hace_dev = platform_get_drvdata(pdev);
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struct aspeed_engine_crypto *crypto_engine = &hace_dev->crypto_engine;
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struct aspeed_engine_hash *hash_engine = &hace_dev->hash_engine;
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aspeed_hace_unregister(hace_dev);
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crypto_engine_exit(hace_dev->crypt_engine_hash);
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crypto_engine_exit(hace_dev->crypt_engine_crypto);
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tasklet_kill(&hash_engine->done_task);
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tasklet_kill(&crypto_engine->done_task);
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clk_disable_unprepare(hace_dev->clk);
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@ -7,9 +7,12 @@
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#include <linux/err.h>
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#include <linux/fips.h>
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#include <linux/dma-mapping.h>
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#include <crypto/aes.h>
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#include <crypto/des.h>
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#include <crypto/scatterwalk.h>
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#include <crypto/internal/aead.h>
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#include <crypto/internal/akcipher.h>
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#include <crypto/internal/des.h>
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#include <crypto/internal/hash.h>
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#include <crypto/internal/kpp.h>
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#include <crypto/internal/skcipher.h>
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@ -24,15 +27,75 @@
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* HACE register definitions *
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* *
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* ***************************/
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#define ASPEED_HACE_SRC 0x00 /* Crypto Data Source Base Address Register */
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#define ASPEED_HACE_DEST 0x04 /* Crypto Data Destination Base Address Register */
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#define ASPEED_HACE_CONTEXT 0x08 /* Crypto Context Buffer Base Address Register */
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#define ASPEED_HACE_DATA_LEN 0x0C /* Crypto Data Length Register */
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#define ASPEED_HACE_CMD 0x10 /* Crypto Engine Command Register */
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/* G5 */
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#define ASPEED_HACE_TAG 0x18 /* HACE Tag Register */
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/* G6 */
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#define ASPEED_HACE_GCM_ADD_LEN 0x14 /* Crypto AES-GCM Additional Data Length Register */
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#define ASPEED_HACE_GCM_TAG_BASE_ADDR 0x18 /* Crypto AES-GCM Tag Write Buff Base Address Reg */
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#define ASPEED_HACE_STS 0x1C /* HACE Status Register */
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#define ASPEED_HACE_HASH_SRC 0x20 /* Hash Data Source Base Address Register */
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#define ASPEED_HACE_HASH_DIGEST_BUFF 0x24 /* Hash Digest Write Buffer Base Address Register */
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#define ASPEED_HACE_HASH_KEY_BUFF 0x28 /* Hash HMAC Key Buffer Base Address Register */
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#define ASPEED_HACE_HASH_DATA_LEN 0x2C /* Hash Data Length Register */
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#define ASPEED_HACE_HASH_CMD 0x30 /* Hash Engine Command Register */
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/* crypto cmd */
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#define HACE_CMD_SINGLE_DES 0
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#define HACE_CMD_TRIPLE_DES BIT(17)
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#define HACE_CMD_AES_SELECT 0
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#define HACE_CMD_DES_SELECT BIT(16)
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#define HACE_CMD_ISR_EN BIT(12)
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#define HACE_CMD_CONTEXT_SAVE_ENABLE (0)
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#define HACE_CMD_CONTEXT_SAVE_DISABLE BIT(9)
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#define HACE_CMD_AES (0)
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#define HACE_CMD_DES (0)
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#define HACE_CMD_RC4 BIT(8)
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#define HACE_CMD_DECRYPT (0)
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#define HACE_CMD_ENCRYPT BIT(7)
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#define HACE_CMD_ECB (0x0 << 4)
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#define HACE_CMD_CBC (0x1 << 4)
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#define HACE_CMD_CFB (0x2 << 4)
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#define HACE_CMD_OFB (0x3 << 4)
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#define HACE_CMD_CTR (0x4 << 4)
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#define HACE_CMD_OP_MODE_MASK (0x7 << 4)
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#define HACE_CMD_AES128 (0x0 << 2)
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#define HACE_CMD_AES192 (0x1 << 2)
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#define HACE_CMD_AES256 (0x2 << 2)
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#define HACE_CMD_OP_CASCADE (0x3)
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#define HACE_CMD_OP_INDEPENDENT (0x1)
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/* G5 */
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#define HACE_CMD_RI_WO_DATA_ENABLE (0)
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#define HACE_CMD_RI_WO_DATA_DISABLE BIT(11)
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#define HACE_CMD_CONTEXT_LOAD_ENABLE (0)
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#define HACE_CMD_CONTEXT_LOAD_DISABLE BIT(10)
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/* G6 */
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#define HACE_CMD_AES_KEY_FROM_OTP BIT(24)
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#define HACE_CMD_GHASH_TAG_XOR_EN BIT(23)
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#define HACE_CMD_GHASH_PAD_LEN_INV BIT(22)
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#define HACE_CMD_GCM_TAG_ADDR_SEL BIT(21)
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#define HACE_CMD_MBUS_REQ_SYNC_EN BIT(20)
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#define HACE_CMD_DES_SG_CTRL BIT(19)
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#define HACE_CMD_SRC_SG_CTRL BIT(18)
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#define HACE_CMD_CTR_IV_AES_96 (0x1 << 14)
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#define HACE_CMD_CTR_IV_DES_32 (0x1 << 14)
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#define HACE_CMD_CTR_IV_AES_64 (0x2 << 14)
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#define HACE_CMD_CTR_IV_AES_32 (0x3 << 14)
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#define HACE_CMD_AES_KEY_HW_EXP BIT(13)
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#define HACE_CMD_GCM (0x5 << 4)
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/* interrupt status reg */
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#define HACE_CRYPTO_ISR BIT(12)
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#define HACE_HASH_ISR BIT(9)
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#define HACE_HASH_BUSY BIT(0)
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@ -77,6 +140,9 @@
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#define ASPEED_HASH_SRC_DMA_BUF_LEN 0xa000
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#define ASPEED_HASH_QUEUE_LENGTH 50
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#define HACE_CMD_IV_REQUIRE (HACE_CMD_CBC | HACE_CMD_CFB | \
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HACE_CMD_OFB | HACE_CMD_CTR)
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struct aspeed_hace_dev;
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typedef int (*aspeed_hace_fn_t)(struct aspeed_hace_dev *);
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@ -147,6 +213,48 @@ struct aspeed_sham_reqctx {
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u64 digcnt[2];
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};
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struct aspeed_engine_crypto {
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struct tasklet_struct done_task;
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unsigned long flags;
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struct skcipher_request *req;
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/* context buffer */
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void *cipher_ctx;
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dma_addr_t cipher_ctx_dma;
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/* input buffer, could be single/scatter-gather lists */
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void *cipher_addr;
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dma_addr_t cipher_dma_addr;
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/* output buffer, only used in scatter-gather lists */
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void *dst_sg_addr;
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dma_addr_t dst_sg_dma_addr;
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/* callback func */
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aspeed_hace_fn_t resume;
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};
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struct aspeed_cipher_ctx {
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struct crypto_engine_ctx enginectx;
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struct aspeed_hace_dev *hace_dev;
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int key_len;
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u8 key[AES_MAX_KEYLENGTH];
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/* callback func */
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aspeed_hace_fn_t start;
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struct crypto_skcipher *fallback_tfm;
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};
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struct aspeed_cipher_reqctx {
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int enc_cmd;
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int src_nents;
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int dst_nents;
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struct skcipher_request fallback_req; /* keep at the end */
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};
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struct aspeed_hace_dev {
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void __iomem *regs;
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struct device *dev;
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@ -155,8 +263,10 @@ struct aspeed_hace_dev {
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unsigned long version;
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struct crypto_engine *crypt_engine_hash;
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struct crypto_engine *crypt_engine_crypto;
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struct aspeed_engine_hash hash_engine;
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struct aspeed_engine_crypto crypto_engine;
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};
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struct aspeed_hace_alg {
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@ -182,5 +292,7 @@ enum aspeed_version {
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void aspeed_register_hace_hash_algs(struct aspeed_hace_dev *hace_dev);
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void aspeed_unregister_hace_hash_algs(struct aspeed_hace_dev *hace_dev);
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void aspeed_register_hace_crypto_algs(struct aspeed_hace_dev *hace_dev);
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void aspeed_unregister_hace_crypto_algs(struct aspeed_hace_dev *hace_dev);
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#endif
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