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drm/amdgpu: implement PRT for GFX7 v2

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Enable/disable the handling globally for now and
print a warning when we enable it for the first time.

v2: set correct register

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Christian König 2017-01-18 13:37:21 +01:00 committed by Alex Deucher
parent f7c35abe93
commit 62cd91f99e
1 changed files with 57 additions and 0 deletions
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57
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
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@ -480,6 +480,62 @@ static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev,
WREG32(mmVM_CONTEXT1_CNTL, tmp);
}
/**
* gmc_v7_0_set_prt - set PRT VM fault
*
* @adev: amdgpu_device pointer
* @enable: enable/disable VM fault handling for PRT
*/
static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable)
{
uint32_t tmp;
if (enable && !adev->mc.prt_warning) {
dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
adev->mc.prt_warning = true;
}
tmp = RREG32(mmVM_PRT_CNTL);
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
L2_CACHE_STORE_INVALID_ENTRIES, enable);
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
L1_TLB_STORE_INVALID_ENTRIES, enable);
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
MASK_PDE0_FAULT, enable);
WREG32(mmVM_PRT_CNTL, tmp);
if (enable) {
uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
uint32_t high = adev->vm_manager.max_pfn;
WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
} else {
WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
}
}
/**
* gmc_v7_0_gart_enable - gart enable
*
@ -1259,6 +1315,7 @@ static const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
static const struct amdgpu_gart_funcs gmc_v7_0_gart_funcs = {
.flush_gpu_tlb = gmc_v7_0_gart_flush_gpu_tlb,
.set_pte_pde = gmc_v7_0_gart_set_pte_pde,
.set_prt = gmc_v7_0_set_prt,
};
static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = {