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ravb: Add tx and rx clock internal delays mode of APSR

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This patch enables tx and rx clock internal delay modes (TDM and RDM).

This is to address a failure in the case of 1Gbps communication using the
by salvator-x board with the KSZ9031RNX phy. This has been reported to
occur with both the r8a7795 (H3) and r8a7796 (M3-W) SoCs.

With this change APSR internal delay modes are enabled for
"rgmii-id", "rgmii-rxid" and "rgmii-txid" phy modes as follows:

phy mode   | ASPR delay mode
-----------+----------------
rgmii-id   | TDM and RDM
rgmii-rxid | RDM
rgmii-txid | TDM

Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Kazuya Mizuguchi 2017-01-27 20:46:26 +01:00 committed by David S. Miller
parent 1a28242bac
commit 61fccb2d62
2 changed files with 33 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/net/ethernet/renesas/ravb.h
View File

@ -76,6 +76,7 @@ enum ravb_reg {
CDAR20 = 0x0060, CDAR20 = 0x0060,
CDAR21 = 0x0064, CDAR21 = 0x0064,
ESR = 0x0088, ESR = 0x0088,
APSR = 0x008C, /* R-Car Gen3 only */
RCR = 0x0090, RCR = 0x0090,
RQC0 = 0x0094, RQC0 = 0x0094,
RQC1 = 0x0098, RQC1 = 0x0098,
@ -248,6 +249,15 @@ enum ESR_BIT {
ESR_EIL = 0x00001000, ESR_EIL = 0x00001000,
}; };
/* APSR */
enum APSR_BIT {
APSR_MEMS = 0x00000002,
APSR_CMSW = 0x00000010,
APSR_DM = 0x00006000, /* Undocumented? */
APSR_DM_RDM = 0x00002000,
APSR_DM_TDM = 0x00004000,
};
/* RCR */ /* RCR */
enum RCR_BIT { enum RCR_BIT {
RCR_EFFS = 0x00000001, RCR_EFFS = 0x00000001,

23
drivers/net/ethernet/renesas/ravb_main.c
View File

@ -1920,6 +1920,23 @@ static void ravb_set_config_mode(struct net_device *ndev)
} }
} }
/* Set tx and rx clock internal delay modes */
static void ravb_set_delay_mode(struct net_device *ndev)
{
struct ravb_private *priv = netdev_priv(ndev);
int set = 0;
if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID)
set |= APSR_DM_RDM;
if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
set |= APSR_DM_TDM;
ravb_modify(ndev, APSR, APSR_DM, set);
}
static int ravb_probe(struct platform_device *pdev) static int ravb_probe(struct platform_device *pdev)
{ {
struct device_node *np = pdev->dev.of_node; struct device_node *np = pdev->dev.of_node;
@ -2032,6 +2049,9 @@ static int ravb_probe(struct platform_device *pdev)
/* Request GTI loading */ /* Request GTI loading */
ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
if (priv->chip_id != RCAR_GEN2)
ravb_set_delay_mode(ndev);
/* Allocate descriptor base address table */ /* Allocate descriptor base address table */
priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM;
priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size,
@ -2168,6 +2188,9 @@ static int __maybe_unused ravb_resume(struct device *dev)
/* Request GTI loading */ /* Request GTI loading */
ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
if (priv->chip_id != RCAR_GEN2)
ravb_set_delay_mode(ndev);
/* Restore descriptor base address table */ /* Restore descriptor base address table */
ravb_write(ndev, priv->desc_bat_dma, DBAT); ravb_write(ndev, priv->desc_bat_dma, DBAT);