extcon fixes for 3.9-rc3
This is small fixes against 3.9-rc2. Fix to max77693 extcon driver: - Set default value of MUIC register to bring up it. Fix to max8997 extcon driver: - Fix null pointer error duing probe when platform data isn't used. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJRQDzoAAoJEJzN3yze689TprQP+gPvd2I2LLl/Sq42UyhtzIlk MlDIXk/4mHLeDycsTEq6RlDHmA2mXznpnXd0lyIBrD4VJqie9RQsd2TMJ560QeBd PJPaQwruAcKnRBh6BdVRNGE9wZvZYEaXOl6tB0QHbldrqfA6lU3WzOd4lzw7dnNw a+nFkhvLUraIHAlvjGMlH5ZEhobuKpsOyWSpznI1M5MsvxgPoEL4Vzbq5/QJBVVD R5x9tZ+Fb0PM1IexwDpBzxuTMGua0XJsrKCZ3FZExy5LcIb1etnELmacwPNkr0XX N06ZwJyQWiG4TpRvYOhhpWbhHwlGLu2tTtfvg+TipeN+bjFarExeg7IiReNiz2Sg mig+5R8BMAXMMcaC7l1erzaOPrUJDrBdd57pBGCx3eYIW1OeHJ1apTKKKaFXTqdr w19Y4j379breQMIk41KaFhZcWidgt37qxxKpreaM8XowJBhrrFFUSOvDTWhCBxq6 AUIWtP5kCUPynivkpm7S6f0N2nSdtRVQTpVGUwORxPCt3tMXErWDC2Hd+8GTioXC 9i3pFmbOHB60WEaTIr1wHFWCX+vnU8pWk6TPt/NSF9vScZxKUnNw0inOv/fsqyVM D8vTNYrjyq9ES21jmmIcYCtS1Ue7D+aj0t6f0YNxrsslaq/k5AKMI2xtg+q4HPTI lhCd46ALukPKHIxs1oc+ =XVHH -----END PGP SIGNATURE----- Merge tag 'extcon-3.9-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/extcon into char-misc-linus Chanwoo writes: extcon fixes for 3.9-rc3 This is small fixes against 3.9-rc2. Fix to max77693 extcon driver: - Set default value of MUIC register to bring up it. Fix to max8997 extcon driver: - Fix null pointer error duing probe when platform data isn't used.
This commit is contained in:
Greg Kroah-Hartman
commit
61ec7e77d7
@ -32,6 +32,38 @@
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#define DEV_NAME "max77693-muic"
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#define DELAY_MS_DEFAULT 20000 /* unit: millisecond */
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/*
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* Default value of MAX77693 register to bring up MUIC device.
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* If user don't set some initial value for MUIC device through platform data,
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* extcon-max77693 driver use 'default_init_data' to bring up base operation
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* of MAX77693 MUIC device.
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*/
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struct max77693_reg_data default_init_data[] = {
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{
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/* STATUS2 - [3]ChgDetRun */
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.addr = MAX77693_MUIC_REG_STATUS2,
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.data = STATUS2_CHGDETRUN_MASK,
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}, {
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/* INTMASK1 - Unmask [3]ADC1KM,[0]ADCM */
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.addr = MAX77693_MUIC_REG_INTMASK1,
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.data = INTMASK1_ADC1K_MASK
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| INTMASK1_ADC_MASK,
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}, {
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/* INTMASK2 - Unmask [0]ChgTypM */
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.addr = MAX77693_MUIC_REG_INTMASK2,
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.data = INTMASK2_CHGTYP_MASK,
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}, {
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/* INTMASK3 - Mask all of interrupts */
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.addr = MAX77693_MUIC_REG_INTMASK3,
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.data = 0x0,
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}, {
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/* CDETCTRL2 */
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.addr = MAX77693_MUIC_REG_CDETCTRL2,
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.data = CDETCTRL2_VIDRMEN_MASK
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| CDETCTRL2_DXOVPEN_MASK,
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},
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};
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enum max77693_muic_adc_debounce_time {
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ADC_DEBOUNCE_TIME_5MS = 0,
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ADC_DEBOUNCE_TIME_10MS,
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@ -1045,8 +1077,9 @@ static int max77693_muic_probe(struct platform_device *pdev)
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{
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struct max77693_dev *max77693 = dev_get_drvdata(pdev->dev.parent);
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struct max77693_platform_data *pdata = dev_get_platdata(max77693->dev);
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struct max77693_muic_platform_data *muic_pdata = pdata->muic_data;
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struct max77693_muic_info *info;
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struct max77693_reg_data *init_data;
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int num_init_data;
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int delay_jiffies;
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int ret;
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int i;
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@ -1145,15 +1178,25 @@ static int max77693_muic_probe(struct platform_device *pdev)
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goto err_irq;
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}
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/* Initialize MUIC register by using platform data */
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for (i = 0 ; i < muic_pdata->num_init_data ; i++) {
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enum max77693_irq_source irq_src = MAX77693_IRQ_GROUP_NR;
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/* Initialize MUIC register by using platform data or default data */
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if (pdata->muic_data) {
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init_data = pdata->muic_data->init_data;
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num_init_data = pdata->muic_data->num_init_data;
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} else {
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init_data = default_init_data;
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num_init_data = ARRAY_SIZE(default_init_data);
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}
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for (i = 0 ; i < num_init_data ; i++) {
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enum max77693_irq_source irq_src
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= MAX77693_IRQ_GROUP_NR;
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max77693_write_reg(info->max77693->regmap_muic,
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muic_pdata->init_data[i].addr,
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muic_pdata->init_data[i].data);
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init_data[i].addr,
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init_data[i].data);
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switch (muic_pdata->init_data[i].addr) {
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switch (init_data[i].addr) {
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case MAX77693_MUIC_REG_INTMASK1:
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irq_src = MUIC_INT1;
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break;
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@ -1167,22 +1210,40 @@ static int max77693_muic_probe(struct platform_device *pdev)
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if (irq_src < MAX77693_IRQ_GROUP_NR)
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info->max77693->irq_masks_cur[irq_src]
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= muic_pdata->init_data[i].data;
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= init_data[i].data;
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}
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/*
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* Default usb/uart path whether UART/USB or AUX_UART/AUX_USB
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* h/w path of COMP2/COMN1 on CONTROL1 register.
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*/
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if (muic_pdata->path_uart)
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info->path_uart = muic_pdata->path_uart;
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else
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info->path_uart = CONTROL1_SW_UART;
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if (pdata->muic_data) {
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struct max77693_muic_platform_data *muic_pdata = pdata->muic_data;
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if (muic_pdata->path_usb)
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info->path_usb = muic_pdata->path_usb;
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else
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/*
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* Default usb/uart path whether UART/USB or AUX_UART/AUX_USB
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* h/w path of COMP2/COMN1 on CONTROL1 register.
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*/
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if (muic_pdata->path_uart)
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info->path_uart = muic_pdata->path_uart;
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else
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info->path_uart = CONTROL1_SW_UART;
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if (muic_pdata->path_usb)
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info->path_usb = muic_pdata->path_usb;
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else
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info->path_usb = CONTROL1_SW_USB;
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/*
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* Default delay time for detecting cable state
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* after certain time.
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*/
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if (muic_pdata->detcable_delay_ms)
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delay_jiffies =
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msecs_to_jiffies(muic_pdata->detcable_delay_ms);
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else
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delay_jiffies = msecs_to_jiffies(DELAY_MS_DEFAULT);
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} else {
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info->path_usb = CONTROL1_SW_USB;
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info->path_uart = CONTROL1_SW_UART;
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delay_jiffies = msecs_to_jiffies(DELAY_MS_DEFAULT);
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}
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/* Set initial path for UART */
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max77693_muic_set_path(info, info->path_uart, true);
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@ -1208,10 +1269,6 @@ static int max77693_muic_probe(struct platform_device *pdev)
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* driver should notify cable state to upper layer.
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*/
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INIT_DELAYED_WORK(&info->wq_detcable, max77693_muic_detect_cable_wq);
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if (muic_pdata->detcable_delay_ms)
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delay_jiffies = msecs_to_jiffies(muic_pdata->detcable_delay_ms);
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else
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delay_jiffies = msecs_to_jiffies(DELAY_MS_DEFAULT);
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schedule_delayed_work(&info->wq_detcable, delay_jiffies);
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return ret;
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@ -712,29 +712,45 @@ static int max8997_muic_probe(struct platform_device *pdev)
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goto err_irq;
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}
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/* Initialize registers according to platform data */
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if (pdata->muic_pdata) {
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struct max8997_muic_platform_data *mdata = info->muic_pdata;
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struct max8997_muic_platform_data *muic_pdata
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= pdata->muic_pdata;
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for (i = 0; i < mdata->num_init_data; i++) {
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max8997_write_reg(info->muic, mdata->init_data[i].addr,
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mdata->init_data[i].data);
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/* Initialize registers according to platform data */
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for (i = 0; i < muic_pdata->num_init_data; i++) {
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max8997_write_reg(info->muic,
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muic_pdata->init_data[i].addr,
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muic_pdata->init_data[i].data);
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}
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}
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/*
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* Default usb/uart path whether UART/USB or AUX_UART/AUX_USB
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* h/w path of COMP2/COMN1 on CONTROL1 register.
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*/
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if (pdata->muic_pdata->path_uart)
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info->path_uart = pdata->muic_pdata->path_uart;
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else
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/*
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* Default usb/uart path whether UART/USB or AUX_UART/AUX_USB
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* h/w path of COMP2/COMN1 on CONTROL1 register.
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*/
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if (muic_pdata->path_uart)
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info->path_uart = muic_pdata->path_uart;
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else
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info->path_uart = CONTROL1_SW_UART;
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if (muic_pdata->path_usb)
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info->path_usb = muic_pdata->path_usb;
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else
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info->path_usb = CONTROL1_SW_USB;
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/*
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* Default delay time for detecting cable state
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* after certain time.
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*/
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if (muic_pdata->detcable_delay_ms)
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delay_jiffies =
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msecs_to_jiffies(muic_pdata->detcable_delay_ms);
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else
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delay_jiffies = msecs_to_jiffies(DELAY_MS_DEFAULT);
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} else {
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info->path_uart = CONTROL1_SW_UART;
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if (pdata->muic_pdata->path_usb)
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info->path_usb = pdata->muic_pdata->path_usb;
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else
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info->path_usb = CONTROL1_SW_USB;
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delay_jiffies = msecs_to_jiffies(DELAY_MS_DEFAULT);
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}
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/* Set initial path for UART */
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max8997_muic_set_path(info, info->path_uart, true);
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@ -751,10 +767,6 @@ static int max8997_muic_probe(struct platform_device *pdev)
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* driver should notify cable state to upper layer.
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*/
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INIT_DELAYED_WORK(&info->wq_detcable, max8997_muic_detect_cable_wq);
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if (pdata->muic_pdata->detcable_delay_ms)
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delay_jiffies = msecs_to_jiffies(pdata->muic_pdata->detcable_delay_ms);
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else
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delay_jiffies = msecs_to_jiffies(DELAY_MS_DEFAULT);
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schedule_delayed_work(&info->wq_detcable, delay_jiffies);
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return 0;
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@ -106,6 +106,29 @@ enum max77693_muic_reg {
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MAX77693_MUIC_REG_END,
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};
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/* MAX77693 INTMASK1~2 Register */
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#define INTMASK1_ADC1K_SHIFT 3
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#define INTMASK1_ADCERR_SHIFT 2
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#define INTMASK1_ADCLOW_SHIFT 1
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#define INTMASK1_ADC_SHIFT 0
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#define INTMASK1_ADC1K_MASK (1 << INTMASK1_ADC1K_SHIFT)
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#define INTMASK1_ADCERR_MASK (1 << INTMASK1_ADCERR_SHIFT)
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#define INTMASK1_ADCLOW_MASK (1 << INTMASK1_ADCLOW_SHIFT)
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#define INTMASK1_ADC_MASK (1 << INTMASK1_ADC_SHIFT)
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#define INTMASK2_VIDRM_SHIFT 5
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#define INTMASK2_VBVOLT_SHIFT 4
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#define INTMASK2_DXOVP_SHIFT 3
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#define INTMASK2_DCDTMR_SHIFT 2
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#define INTMASK2_CHGDETRUN_SHIFT 1
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#define INTMASK2_CHGTYP_SHIFT 0
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#define INTMASK2_VIDRM_MASK (1 << INTMASK2_VIDRM_SHIFT)
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#define INTMASK2_VBVOLT_MASK (1 << INTMASK2_VBVOLT_SHIFT)
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#define INTMASK2_DXOVP_MASK (1 << INTMASK2_DXOVP_SHIFT)
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#define INTMASK2_DCDTMR_MASK (1 << INTMASK2_DCDTMR_SHIFT)
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#define INTMASK2_CHGDETRUN_MASK (1 << INTMASK2_CHGDETRUN_SHIFT)
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#define INTMASK2_CHGTYP_MASK (1 << INTMASK2_CHGTYP_SHIFT)
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/* MAX77693 MUIC - STATUS1~3 Register */
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#define STATUS1_ADC_SHIFT (0)
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#define STATUS1_ADCLOW_SHIFT (5)
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