drm/amd/display: dc/irq: add support for DCE6 (v4)
[Why]
irq service requires changes for DCE6 support
[How]
(v1) DCE6 targets are added replicating existing DCE8 implementation.
due to missing CRTC_VERTICAL_INTERRUPT0_CONTROL registers/masks,
dce/dce_8_0_{d,sh_mask}.h used instead of dce/dce_6_0_{d,sh_mask}.h
(v2) DCE6 headers used adding the necessary vblank irq registers
(INT_MASK and VBLANK_STATUS) and vblank irq masks as implemented
in amdgpu driver.
Add vblank_irq_info_funcs_dce60 with .set and .ack as per commit
b10d51f ("drm/amd/display: Add interrupt entries for VBLANK isr.")
and use it in vblank_int_entry(reg_num) macro definition
(v3) updated due to following kernel 5.3 commit:
4fc4dca ("drm/amd: drop use of drmp.h in os_types.h")
(v4) updated due to following kernel 5.6 commit:
d9e3267 ("drm/amd/display: cleanup of construct and destruct funcs")
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Mauro Rossi
Alex Deucher
parent
b168930d68
commit
61bf32937b
@ -30,6 +30,17 @@ AMD_DAL_IRQ = $(addprefix $(AMDDALPATH)/dc/irq/,$(IRQ))
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AMD_DISPLAY_FILES += $(AMD_DAL_IRQ)
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###############################################################################
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# DCE 6x
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###############################################################################
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ifdef CONFIG_DRM_AMD_DC_SI
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IRQ_DCE60 = irq_service_dce60.o
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AMD_DAL_IRQ_DCE60 = $(addprefix $(AMDDALPATH)/dc/irq/dce60/,$(IRQ_DCE60))
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AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCE60)
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endif
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###############################################################################
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# DCE 8x
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###############################################################################
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395
drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
Normal file
395
drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
Normal file
@ -0,0 +1,395 @@
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/*
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* Copyright 2020 Mauro Rossi <issor.oruam@gmail.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include <linux/slab.h>
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#include "dm_services.h"
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#include "include/logger_interface.h"
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#include "irq_service_dce60.h"
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#include "../dce110/irq_service_dce110.h"
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#include "dce/dce_6_0_d.h"
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#include "dce/dce_6_0_sh_mask.h"
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#include "ivsrcid/ivsrcid_vislands30.h"
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#define VISLANDS30_IV_SRCID_D1_VBLANK 1
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#define VISLANDS30_IV_SRCID_D2_VBLANK 2
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#define VISLANDS30_IV_SRCID_D3_VBLANK 3
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#define VISLANDS30_IV_SRCID_D4_VBLANK 4
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#define VISLANDS30_IV_SRCID_D5_VBLANK 5
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#define VISLANDS30_IV_SRCID_D6_VBLANK 6
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#include "dc_types.h"
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static bool hpd_ack(
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struct irq_service *irq_service,
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const struct irq_source_info *info)
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{
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uint32_t addr = info->status_reg;
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uint32_t value = dm_read_reg(irq_service->ctx, addr);
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uint32_t current_status =
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get_reg_field_value(
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value,
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DC_HPD1_INT_STATUS,
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DC_HPD1_SENSE_DELAYED);
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dal_irq_service_ack_generic(irq_service, info);
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value = dm_read_reg(irq_service->ctx, info->enable_reg);
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set_reg_field_value(
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value,
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current_status ? 0 : 1,
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DC_HPD1_INT_CONTROL,
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DC_HPD1_INT_POLARITY);
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dm_write_reg(irq_service->ctx, info->enable_reg, value);
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return true;
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}
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static const struct irq_source_info_funcs hpd_irq_info_funcs = {
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.set = NULL,
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.ack = hpd_ack
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};
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static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
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.set = NULL,
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.ack = NULL
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};
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static const struct irq_source_info_funcs pflip_irq_info_funcs = {
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.set = NULL,
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.ack = NULL
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};
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static const struct irq_source_info_funcs vblank_irq_info_funcs = {
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.set = dce110_vblank_set,
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.ack = NULL
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};
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static const struct irq_source_info_funcs vblank_irq_info_funcs_dce60 = {
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.set = NULL,
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.ack = NULL
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};
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#define hpd_int_entry(reg_num)\
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[DC_IRQ_SOURCE_INVALID + reg_num] = {\
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.enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
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.enable_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK,\
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.enable_value = {\
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DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK,\
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~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK\
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},\
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.ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
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.ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK,\
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.ack_value = DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK,\
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.status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
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.funcs = &hpd_irq_info_funcs\
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}
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#define hpd_rx_int_entry(reg_num)\
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[DC_IRQ_SOURCE_HPD6 + reg_num] = {\
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.enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
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.enable_mask = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK,\
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.enable_value = {\
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DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK,\
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~DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK },\
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.ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
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.ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK,\
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.ack_value = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK,\
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.status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
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.funcs = &hpd_rx_irq_info_funcs\
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}
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#define pflip_int_entry(reg_num)\
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[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
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.enable_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_CONTROL,\
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.enable_mask =\
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GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
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.enable_value = {\
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GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
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~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK},\
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.ack_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_STATUS,\
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.ack_mask = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
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.ack_value = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
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.status_reg = mmDCP ## reg_num ##_GRPH_INTERRUPT_STATUS,\
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.funcs = &pflip_irq_info_funcs\
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}
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#define vupdate_int_entry(reg_num)\
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[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
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.enable_reg = mmCRTC ## reg_num ## _CRTC_INTERRUPT_CONTROL,\
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.enable_mask =\
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CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
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.enable_value = {\
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CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
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~CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK},\
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.ack_reg = mmCRTC ## reg_num ## _CRTC_V_UPDATE_INT_STATUS,\
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.ack_mask =\
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CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
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.ack_value =\
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CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
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.funcs = &vblank_irq_info_funcs\
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}
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#define vblank_int_entry(reg_num)\
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[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
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.enable_reg = mmLB ## reg_num ## _INT_MASK,\
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.enable_mask =\
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INT_MASK__VBLANK_INT_MASK,\
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.enable_value = {\
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INT_MASK__VBLANK_INT_MASK,\
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~INT_MASK__VBLANK_INT_MASK},\
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.ack_reg = mmLB ## reg_num ## _VBLANK_STATUS,\
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.ack_mask =\
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VBLANK_STATUS__VBLANK_ACK_MASK,\
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.ack_value =\
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VBLANK_STATUS__VBLANK_ACK_MASK,\
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.funcs = &vblank_irq_info_funcs_dce60\
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}
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#define dummy_irq_entry() \
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{\
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.funcs = &dummy_irq_info_funcs\
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}
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#define i2c_int_entry(reg_num) \
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[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
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#define dp_sink_int_entry(reg_num) \
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[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
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#define gpio_pad_int_entry(reg_num) \
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[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
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#define dc_underflow_int_entry(reg_num) \
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[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
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static const struct irq_source_info_funcs dummy_irq_info_funcs = {
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.set = dal_irq_service_dummy_set,
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.ack = dal_irq_service_dummy_ack
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};
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static const struct irq_source_info
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irq_source_info_dce60[DAL_IRQ_SOURCES_NUMBER] = {
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[DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
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hpd_int_entry(1),
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hpd_int_entry(2),
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hpd_int_entry(3),
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hpd_int_entry(4),
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hpd_int_entry(5),
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hpd_int_entry(6),
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hpd_rx_int_entry(1),
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hpd_rx_int_entry(2),
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hpd_rx_int_entry(3),
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hpd_rx_int_entry(4),
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hpd_rx_int_entry(5),
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hpd_rx_int_entry(6),
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i2c_int_entry(1),
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i2c_int_entry(2),
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i2c_int_entry(3),
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i2c_int_entry(4),
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i2c_int_entry(5),
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i2c_int_entry(6),
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dp_sink_int_entry(1),
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dp_sink_int_entry(2),
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dp_sink_int_entry(3),
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dp_sink_int_entry(4),
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dp_sink_int_entry(5),
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dp_sink_int_entry(6),
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[DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
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pflip_int_entry(0),
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pflip_int_entry(1),
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pflip_int_entry(2),
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pflip_int_entry(3),
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pflip_int_entry(4),
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pflip_int_entry(5),
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[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
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gpio_pad_int_entry(0),
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gpio_pad_int_entry(1),
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gpio_pad_int_entry(2),
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gpio_pad_int_entry(3),
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gpio_pad_int_entry(4),
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gpio_pad_int_entry(5),
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gpio_pad_int_entry(6),
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gpio_pad_int_entry(7),
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gpio_pad_int_entry(8),
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gpio_pad_int_entry(9),
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gpio_pad_int_entry(10),
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gpio_pad_int_entry(11),
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gpio_pad_int_entry(12),
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gpio_pad_int_entry(13),
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gpio_pad_int_entry(14),
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gpio_pad_int_entry(15),
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gpio_pad_int_entry(16),
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gpio_pad_int_entry(17),
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gpio_pad_int_entry(18),
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gpio_pad_int_entry(19),
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gpio_pad_int_entry(20),
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gpio_pad_int_entry(21),
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gpio_pad_int_entry(22),
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gpio_pad_int_entry(23),
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gpio_pad_int_entry(24),
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gpio_pad_int_entry(25),
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gpio_pad_int_entry(26),
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gpio_pad_int_entry(27),
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gpio_pad_int_entry(28),
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gpio_pad_int_entry(29),
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gpio_pad_int_entry(30),
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dc_underflow_int_entry(1),
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dc_underflow_int_entry(2),
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dc_underflow_int_entry(3),
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dc_underflow_int_entry(4),
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dc_underflow_int_entry(5),
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dc_underflow_int_entry(6),
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[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
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[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
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vupdate_int_entry(0),
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vupdate_int_entry(1),
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vupdate_int_entry(2),
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vupdate_int_entry(3),
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vupdate_int_entry(4),
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vupdate_int_entry(5),
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vblank_int_entry(0),
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vblank_int_entry(1),
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vblank_int_entry(2),
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vblank_int_entry(3),
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vblank_int_entry(4),
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vblank_int_entry(5),
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};
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enum dc_irq_source to_dal_irq_source_dce60(
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struct irq_service *irq_service,
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uint32_t src_id,
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uint32_t ext_id)
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{
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switch (src_id) {
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case VISLANDS30_IV_SRCID_D1_VBLANK:
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return DC_IRQ_SOURCE_VBLANK1;
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case VISLANDS30_IV_SRCID_D2_VBLANK:
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return DC_IRQ_SOURCE_VBLANK2;
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case VISLANDS30_IV_SRCID_D3_VBLANK:
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return DC_IRQ_SOURCE_VBLANK3;
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case VISLANDS30_IV_SRCID_D4_VBLANK:
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return DC_IRQ_SOURCE_VBLANK4;
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case VISLANDS30_IV_SRCID_D5_VBLANK:
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return DC_IRQ_SOURCE_VBLANK5;
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case VISLANDS30_IV_SRCID_D6_VBLANK:
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return DC_IRQ_SOURCE_VBLANK6;
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case VISLANDS30_IV_SRCID_D1_V_UPDATE_INT:
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return DC_IRQ_SOURCE_VUPDATE1;
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case VISLANDS30_IV_SRCID_D2_V_UPDATE_INT:
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return DC_IRQ_SOURCE_VUPDATE2;
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case VISLANDS30_IV_SRCID_D3_V_UPDATE_INT:
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return DC_IRQ_SOURCE_VUPDATE3;
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case VISLANDS30_IV_SRCID_D4_V_UPDATE_INT:
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return DC_IRQ_SOURCE_VUPDATE4;
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case VISLANDS30_IV_SRCID_D5_V_UPDATE_INT:
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return DC_IRQ_SOURCE_VUPDATE5;
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case VISLANDS30_IV_SRCID_D6_V_UPDATE_INT:
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return DC_IRQ_SOURCE_VUPDATE6;
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case VISLANDS30_IV_SRCID_D1_GRPH_PFLIP:
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return DC_IRQ_SOURCE_PFLIP1;
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case VISLANDS30_IV_SRCID_D2_GRPH_PFLIP:
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return DC_IRQ_SOURCE_PFLIP2;
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case VISLANDS30_IV_SRCID_D3_GRPH_PFLIP:
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return DC_IRQ_SOURCE_PFLIP3;
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case VISLANDS30_IV_SRCID_D4_GRPH_PFLIP:
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return DC_IRQ_SOURCE_PFLIP4;
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case VISLANDS30_IV_SRCID_D5_GRPH_PFLIP:
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return DC_IRQ_SOURCE_PFLIP5;
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case VISLANDS30_IV_SRCID_D6_GRPH_PFLIP:
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return DC_IRQ_SOURCE_PFLIP6;
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case VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A:
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/* generic src_id for all HPD and HPDRX interrupts */
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switch (ext_id) {
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case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_A:
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return DC_IRQ_SOURCE_HPD1;
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case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_B:
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return DC_IRQ_SOURCE_HPD2;
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case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_C:
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return DC_IRQ_SOURCE_HPD3;
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case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_D:
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return DC_IRQ_SOURCE_HPD4;
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case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_E:
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return DC_IRQ_SOURCE_HPD5;
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case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_F:
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return DC_IRQ_SOURCE_HPD6;
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case VISLANDS30_IV_EXTID_HPD_RX_A:
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return DC_IRQ_SOURCE_HPD1RX;
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case VISLANDS30_IV_EXTID_HPD_RX_B:
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return DC_IRQ_SOURCE_HPD2RX;
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case VISLANDS30_IV_EXTID_HPD_RX_C:
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return DC_IRQ_SOURCE_HPD3RX;
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case VISLANDS30_IV_EXTID_HPD_RX_D:
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return DC_IRQ_SOURCE_HPD4RX;
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case VISLANDS30_IV_EXTID_HPD_RX_E:
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return DC_IRQ_SOURCE_HPD5RX;
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case VISLANDS30_IV_EXTID_HPD_RX_F:
|
||||
return DC_IRQ_SOURCE_HPD6RX;
|
||||
default:
|
||||
return DC_IRQ_SOURCE_INVALID;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
return DC_IRQ_SOURCE_INVALID;
|
||||
}
|
||||
}
|
||||
|
||||
static const struct irq_service_funcs irq_service_funcs_dce60 = {
|
||||
.to_dal_irq_source = to_dal_irq_source_dce60
|
||||
};
|
||||
|
||||
static void dce60_irq_construct(
|
||||
struct irq_service *irq_service,
|
||||
struct irq_service_init_data *init_data)
|
||||
{
|
||||
dal_irq_service_construct(irq_service, init_data);
|
||||
|
||||
irq_service->info = irq_source_info_dce60;
|
||||
irq_service->funcs = &irq_service_funcs_dce60;
|
||||
}
|
||||
|
||||
struct irq_service *dal_irq_service_dce60_create(
|
||||
struct irq_service_init_data *init_data)
|
||||
{
|
||||
struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
|
||||
GFP_KERNEL);
|
||||
|
||||
if (!irq_service)
|
||||
return NULL;
|
||||
|
||||
dce60_irq_construct(irq_service, init_data);
|
||||
return irq_service;
|
||||
}
|
||||
|
||||
|
||||
40
drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.h
Normal file
40
drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.h
Normal file
@ -0,0 +1,40 @@
|
||||
/*
|
||||
* Copyright 2020 Mauro Rossi <issor.oruam@gmail.com>
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: AMD
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DAL_IRQ_SERVICE_DCE60_H__
|
||||
#define __DAL_IRQ_SERVICE_DCE60_H__
|
||||
|
||||
#include "../irq_service.h"
|
||||
|
||||
enum dc_irq_source to_dal_irq_source_dce60(
|
||||
struct irq_service *irq_service,
|
||||
uint32_t src_id,
|
||||
uint32_t ext_id);
|
||||
|
||||
struct irq_service *dal_irq_service_dce60_create(
|
||||
struct irq_service_init_data *init_data);
|
||||
|
||||
#endif
|
||||
|
||||
@ -32,6 +32,9 @@
|
||||
|
||||
#include "dce110/irq_service_dce110.h"
|
||||
|
||||
#if defined(CONFIG_DRM_AMD_DC_SI)
|
||||
#include "dce60/irq_service_dce60.h"
|
||||
#endif
|
||||
|
||||
#include "dce80/irq_service_dce80.h"
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user