forked from Minki/linux
Here are fixes for AT91 that are mainly related to device tree.
One RM9200 setup option is the only C code change. Some documentation changes can clarify the pinctrl use. Then, some defconfig modifications are allowing the affected platforms to boot. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQEcBAABAgAGBQJRAPnqAAoJEAf03oE53VmQbeUH/04lzIgUv63RX2zQFD6Fi1zD IeYBhfzeSP65CPMqyFnw+lrHUdCWn0JYdFM6/x7J8n1k2+SY3T7N95k5oXlnqO6e pT/XGontWQIZkyL0jkrawbs5QtE0OYnkm8Ge97qlhul4XoIiyWLFFGDHE36dzcv/ K4FPrG9PVVhjFIiZB+v5I3CnhzLWJvozn9J2ceIZ5d0Z9dwLuHWgXGu6OM2ZRvOw LR1r2YpnGTKUT0am6tmWm1W7PY6ZQOQXmx5qX/H2X6gRQdq690baYUTOYPK3ZckX kdEa+pCOQHY1GgimFzUzAVfoCyYwllo1yAWaK2a4qR4kxcaeGd1BYqlKeCFIfRc= =aKwA -----END PGP SIGNATURE----- Merge tag 'at91-fixes' of git://github.com/at91linux/linux-at91 into fixes From Nicolas Ferre: Here are fixes for AT91 that are mainly related to device tree. One RM9200 setup option is the only C code change. Some documentation changes can clarify the pinctrl use. Then, some defconfig modifications are allowing the affected platforms to boot. * tag 'at91-fixes' of git://github.com/at91linux/linux-at91: ARM: at91/dts: correct comment in at91sam9x5.dtsi for mii ARM: at91/at91_dt_defconfig: add at91sam9n12 SoC to DT defconfig ARM: at91/at91_dt_defconfig: remove memory specification to cmdline ARM: at91/dts: add macb mii pinctrl config for kizbox ARM: at91: rm9200: remake the BGA as default version ARM: at91: fix gpios on i2c-gpio for RM9200 DT ARM: at91/at91sam9x5 DTS: add SCK USART pins ARM: at91/at91sam9x5 DTS: correct wrong PIO BANK values on u(s)arts ARM: at91/at91-pinctrl documentation: fix typo and add some details
This commit is contained in:
Olof Johansson
commit
60fd8e35e3
@ -81,7 +81,8 @@ PA31 TXD4
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Required properties for pin configuration node:
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- atmel,pins: 4 integers array, represents a group of pins mux and config
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setting. The format is atmel,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>.
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The PERIPH 0 means gpio.
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The PERIPH 0 means gpio, PERIPH 1 is periph A, PERIPH 2 is periph B...
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PIN_BANK 0 is pioA, PIN_BANK 1 is pioB...
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Bits used for CONFIG:
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PULL_UP (1 << 0): indicate this pin need a pull up.
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@ -126,7 +127,7 @@ pinctrl@fffff400 {
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pinctrl_dbgu: dbgu-0 {
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atmel,pins =
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<1 14 0x1 0x0 /* PB14 periph A */
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1 15 0x1 0x1>; /* PB15 periph with pullup */
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1 15 0x1 0x1>; /* PB15 periph A with pullup */
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};
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};
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};
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@ -336,8 +336,8 @@
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i2c@0 {
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compatible = "i2c-gpio";
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gpios = <&pioA 23 0 /* sda */
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&pioA 24 0 /* scl */
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gpios = <&pioA 25 0 /* sda */
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&pioA 26 0 /* scl */
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>;
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i2c-gpio,sda-open-drain;
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i2c-gpio,scl-open-drain;
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@ -143,6 +143,11 @@
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atmel,pins =
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<0 3 0x1 0x0>; /* PA3 periph A */
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};
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pinctrl_usart0_sck: usart0_sck-0 {
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atmel,pins =
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<0 4 0x1 0x0>; /* PA4 periph A */
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};
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};
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usart1 {
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@ -154,12 +159,17 @@
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pinctrl_usart1_rts: usart1_rts-0 {
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atmel,pins =
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<3 27 0x3 0x0>; /* PC27 periph C */
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<2 27 0x3 0x0>; /* PC27 periph C */
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};
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pinctrl_usart1_cts: usart1_cts-0 {
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atmel,pins =
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<3 28 0x3 0x0>; /* PC28 periph C */
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<2 28 0x3 0x0>; /* PC28 periph C */
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};
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pinctrl_usart1_sck: usart1_sck-0 {
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atmel,pins =
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<2 28 0x3 0x0>; /* PC29 periph C */
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};
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};
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@ -172,46 +182,56 @@
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pinctrl_uart2_rts: uart2_rts-0 {
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atmel,pins =
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<0 0 0x2 0x0>; /* PB0 periph B */
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<1 0 0x2 0x0>; /* PB0 periph B */
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};
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pinctrl_uart2_cts: uart2_cts-0 {
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atmel,pins =
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<0 1 0x2 0x0>; /* PB1 periph B */
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<1 1 0x2 0x0>; /* PB1 periph B */
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};
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pinctrl_usart2_sck: usart2_sck-0 {
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atmel,pins =
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<1 2 0x2 0x0>; /* PB2 periph B */
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};
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};
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usart3 {
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pinctrl_uart3: usart3-0 {
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atmel,pins =
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<3 23 0x2 0x1 /* PC22 periph B with pullup */
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3 23 0x2 0x0>; /* PC23 periph B */
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<2 23 0x2 0x1 /* PC22 periph B with pullup */
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2 23 0x2 0x0>; /* PC23 periph B */
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};
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pinctrl_usart3_rts: usart3_rts-0 {
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atmel,pins =
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<3 24 0x2 0x0>; /* PC24 periph B */
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<2 24 0x2 0x0>; /* PC24 periph B */
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};
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pinctrl_usart3_cts: usart3_cts-0 {
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atmel,pins =
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<3 25 0x2 0x0>; /* PC25 periph B */
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<2 25 0x2 0x0>; /* PC25 periph B */
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};
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pinctrl_usart3_sck: usart3_sck-0 {
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atmel,pins =
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<2 26 0x2 0x0>; /* PC26 periph B */
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};
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};
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uart0 {
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pinctrl_uart0: uart0-0 {
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atmel,pins =
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<3 8 0x3 0x0 /* PC8 periph C */
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3 9 0x3 0x1>; /* PC9 periph C with pullup */
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<2 8 0x3 0x0 /* PC8 periph C */
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2 9 0x3 0x1>; /* PC9 periph C with pullup */
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};
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};
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uart1 {
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pinctrl_uart1: uart1-0 {
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atmel,pins =
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<3 16 0x3 0x0 /* PC16 periph C */
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3 17 0x3 0x1>; /* PC17 periph C with pullup */
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<2 16 0x3 0x0 /* PC16 periph C */
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2 17 0x3 0x1>; /* PC17 periph C with pullup */
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};
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};
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@ -240,14 +260,14 @@
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pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
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atmel,pins =
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<1 8 0x1 0x0 /* PA8 periph A */
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1 11 0x1 0x0 /* PA11 periph A */
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1 12 0x1 0x0 /* PA12 periph A */
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1 13 0x1 0x0 /* PA13 periph A */
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1 14 0x1 0x0 /* PA14 periph A */
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1 15 0x1 0x0 /* PA15 periph A */
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1 16 0x1 0x0 /* PA16 periph A */
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1 17 0x1 0x0>; /* PA17 periph A */
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<1 8 0x1 0x0 /* PB8 periph A */
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1 11 0x1 0x0 /* PB11 periph A */
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1 12 0x1 0x0 /* PB12 periph A */
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1 13 0x1 0x0 /* PB13 periph A */
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1 14 0x1 0x0 /* PB14 periph A */
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1 15 0x1 0x0 /* PB15 periph A */
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1 16 0x1 0x0 /* PB16 periph A */
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1 17 0x1 0x0>; /* PB17 periph A */
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};
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};
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@ -48,6 +48,8 @@
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macb0: ethernet@fffc4000 {
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phy-mode = "mii";
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pinctrl-0 = <&pinctrl_macb_rmii
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&pinctrl_macb_rmii_mii_alt>;
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status = "okay";
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};
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@ -19,6 +19,7 @@ CONFIG_SOC_AT91SAM9260=y
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CONFIG_SOC_AT91SAM9263=y
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CONFIG_SOC_AT91SAM9G45=y
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CONFIG_SOC_AT91SAM9X5=y
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CONFIG_SOC_AT91SAM9N12=y
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CONFIG_MACH_AT91SAM_DT=y
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CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
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CONFIG_AT91_TIMER_HZ=128
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@ -31,7 +32,7 @@ CONFIG_ZBOOT_ROM_TEXT=0x0
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CONFIG_ZBOOT_ROM_BSS=0x0
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CONFIG_ARM_APPENDED_DTB=y
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CONFIG_ARM_ATAG_DTB_COMPAT=y
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CONFIG_CMDLINE="mem=128M console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw"
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CONFIG_CMDLINE="console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw"
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CONFIG_KEXEC=y
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CONFIG_AUTO_ZRELADDR=y
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# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
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@ -105,6 +105,8 @@ static void __init soc_detect(u32 dbgu_base)
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switch (socid) {
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case ARCH_ID_AT91RM9200:
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at91_soc_initdata.type = AT91_SOC_RM9200;
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if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_NONE)
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at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
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at91_boot_soc = at91rm9200_soc;
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break;
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