forked from Minki/linux
drm/i915/display/adlp: Implement new step in the TC voltage swing prog sequence
TC voltage swing programming sequence was updated with a new step. BSpec: 54956 Cc: stable@vger.kernel.org Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Clint Taylor <clinton.a.taylor@intel.com> Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220113174826.50272-1-jose.souza@intel.com
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@ -1300,6 +1300,28 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
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intel_de_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port),
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intel_de_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port),
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DKL_TX_DP20BITMODE, 0);
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DKL_TX_DP20BITMODE, 0);
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if (IS_ALDERLAKE_P(dev_priv)) {
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u32 val;
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if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
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if (ln == 0) {
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val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0);
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val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2);
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} else {
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val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3);
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val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3);
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}
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} else {
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val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0);
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val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0);
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}
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intel_de_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port),
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DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK |
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DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK,
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val);
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}
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}
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}
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}
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}
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@ -9968,8 +9968,12 @@ enum skl_power_gate {
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_DKL_PHY2_BASE) + \
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_DKL_PHY2_BASE) + \
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_DKL_TX_DPCNTL1)
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_DKL_TX_DPCNTL1)
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#define _DKL_TX_DPCNTL2 0x2C8
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#define _DKL_TX_DPCNTL2 0x2C8
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#define DKL_TX_DP20BITMODE (1 << 2)
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#define DKL_TX_DP20BITMODE REG_BIT(2)
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#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK REG_GENMASK(4, 3)
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#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK, (val))
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#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK REG_GENMASK(6, 5)
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#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, (val))
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#define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \
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#define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \
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_DKL_PHY1_BASE, \
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_DKL_PHY1_BASE, \
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_DKL_PHY2_BASE) + \
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_DKL_PHY2_BASE) + \
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