forked from Minki/linux
Merge branch 'x86-timers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 timer updates from Ingo Molnar: "The main change in this tree is the reworking, fixing and extension of the TSC frequency enumeration code (by Len Brown)" * 'x86-timers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/tsc: Remove the unused check_tsc_disabled() x86/tsc: Enumerate BXT tsc_khz via CPUID x86/tsc: Enumerate SKL cpu_khz and tsc_khz via CPUID x86/tsc_msr: Remove irqoff around MSR-based TSC enumeration x86/tsc_msr: Add Airmont reference clock values x86/tsc_msr: Correct Silvermont reference clock values x86/tsc_msr: Update comments, expand definitions x86/tsc_msr: Remove debugging messages x86/tsc_msr: Identify Intel-specific code Revert "x86/tsc: Add missing Cherrytrail frequency to the table"
This commit is contained in:
Linus Torvalds
commit
5f22004ba9
@ -35,7 +35,7 @@ extern void tsc_init(void);
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extern void mark_tsc_unstable(char *reason);
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extern int unsynchronized_tsc(void);
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extern int check_tsc_unstable(void);
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extern int check_tsc_disabled(void);
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extern unsigned long native_calibrate_cpu(void);
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extern unsigned long native_calibrate_tsc(void);
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extern unsigned long long native_sched_clock_from_tsc(u64 tsc);
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@ -52,7 +52,6 @@ extern int notsc_setup(char *);
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extern void tsc_save_sched_clock_state(void);
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extern void tsc_restore_sched_clock_state(void);
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/* MSR based TSC calibration for Intel Atom SoC platforms */
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unsigned long try_msr_calibrate_tsc(void);
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unsigned long cpu_khz_from_msr(void);
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#endif /* _ASM_X86_TSC_H */
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@ -182,7 +182,8 @@ struct x86_legacy_features {
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/**
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* struct x86_platform_ops - platform specific runtime functions
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* @calibrate_tsc: calibrate TSC
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* @calibrate_cpu: calibrate CPU
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* @calibrate_tsc: calibrate TSC, if different from CPU
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* @get_wallclock: get time from HW clock like RTC etc.
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* @set_wallclock: set time back to HW clock
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* @is_untracked_pat_range exclude from PAT logic
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@ -201,6 +202,7 @@ struct x86_legacy_features {
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* semantics.
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*/
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struct x86_platform_ops {
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unsigned long (*calibrate_cpu)(void);
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unsigned long (*calibrate_tsc)(void);
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void (*get_wallclock)(struct timespec *ts);
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int (*set_wallclock)(const struct timespec *ts);
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@ -239,7 +239,7 @@ static inline unsigned long long cycles_2_ns(unsigned long long cyc)
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return ns;
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}
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static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu)
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static void set_cyc2ns_scale(unsigned long khz, int cpu)
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{
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unsigned long long tsc_now, ns_now;
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struct cyc2ns_data *data;
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@ -248,7 +248,7 @@ static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu)
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local_irq_save(flags);
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sched_clock_idle_sleep_event();
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if (!cpu_khz)
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if (!khz)
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goto done;
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data = cyc2ns_write_begin(cpu);
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@ -261,7 +261,7 @@ static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu)
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* time function is continuous; see the comment near struct
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* cyc2ns_data.
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*/
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clocks_calc_mult_shift(&data->cyc2ns_mul, &data->cyc2ns_shift, cpu_khz,
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clocks_calc_mult_shift(&data->cyc2ns_mul, &data->cyc2ns_shift, khz,
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NSEC_PER_MSEC, 0);
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/*
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@ -335,12 +335,6 @@ int check_tsc_unstable(void)
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}
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EXPORT_SYMBOL_GPL(check_tsc_unstable);
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int check_tsc_disabled(void)
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{
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return tsc_disabled;
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}
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EXPORT_SYMBOL_GPL(check_tsc_disabled);
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#ifdef CONFIG_X86_TSC
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int __init notsc_setup(char *str)
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{
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@ -665,19 +659,77 @@ success:
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}
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/**
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* native_calibrate_tsc - calibrate the tsc on boot
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* native_calibrate_tsc
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* Determine TSC frequency via CPUID, else return 0.
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*/
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unsigned long native_calibrate_tsc(void)
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{
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unsigned int eax_denominator, ebx_numerator, ecx_hz, edx;
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unsigned int crystal_khz;
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if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
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return 0;
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if (boot_cpu_data.cpuid_level < 0x15)
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return 0;
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eax_denominator = ebx_numerator = ecx_hz = edx = 0;
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/* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */
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cpuid(0x15, &eax_denominator, &ebx_numerator, &ecx_hz, &edx);
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if (ebx_numerator == 0 || eax_denominator == 0)
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return 0;
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crystal_khz = ecx_hz / 1000;
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if (crystal_khz == 0) {
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switch (boot_cpu_data.x86_model) {
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case 0x4E: /* SKL */
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case 0x5E: /* SKL */
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crystal_khz = 24000; /* 24.0 MHz */
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break;
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case 0x5C: /* BXT */
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crystal_khz = 19200; /* 19.2 MHz */
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break;
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}
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}
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return crystal_khz * ebx_numerator / eax_denominator;
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}
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static unsigned long cpu_khz_from_cpuid(void)
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{
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unsigned int eax_base_mhz, ebx_max_mhz, ecx_bus_mhz, edx;
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if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
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return 0;
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if (boot_cpu_data.cpuid_level < 0x16)
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return 0;
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eax_base_mhz = ebx_max_mhz = ecx_bus_mhz = edx = 0;
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cpuid(0x16, &eax_base_mhz, &ebx_max_mhz, &ecx_bus_mhz, &edx);
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return eax_base_mhz * 1000;
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}
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/**
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* native_calibrate_cpu - calibrate the cpu on boot
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*/
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unsigned long native_calibrate_cpu(void)
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{
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u64 tsc1, tsc2, delta, ref1, ref2;
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unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX;
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unsigned long flags, latch, ms, fast_calibrate;
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int hpet = is_hpet_enabled(), i, loopmin;
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/* Calibrate TSC using MSR for Intel Atom SoCs */
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local_irq_save(flags);
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fast_calibrate = try_msr_calibrate_tsc();
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local_irq_restore(flags);
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fast_calibrate = cpu_khz_from_cpuid();
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if (fast_calibrate)
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return fast_calibrate;
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fast_calibrate = cpu_khz_from_msr();
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if (fast_calibrate)
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return fast_calibrate;
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@ -837,8 +889,12 @@ int recalibrate_cpu_khz(void)
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if (!boot_cpu_has(X86_FEATURE_TSC))
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return -ENODEV;
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cpu_khz = x86_platform.calibrate_cpu();
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tsc_khz = x86_platform.calibrate_tsc();
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cpu_khz = tsc_khz;
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if (tsc_khz == 0)
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tsc_khz = cpu_khz;
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else if (abs(cpu_khz - tsc_khz) * 10 > tsc_khz)
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cpu_khz = tsc_khz;
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cpu_data(0).loops_per_jiffy = cpufreq_scale(cpu_data(0).loops_per_jiffy,
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cpu_khz_old, cpu_khz);
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@ -1244,8 +1300,18 @@ void __init tsc_init(void)
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return;
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}
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cpu_khz = x86_platform.calibrate_cpu();
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tsc_khz = x86_platform.calibrate_tsc();
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cpu_khz = tsc_khz;
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/*
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* Trust non-zero tsc_khz as authorative,
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* and use it to sanity check cpu_khz,
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* which will be off if system timer is off.
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*/
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if (tsc_khz == 0)
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tsc_khz = cpu_khz;
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else if (abs(cpu_khz - tsc_khz) * 10 > tsc_khz)
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cpu_khz = tsc_khz;
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if (!tsc_khz) {
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mark_tsc_unstable("could not calculate TSC khz");
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@ -1265,7 +1331,7 @@ void __init tsc_init(void)
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*/
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for_each_possible_cpu(cpu) {
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cyc2ns_init(cpu);
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set_cyc2ns_scale(cpu_khz, cpu);
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set_cyc2ns_scale(tsc_khz, cpu);
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}
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if (tsc_disabled > 0)
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@ -1,14 +1,5 @@
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/*
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* tsc_msr.c - MSR based TSC calibration on Intel Atom SoC platforms.
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*
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* TSC in Intel Atom SoC runs at a constant rate which can be figured
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* by this formula:
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* <maximum core-clock to bus-clock ratio> * <maximum resolved frequency>
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* See Intel 64 and IA-32 System Programming Guid section 16.12 and 30.11.5
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* for details.
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* Especially some Intel Atom SoCs don't have PIT(i8254) or HPET, so MSR
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* based calibration is the only option.
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*
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* tsc_msr.c - TSC frequency enumeration via MSR
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*
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* Copyright (C) 2013 Intel Corporation
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* Author: Bin Gao <bin.gao@intel.com>
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@ -22,18 +13,10 @@
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#include <asm/apic.h>
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#include <asm/param.h>
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/* CPU reference clock frequency: in KHz */
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#define FREQ_80 80000
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#define FREQ_83 83200
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#define FREQ_100 99840
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#define FREQ_133 133200
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#define FREQ_166 166400
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#define MAX_NUM_FREQS 8
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#define MAX_NUM_FREQS 9
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/*
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* According to Intel 64 and IA-32 System Programming Guide,
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* if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
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* If MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
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* read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40].
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* Unfortunately some Intel Atom SoCs aren't quite compliant to this,
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* so we need manually differentiate SoC families. This is what the
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@ -48,17 +31,18 @@ struct freq_desc {
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static struct freq_desc freq_desc_tables[] = {
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/* PNW */
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{ 6, 0x27, 0, { 0, 0, 0, 0, 0, FREQ_100, 0, FREQ_83 } },
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{ 6, 0x27, 0, { 0, 0, 0, 0, 0, 99840, 0, 83200 } },
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/* CLV+ */
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{ 6, 0x35, 0, { 0, FREQ_133, 0, 0, 0, FREQ_100, 0, FREQ_83 } },
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/* TNG */
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{ 6, 0x4a, 1, { 0, FREQ_100, FREQ_133, 0, 0, 0, 0, 0 } },
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/* VLV2 */
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{ 6, 0x37, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } },
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/* ANN */
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{ 6, 0x5a, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_100, 0, 0, 0, 0 } },
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/* AIRMONT */
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{ 6, 0x4c, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, FREQ_80, 0, 0, 0 } },
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{ 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200 } },
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/* TNG - Intel Atom processor Z3400 series */
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{ 6, 0x4a, 1, { 0, 100000, 133300, 0, 0, 0, 0, 0 } },
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/* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */
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{ 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0 } },
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/* ANN - Intel Atom processor Z3500 series */
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{ 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0 } },
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/* AMT - Intel Atom processor X7-Z8000 and X5-Z8000 series */
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{ 6, 0x4c, 1, { 83300, 100000, 133300, 116700,
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80000, 93300, 90000, 88900, 87500 } },
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};
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static int match_cpu(u8 family, u8 model)
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@ -79,16 +63,20 @@ static int match_cpu(u8 family, u8 model)
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(freq_desc_tables[cpu_index].freqs[freq_id])
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/*
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* Do MSR calibration only for known/supported CPUs.
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* MSR-based CPU/TSC frequency discovery for certain CPUs.
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*
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* Returns the calibration value or 0 if MSR calibration failed.
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* Set global "lapic_timer_frequency" to bus_clock_cycles/jiffy
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* Return processor base frequency in KHz, or 0 on failure.
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*/
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unsigned long try_msr_calibrate_tsc(void)
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unsigned long cpu_khz_from_msr(void)
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{
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u32 lo, hi, ratio, freq_id, freq;
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unsigned long res;
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int cpu_index;
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if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
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return 0;
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cpu_index = match_cpu(boot_cpu_data.x86, boot_cpu_data.x86_model);
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if (cpu_index < 0)
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return 0;
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@ -100,31 +88,17 @@ unsigned long try_msr_calibrate_tsc(void)
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rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
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ratio = (hi >> 8) & 0x1f;
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}
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pr_info("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio);
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if (!ratio)
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goto fail;
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/* Get FSB FREQ ID */
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rdmsr(MSR_FSB_FREQ, lo, hi);
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freq_id = lo & 0x7;
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freq = id_to_freq(cpu_index, freq_id);
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pr_info("Resolved frequency ID: %u, frequency: %u KHz\n",
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freq_id, freq);
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if (!freq)
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goto fail;
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/* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
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res = freq * ratio;
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pr_info("TSC runs at %lu KHz\n", res);
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#ifdef CONFIG_X86_LOCAL_APIC
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lapic_timer_frequency = (freq * 1000) / HZ;
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pr_info("lapic_timer_frequency = %d\n", lapic_timer_frequency);
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#endif
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return res;
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fail:
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pr_warn("Fast TSC calibration using MSR failed\n");
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return 0;
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}
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@ -92,6 +92,7 @@ static void default_nmi_init(void) { };
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static int default_i8042_detect(void) { return 1; };
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struct x86_platform_ops x86_platform = {
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.calibrate_cpu = native_calibrate_cpu,
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.calibrate_tsc = native_calibrate_tsc,
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.get_wallclock = mach_get_cmos_time,
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.set_wallclock = mach_set_rtc_mmss,
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