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drm/amd/display: retire dm_pp_apply_clock_for_voltage_request

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set dcfclk and fclk req with pp_smu_display_requirement_rv

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Tony Cheng 2017-08-20 14:25:19 -04:00 committed by Alex Deucher
parent a0c38ebaa1
commit 5f06b3cf90
2 changed files with 17 additions and 17 deletions
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26
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
View File

@ -2550,7 +2550,10 @@ static void dcn10_set_bandwidth(
struct validate_context *context,
bool decrease_allowed)
{
struct dm_pp_clock_for_voltage_req clock;
struct pp_smu_display_requirement_rv *smu_req_cur =
&dc->res_pool->pp_smu_req;
struct pp_smu_display_requirement_rv smu_req = *smu_req_cur;
struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu;
if (dc->debug.sanity_checks) {
verify_allow_pstate_change_high(dc->hwseq);
@ -2569,19 +2572,12 @@ static void dcn10_set_bandwidth(
}
if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_khz
> dc->current_context->bw.dcn.cur_clk.dcfclk_khz) {
clock.clk_type = DM_PP_CLOCK_TYPE_DCFCLK;
clock.clocks_in_khz = context->bw.dcn.calc_clk.dcfclk_khz;
dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
dc->current_context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz;
context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz;
smu_req.hard_min_dcefclk_khz =
context->bw.dcn.calc_clk.dcfclk_khz;
}
if (decrease_allowed || context->bw.dcn.calc_clk.fclk_khz
> dc->current_context->bw.dcn.cur_clk.fclk_khz) {
clock.clk_type = DM_PP_CLOCK_TYPE_FCLK;
clock.clocks_in_khz = context->bw.dcn.calc_clk.fclk_khz;
dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
dc->current_context->bw.dcn.calc_clk.fclk_khz = clock.clocks_in_khz;
context->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz;
smu_req.hard_min_fclk_khz = context->bw.dcn.calc_clk.fclk_khz;
}
if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz
> dc->current_context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz) {
@ -2590,6 +2586,14 @@ static void dcn10_set_bandwidth(
context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz =
context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz;
}
smu_req.display_count = context->stream_count;
if (pp_smu->set_display_requirement)
pp_smu->set_display_requirement(&pp_smu->pp_smu, &smu_req);
*smu_req_cur = smu_req;
/* Decrease in freq is increase in period so opposite comparison for dram_ccm */
if (decrease_allowed || context->bw.dcn.calc_clk.dram_ccm_us
< dc->current_context->bw.dcn.cur_clk.dram_ccm_us) {

8
drivers/gpu/drm/amd/display/dc/inc/core_types.h
View File

@ -132,10 +132,10 @@ struct resource_pool {
struct output_pixel_processor *opps[MAX_PIPES];
struct timing_generator *timing_generators[MAX_PIPES];
struct stream_encoder *stream_enc[MAX_PIPES * 2];
#ifdef CONFIG_DRM_AMD_DC_DCN1_0
struct mpc *mpc;
struct pp_smu_funcs_rv *pp_smu;
#endif
struct pp_smu_display_requirement_rv pp_smu_req;
struct dwbc *dwbc[MAX_DWB_PIPES];
@ -234,7 +234,6 @@ struct dce_bw_output {
int blackout_recovery_time_us;
};
#ifdef CONFIG_DRM_AMD_DC_DCN1_0
struct dcn_bw_clocks {
int dispclk_khz;
bool dppclk_div;
@ -250,12 +249,9 @@ struct dcn_bw_output {
struct dcn_bw_clocks calc_clk;
struct dcn_watermark_set watermarks;
};
#endif
union bw_context {
#ifdef CONFIG_DRM_AMD_DC_DCN1_0
struct dcn_bw_output dcn;
#endif
struct dce_bw_output dce;
};