forked from Minki/linux
drm/nouveau/i2c: add support for ddc/aux, and dp link training on anx9805
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
eb6313add6
commit
5effecd4f8
@ -93,6 +93,7 @@ nouveau-y += core/subdev/gpio/nv50.o
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nouveau-y += core/subdev/gpio/nvd0.o
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nouveau-y += core/subdev/gpio/nve0.o
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nouveau-y += core/subdev/i2c/base.o
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nouveau-y += core/subdev/i2c/anx9805.o
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nouveau-y += core/subdev/i2c/aux.o
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nouveau-y += core/subdev/i2c/bit.o
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nouveau-y += core/subdev/i2c/nv04.o
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@ -103,6 +103,7 @@ extern struct nouveau_oclass nv4e_i2c_oclass;
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extern struct nouveau_oclass nv50_i2c_oclass;
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extern struct nouveau_oclass nv94_i2c_oclass;
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extern struct nouveau_oclass nvd0_i2c_oclass;
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extern struct nouveau_oclass nouveau_anx9805_sclass[];
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extern const struct i2c_algorithm nouveau_i2c_bit_algo;
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extern const struct i2c_algorithm nouveau_i2c_aux_algo;
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279
drivers/gpu/drm/nouveau/core/subdev/i2c/anx9805.c
Normal file
279
drivers/gpu/drm/nouveau/core/subdev/i2c/anx9805.c
Normal file
@ -0,0 +1,279 @@
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/*
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* Copyright 2013 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs <bskeggs@redhat.com>
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*/
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#include <subdev/i2c.h>
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struct anx9805_i2c_port {
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struct nouveau_i2c_port base;
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u32 addr;
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u32 ctrl;
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};
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static int
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anx9805_train(struct nouveau_i2c_port *port, int link_nr, int link_bw, bool enh)
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{
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struct anx9805_i2c_port *chan = (void *)port;
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struct nouveau_i2c_port *mast = (void *)nv_object(chan)->parent;
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u8 tmp, i;
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nv_wri2cr(mast, chan->addr, 0xa0, link_bw);
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nv_wri2cr(mast, chan->addr, 0xa1, link_nr | (enh ? 0x80 : 0x00));
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nv_wri2cr(mast, chan->addr, 0xa2, 0x01);
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nv_wri2cr(mast, chan->addr, 0xa8, 0x01);
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i = 0;
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while ((tmp = nv_rdi2cr(mast, chan->addr, 0xa8)) & 0x01) {
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mdelay(5);
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if (i++ == 100) {
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nv_error(port, "link training timed out\n");
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return -ETIMEDOUT;
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}
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}
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if (tmp & 0x70) {
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nv_error(port, "link training failed: 0x%02x\n", tmp);
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return -EIO;
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}
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return 1;
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}
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static int
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anx9805_aux(struct nouveau_i2c_port *port, u8 type, u32 addr, u8 *data, u8 size)
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{
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struct anx9805_i2c_port *chan = (void *)port;
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struct nouveau_i2c_port *mast = (void *)nv_object(chan)->parent;
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int i, ret = -ETIMEDOUT;
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u8 tmp;
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tmp = nv_rdi2cr(mast, chan->ctrl, 0x07) & ~0x04;
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nv_wri2cr(mast, chan->ctrl, 0x07, tmp | 0x04);
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nv_wri2cr(mast, chan->ctrl, 0x07, tmp);
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nv_wri2cr(mast, chan->ctrl, 0xf7, 0x01);
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nv_wri2cr(mast, chan->addr, 0xe4, 0x80);
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for (i = 0; !(type & 1) && i < size; i++)
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nv_wri2cr(mast, chan->addr, 0xf0 + i, data[i]);
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nv_wri2cr(mast, chan->addr, 0xe5, ((size - 1) << 4) | type);
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nv_wri2cr(mast, chan->addr, 0xe6, (addr & 0x000ff) >> 0);
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nv_wri2cr(mast, chan->addr, 0xe7, (addr & 0x0ff00) >> 8);
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nv_wri2cr(mast, chan->addr, 0xe8, (addr & 0xf0000) >> 16);
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nv_wri2cr(mast, chan->addr, 0xe9, 0x01);
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i = 0;
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while ((tmp = nv_rdi2cr(mast, chan->addr, 0xe9)) & 0x01) {
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mdelay(5);
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if (i++ == 32)
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goto done;
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}
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if ((tmp = nv_rdi2cr(mast, chan->ctrl, 0xf7)) & 0x01) {
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ret = -EIO;
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goto done;
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}
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for (i = 0; (type & 1) && i < size; i++)
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data[i] = nv_rdi2cr(mast, chan->addr, 0xf0 + i);
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ret = 0;
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done:
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nv_wri2cr(mast, chan->ctrl, 0xf7, 0x01);
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return ret;
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}
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static const struct nouveau_i2c_func
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anx9805_aux_func = {
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.aux = anx9805_aux,
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.lnk_ctl = anx9805_train,
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};
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static int
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anx9805_aux_chan_ctor(struct nouveau_object *parent,
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struct nouveau_object *engine,
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struct nouveau_oclass *oclass, void *data, u32 index,
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struct nouveau_object **pobject)
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{
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struct nouveau_i2c_port *mast = (void *)parent;
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struct anx9805_i2c_port *chan;
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int ret;
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ret = nouveau_i2c_port_create(parent, engine, oclass, index,
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&nouveau_i2c_aux_algo, &chan);
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*pobject = nv_object(chan);
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if (ret)
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return ret;
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switch ((oclass->handle & 0xff00) >> 8) {
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case 0x0d:
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chan->addr = 0x38;
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chan->ctrl = 0x39;
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break;
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case 0x0e:
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chan->addr = 0x3c;
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chan->ctrl = 0x3b;
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break;
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default:
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BUG_ON(1);
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}
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if (mast->adapter.algo == &i2c_bit_algo) {
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struct i2c_algo_bit_data *algo = mast->adapter.algo_data;
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algo->udelay = max(algo->udelay, 40);
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}
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chan->base.func = &anx9805_aux_func;
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return 0;
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}
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static struct nouveau_ofuncs
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anx9805_aux_ofuncs = {
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.ctor = anx9805_aux_chan_ctor,
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.dtor = _nouveau_i2c_port_dtor,
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.init = _nouveau_i2c_port_init,
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.fini = _nouveau_i2c_port_fini,
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};
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static int
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anx9805_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
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{
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struct anx9805_i2c_port *port = adap->algo_data;
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struct nouveau_i2c_port *mast = (void *)nv_object(port)->parent;
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struct i2c_msg *msg = msgs;
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int ret = -ETIMEDOUT;
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int i, j, cnt = num;
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u8 seg = 0x00, off = 0x00, tmp;
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tmp = nv_rdi2cr(mast, port->ctrl, 0x07) & ~0x10;
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nv_wri2cr(mast, port->ctrl, 0x07, tmp | 0x10);
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nv_wri2cr(mast, port->ctrl, 0x07, tmp);
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nv_wri2cr(mast, port->addr, 0x43, 0x05);
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mdelay(5);
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while (cnt--) {
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if ( (msg->flags & I2C_M_RD) && msg->addr == 0x50) {
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nv_wri2cr(mast, port->addr, 0x40, msg->addr << 1);
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nv_wri2cr(mast, port->addr, 0x41, seg);
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nv_wri2cr(mast, port->addr, 0x42, off);
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nv_wri2cr(mast, port->addr, 0x44, msg->len);
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nv_wri2cr(mast, port->addr, 0x45, 0x00);
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nv_wri2cr(mast, port->addr, 0x43, 0x01);
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for (i = 0; i < msg->len; i++) {
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j = 0;
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while (nv_rdi2cr(mast, port->addr, 0x46) & 0x10) {
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mdelay(5);
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if (j++ == 32)
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goto done;
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}
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msg->buf[i] = nv_rdi2cr(mast, port->addr, 0x47);
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}
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} else
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if (!(msg->flags & I2C_M_RD)) {
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if (msg->addr == 0x50 && msg->len == 0x01) {
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off = msg->buf[0];
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} else
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if (msg->addr == 0x30 && msg->len == 0x01) {
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seg = msg->buf[0];
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} else
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goto done;
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} else {
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goto done;
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}
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msg++;
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}
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ret = num;
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done:
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nv_wri2cr(mast, port->addr, 0x43, 0x00);
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return ret;
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}
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static u32
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anx9805_func(struct i2c_adapter *adap)
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{
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return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
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}
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static const struct i2c_algorithm
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anx9805_i2c_algo = {
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.master_xfer = anx9805_xfer,
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.functionality = anx9805_func
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};
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static const struct nouveau_i2c_func
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anx9805_i2c_func = {
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};
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static int
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anx9805_ddc_port_ctor(struct nouveau_object *parent,
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struct nouveau_object *engine,
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struct nouveau_oclass *oclass, void *data, u32 index,
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struct nouveau_object **pobject)
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{
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struct nouveau_i2c_port *mast = (void *)parent;
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struct anx9805_i2c_port *port;
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int ret;
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ret = nouveau_i2c_port_create(parent, engine, oclass, index,
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&anx9805_i2c_algo, &port);
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*pobject = nv_object(port);
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if (ret)
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return ret;
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switch ((oclass->handle & 0xff00) >> 8) {
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case 0x0d:
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port->addr = 0x3d;
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port->ctrl = 0x39;
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break;
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case 0x0e:
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port->addr = 0x3f;
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port->ctrl = 0x3b;
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break;
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default:
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BUG_ON(1);
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}
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if (mast->adapter.algo == &i2c_bit_algo) {
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struct i2c_algo_bit_data *algo = mast->adapter.algo_data;
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algo->udelay = max(algo->udelay, 40);
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}
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port->base.func = &anx9805_i2c_func;
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return 0;
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}
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static struct nouveau_ofuncs
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anx9805_ddc_ofuncs = {
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.ctor = anx9805_ddc_port_ctor,
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.dtor = _nouveau_i2c_port_dtor,
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.init = _nouveau_i2c_port_init,
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.fini = _nouveau_i2c_port_fini,
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};
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struct nouveau_oclass
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nouveau_anx9805_sclass[] = {
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{ .handle = NV_I2C_TYPE_EXTDDC(0x0d), .ofuncs = &anx9805_ddc_ofuncs },
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{ .handle = NV_I2C_TYPE_EXTAUX(0x0d), .ofuncs = &anx9805_aux_ofuncs },
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{ .handle = NV_I2C_TYPE_EXTDDC(0x0e), .ofuncs = &anx9805_ddc_ofuncs },
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{ .handle = NV_I2C_TYPE_EXTAUX(0x0e), .ofuncs = &anx9805_aux_ofuncs },
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{}
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};
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@ -24,6 +24,9 @@
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#include <core/option.h>
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#include <subdev/bios.h>
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#include <subdev/bios/dcb.h>
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#include <subdev/bios/i2c.h>
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#include <subdev/i2c.h>
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#include <subdev/vga.h>
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@ -278,6 +281,11 @@ _nouveau_i2c_dtor(struct nouveau_object *object)
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nouveau_subdev_destroy(&i2c->base);
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}
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static struct nouveau_oclass *
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nouveau_i2c_extdev_sclass[] = {
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nouveau_anx9805_sclass,
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};
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int
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nouveau_i2c_create_(struct nouveau_object *parent,
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struct nouveau_object *engine,
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@ -289,7 +297,10 @@ nouveau_i2c_create_(struct nouveau_object *parent,
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struct nouveau_i2c *i2c;
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struct nouveau_object *object;
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struct dcb_i2c_entry info;
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int ret, index = -1;
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int ret, i, j, index = -1;
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struct dcb_output outp;
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u8 ver, hdr;
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u32 data;
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ret = nouveau_subdev_create(parent, engine, oclass, 0,
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"I2C", "i2c", &i2c);
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@ -317,5 +328,41 @@ nouveau_i2c_create_(struct nouveau_object *parent,
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} while (ret && (++oclass)->handle);
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}
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/* in addition to the busses specified in the i2c table, there
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* may be ddc/aux channels hiding behind external tmds/dp/etc
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* transmitters.
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*/
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index = ((index + 0x0f) / 0x10) * 0x10;
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i = -1;
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while ((data = dcb_outp_parse(bios, ++i, &ver, &hdr, &outp))) {
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if (!outp.location || !outp.extdev)
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continue;
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switch (outp.type) {
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case DCB_OUTPUT_TMDS:
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info.type = NV_I2C_TYPE_EXTDDC(outp.extdev);
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break;
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case DCB_OUTPUT_DP:
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info.type = NV_I2C_TYPE_EXTAUX(outp.extdev);
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break;
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default:
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continue;
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}
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ret = -ENODEV;
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j = -1;
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while (ret && ++j < ARRAY_SIZE(nouveau_i2c_extdev_sclass)) {
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parent = nv_object(i2c->find(i2c, outp.i2c_index));
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oclass = nouveau_i2c_extdev_sclass[j];
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do {
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if (oclass->handle != info.type)
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continue;
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ret = nouveau_object_ctor(parent, *pobject,
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oclass, NULL,
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index++, &object);
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} while (ret && (++oclass)->handle);
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}
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}
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return 0;
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}
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