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drm/nouveau/ibus: namespace + nvidia gpu names (no binary change)

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The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver.  This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).

Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.

A comparison of objdump disassemblies proves no code changes.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2015-01-14 15:04:31 +10:00
parent b9ec14246d
commit 5ecfadeb89
8 changed files with 102 additions and 108 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

45
drivers/gpu/drm/nouveau/include/nvkm/subdev/ibus.h
View File

@ -1,35 +1,32 @@
#ifndef __NOUVEAU_IBUS_H__ #ifndef __NVKM_IBUS_H__
#define __NOUVEAU_IBUS_H__ #define __NVKM_IBUS_H__
#include <core/subdev.h> #include <core/subdev.h>
#include <core/device.h>
struct nouveau_ibus { struct nvkm_ibus {
struct nouveau_subdev base; struct nvkm_subdev base;
}; };
static inline struct nouveau_ibus * static inline struct nvkm_ibus *
nouveau_ibus(void *obj) nvkm_ibus(void *obj)
{ {
return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_IBUS); return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_IBUS);
} }
#define nouveau_ibus_create(p,e,o,d) \ #define nvkm_ibus_create(p,e,o,d) \
nouveau_subdev_create_((p), (e), (o), 0, "PIBUS", "ibus", \ nvkm_subdev_create_((p), (e), (o), 0, "PIBUS", "ibus", \
sizeof(**d), (void **)d) sizeof(**d), (void **)d)
#define nouveau_ibus_destroy(p) \ #define nvkm_ibus_destroy(p) \
nouveau_subdev_destroy(&(p)->base) nvkm_subdev_destroy(&(p)->base)
#define nouveau_ibus_init(p) \ #define nvkm_ibus_init(p) \
nouveau_subdev_init(&(p)->base) nvkm_subdev_init(&(p)->base)
#define nouveau_ibus_fini(p,s) \ #define nvkm_ibus_fini(p,s) \
nouveau_subdev_fini(&(p)->base, (s)) nvkm_subdev_fini(&(p)->base, (s))
#define _nouveau_ibus_dtor _nouveau_subdev_dtor #define _nvkm_ibus_dtor _nvkm_subdev_dtor
#define _nouveau_ibus_init _nouveau_subdev_init #define _nvkm_ibus_init _nvkm_subdev_init
#define _nouveau_ibus_fini _nouveau_subdev_fini #define _nvkm_ibus_fini _nvkm_subdev_fini
extern struct nouveau_oclass nvc0_ibus_oclass;
extern struct nouveau_oclass nve0_ibus_oclass;
extern struct nouveau_oclass gk20a_ibus_oclass;
extern struct nvkm_oclass gf100_ibus_oclass;
extern struct nvkm_oclass gk104_ibus_oclass;
extern struct nvkm_oclass gk20a_ibus_oclass;
#endif #endif

4
drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
View File

@ -74,7 +74,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
@ -118,7 +118,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;

18
drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
View File

@ -74,7 +74,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
@ -107,7 +107,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
@ -140,7 +140,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
@ -172,7 +172,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
@ -205,7 +205,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
@ -237,7 +237,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
@ -269,7 +269,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
@ -302,7 +302,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
@ -334,7 +334,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;

14
drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
View File

@ -74,7 +74,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
@ -108,7 +108,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
@ -142,7 +142,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
@ -198,7 +198,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
@ -232,7 +232,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
@ -266,7 +266,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
@ -299,7 +299,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;

4
drivers/gpu/drm/nouveau/nvkm/subdev/ibus/Kbuild
View File

@ -1,3 +1,3 @@
nvkm-y += nvkm/subdev/ibus/nvc0.o nvkm-y += nvkm/subdev/ibus/gf100.o
nvkm-y += nvkm/subdev/ibus/nve0.o nvkm-y += nvkm/subdev/ibus/gk104.o
nvkm-y += nvkm/subdev/ibus/gk20a.o nvkm-y += nvkm/subdev/ibus/gk20a.o

47
drivers/gpu/drm/nouveau/nvkm/subdev/ibus/nvc0.c → drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gf100.c
View File

@ -21,15 +21,14 @@
* *
* Authors: Ben Skeggs * Authors: Ben Skeggs
*/ */
#include <subdev/ibus.h> #include <subdev/ibus.h>
struct nvc0_ibus_priv { struct gf100_ibus_priv {
struct nouveau_ibus base; struct nvkm_ibus base;
}; };
static void static void
nvc0_ibus_intr_hub(struct nvc0_ibus_priv *priv, int i) gf100_ibus_intr_hub(struct gf100_ibus_priv *priv, int i)
{ {
u32 addr = nv_rd32(priv, 0x122120 + (i * 0x0400)); u32 addr = nv_rd32(priv, 0x122120 + (i * 0x0400));
u32 data = nv_rd32(priv, 0x122124 + (i * 0x0400)); u32 data = nv_rd32(priv, 0x122124 + (i * 0x0400));
@ -39,7 +38,7 @@ nvc0_ibus_intr_hub(struct nvc0_ibus_priv *priv, int i)
} }
static void static void
nvc0_ibus_intr_rop(struct nvc0_ibus_priv *priv, int i) gf100_ibus_intr_rop(struct gf100_ibus_priv *priv, int i)
{ {
u32 addr = nv_rd32(priv, 0x124120 + (i * 0x0400)); u32 addr = nv_rd32(priv, 0x124120 + (i * 0x0400));
u32 data = nv_rd32(priv, 0x124124 + (i * 0x0400)); u32 data = nv_rd32(priv, 0x124124 + (i * 0x0400));
@ -49,7 +48,7 @@ nvc0_ibus_intr_rop(struct nvc0_ibus_priv *priv, int i)
} }
static void static void
nvc0_ibus_intr_gpc(struct nvc0_ibus_priv *priv, int i) gf100_ibus_intr_gpc(struct gf100_ibus_priv *priv, int i)
{ {
u32 addr = nv_rd32(priv, 0x128120 + (i * 0x0400)); u32 addr = nv_rd32(priv, 0x128120 + (i * 0x0400));
u32 data = nv_rd32(priv, 0x128124 + (i * 0x0400)); u32 data = nv_rd32(priv, 0x128124 + (i * 0x0400));
@ -59,9 +58,9 @@ nvc0_ibus_intr_gpc(struct nvc0_ibus_priv *priv, int i)
} }
static void static void
nvc0_ibus_intr(struct nouveau_subdev *subdev) gf100_ibus_intr(struct nvkm_subdev *subdev)
{ {
struct nvc0_ibus_priv *priv = (void *)subdev; struct gf100_ibus_priv *priv = (void *)subdev;
u32 intr0 = nv_rd32(priv, 0x121c58); u32 intr0 = nv_rd32(priv, 0x121c58);
u32 intr1 = nv_rd32(priv, 0x121c5c); u32 intr1 = nv_rd32(priv, 0x121c5c);
u32 hubnr = nv_rd32(priv, 0x121c70); u32 hubnr = nv_rd32(priv, 0x121c70);
@ -72,7 +71,7 @@ nvc0_ibus_intr(struct nouveau_subdev *subdev)
for (i = 0; (intr0 & 0x0000ff00) && i < hubnr; i++) { for (i = 0; (intr0 & 0x0000ff00) && i < hubnr; i++) {
u32 stat = 0x00000100 << i; u32 stat = 0x00000100 << i;
if (intr0 & stat) { if (intr0 & stat) {
nvc0_ibus_intr_hub(priv, i); gf100_ibus_intr_hub(priv, i);
intr0 &= ~stat; intr0 &= ~stat;
} }
} }
@ -80,7 +79,7 @@ nvc0_ibus_intr(struct nouveau_subdev *subdev)
for (i = 0; (intr0 & 0xffff0000) && i < ropnr; i++) { for (i = 0; (intr0 & 0xffff0000) && i < ropnr; i++) {
u32 stat = 0x00010000 << i; u32 stat = 0x00010000 << i;
if (intr0 & stat) { if (intr0 & stat) {
nvc0_ibus_intr_rop(priv, i); gf100_ibus_intr_rop(priv, i);
intr0 &= ~stat; intr0 &= ~stat;
} }
} }
@ -88,36 +87,36 @@ nvc0_ibus_intr(struct nouveau_subdev *subdev)
for (i = 0; intr1 && i < gpcnr; i++) { for (i = 0; intr1 && i < gpcnr; i++) {
u32 stat = 0x00000001 << i; u32 stat = 0x00000001 << i;
if (intr1 & stat) { if (intr1 & stat) {
nvc0_ibus_intr_gpc(priv, i); gf100_ibus_intr_gpc(priv, i);
intr1 &= ~stat; intr1 &= ~stat;
} }
} }
} }
static int static int
nvc0_ibus_ctor(struct nouveau_object *parent, struct nouveau_object *engine, gf100_ibus_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size, struct nvkm_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject) struct nvkm_object **pobject)
{ {
struct nvc0_ibus_priv *priv; struct gf100_ibus_priv *priv;
int ret; int ret;
ret = nouveau_ibus_create(parent, engine, oclass, &priv); ret = nvkm_ibus_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv); *pobject = nv_object(priv);
if (ret) if (ret)
return ret; return ret;
nv_subdev(priv)->intr = nvc0_ibus_intr; nv_subdev(priv)->intr = gf100_ibus_intr;
return 0; return 0;
} }
struct nouveau_oclass struct nvkm_oclass
nvc0_ibus_oclass = { gf100_ibus_oclass = {
.handle = NV_SUBDEV(IBUS, 0xc0), .handle = NV_SUBDEV(IBUS, 0xc0),
.ofuncs = &(struct nouveau_ofuncs) { .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nvc0_ibus_ctor, .ctor = gf100_ibus_ctor,
.dtor = _nouveau_ibus_dtor, .dtor = _nvkm_ibus_dtor,
.init = _nouveau_ibus_init, .init = _nvkm_ibus_init,
.fini = _nouveau_ibus_fini, .fini = _nvkm_ibus_fini,
}, },
}; };

53
drivers/gpu/drm/nouveau/nvkm/subdev/ibus/nve0.c → drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk104.c
View File

@ -21,15 +21,14 @@
* *
* Authors: Ben Skeggs * Authors: Ben Skeggs
*/ */
#include <subdev/ibus.h> #include <subdev/ibus.h>
struct nve0_ibus_priv { struct gk104_ibus_priv {
struct nouveau_ibus base; struct nvkm_ibus base;
}; };
static void static void
nve0_ibus_intr_hub(struct nve0_ibus_priv *priv, int i) gk104_ibus_intr_hub(struct gk104_ibus_priv *priv, int i)
{ {
u32 addr = nv_rd32(priv, 0x122120 + (i * 0x0800)); u32 addr = nv_rd32(priv, 0x122120 + (i * 0x0800));
u32 data = nv_rd32(priv, 0x122124 + (i * 0x0800)); u32 data = nv_rd32(priv, 0x122124 + (i * 0x0800));
@ -39,7 +38,7 @@ nve0_ibus_intr_hub(struct nve0_ibus_priv *priv, int i)
} }
static void static void
nve0_ibus_intr_rop(struct nve0_ibus_priv *priv, int i) gk104_ibus_intr_rop(struct gk104_ibus_priv *priv, int i)
{ {
u32 addr = nv_rd32(priv, 0x124120 + (i * 0x0800)); u32 addr = nv_rd32(priv, 0x124120 + (i * 0x0800));
u32 data = nv_rd32(priv, 0x124124 + (i * 0x0800)); u32 data = nv_rd32(priv, 0x124124 + (i * 0x0800));
@ -49,7 +48,7 @@ nve0_ibus_intr_rop(struct nve0_ibus_priv *priv, int i)
} }
static void static void
nve0_ibus_intr_gpc(struct nve0_ibus_priv *priv, int i) gk104_ibus_intr_gpc(struct gk104_ibus_priv *priv, int i)
{ {
u32 addr = nv_rd32(priv, 0x128120 + (i * 0x0800)); u32 addr = nv_rd32(priv, 0x128120 + (i * 0x0800));
u32 data = nv_rd32(priv, 0x128124 + (i * 0x0800)); u32 data = nv_rd32(priv, 0x128124 + (i * 0x0800));
@ -59,9 +58,9 @@ nve0_ibus_intr_gpc(struct nve0_ibus_priv *priv, int i)
} }
static void static void
nve0_ibus_intr(struct nouveau_subdev *subdev) gk104_ibus_intr(struct nvkm_subdev *subdev)
{ {
struct nve0_ibus_priv *priv = (void *)subdev; struct gk104_ibus_priv *priv = (void *)subdev;
u32 intr0 = nv_rd32(priv, 0x120058); u32 intr0 = nv_rd32(priv, 0x120058);
u32 intr1 = nv_rd32(priv, 0x12005c); u32 intr1 = nv_rd32(priv, 0x12005c);
u32 hubnr = nv_rd32(priv, 0x120070); u32 hubnr = nv_rd32(priv, 0x120070);
@ -72,7 +71,7 @@ nve0_ibus_intr(struct nouveau_subdev *subdev)
for (i = 0; (intr0 & 0x0000ff00) && i < hubnr; i++) { for (i = 0; (intr0 & 0x0000ff00) && i < hubnr; i++) {
u32 stat = 0x00000100 << i; u32 stat = 0x00000100 << i;
if (intr0 & stat) { if (intr0 & stat) {
nve0_ibus_intr_hub(priv, i); gk104_ibus_intr_hub(priv, i);
intr0 &= ~stat; intr0 &= ~stat;
} }
} }
@ -80,7 +79,7 @@ nve0_ibus_intr(struct nouveau_subdev *subdev)
for (i = 0; (intr0 & 0xffff0000) && i < ropnr; i++) { for (i = 0; (intr0 & 0xffff0000) && i < ropnr; i++) {
u32 stat = 0x00010000 << i; u32 stat = 0x00010000 << i;
if (intr0 & stat) { if (intr0 & stat) {
nve0_ibus_intr_rop(priv, i); gk104_ibus_intr_rop(priv, i);
intr0 &= ~stat; intr0 &= ~stat;
} }
} }
@ -88,17 +87,17 @@ nve0_ibus_intr(struct nouveau_subdev *subdev)
for (i = 0; intr1 && i < gpcnr; i++) { for (i = 0; intr1 && i < gpcnr; i++) {
u32 stat = 0x00000001 << i; u32 stat = 0x00000001 << i;
if (intr1 & stat) { if (intr1 & stat) {
nve0_ibus_intr_gpc(priv, i); gk104_ibus_intr_gpc(priv, i);
intr1 &= ~stat; intr1 &= ~stat;
} }
} }
} }
static int static int
nve0_ibus_init(struct nouveau_object *object) gk104_ibus_init(struct nvkm_object *object)
{ {
struct nve0_ibus_priv *priv = (void *)object; struct gk104_ibus_priv *priv = (void *)object;
int ret = nouveau_ibus_init(&priv->base); int ret = nvkm_ibus_init(&priv->base);
if (ret == 0) { if (ret == 0) {
nv_mask(priv, 0x122318, 0x0003ffff, 0x00001000); nv_mask(priv, 0x122318, 0x0003ffff, 0x00001000);
nv_mask(priv, 0x12231c, 0x0003ffff, 0x00000200); nv_mask(priv, 0x12231c, 0x0003ffff, 0x00000200);
@ -112,29 +111,29 @@ nve0_ibus_init(struct nouveau_object *object)
} }
static int static int
nve0_ibus_ctor(struct nouveau_object *parent, struct nouveau_object *engine, gk104_ibus_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size, struct nvkm_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject) struct nvkm_object **pobject)
{ {
struct nve0_ibus_priv *priv; struct gk104_ibus_priv *priv;
int ret; int ret;
ret = nouveau_ibus_create(parent, engine, oclass, &priv); ret = nvkm_ibus_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv); *pobject = nv_object(priv);
if (ret) if (ret)
return ret; return ret;
nv_subdev(priv)->intr = nve0_ibus_intr; nv_subdev(priv)->intr = gk104_ibus_intr;
return 0; return 0;
} }
struct nouveau_oclass struct nvkm_oclass
nve0_ibus_oclass = { gk104_ibus_oclass = {
.handle = NV_SUBDEV(IBUS, 0xe0), .handle = NV_SUBDEV(IBUS, 0xe0),
.ofuncs = &(struct nouveau_ofuncs) { .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nve0_ibus_ctor, .ctor = gk104_ibus_ctor,
.dtor = _nouveau_ibus_dtor, .dtor = _nvkm_ibus_dtor,
.init = nve0_ibus_init, .init = gk104_ibus_init,
.fini = _nouveau_ibus_fini, .fini = _nvkm_ibus_fini,
}, },
}; };

25
drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk20a.c
View File

@ -19,12 +19,11 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE. * DEALINGS IN THE SOFTWARE.
*/ */
#include <subdev/ibus.h> #include <subdev/ibus.h>
#include <subdev/timer.h> #include <subdev/timer.h>
struct gk20a_ibus_priv { struct gk20a_ibus_priv {
struct nouveau_ibus base; struct nvkm_ibus base;
}; };
static void static void
@ -42,7 +41,7 @@ gk20a_ibus_init_priv_ring(struct gk20a_ibus_priv *priv)
} }
static void static void
gk20a_ibus_intr(struct nouveau_subdev *subdev) gk20a_ibus_intr(struct nvkm_subdev *subdev)
{ {
struct gk20a_ibus_priv *priv = (void *)subdev; struct gk20a_ibus_priv *priv = (void *)subdev;
u32 status0 = nv_rd32(priv, 0x120058); u32 status0 = nv_rd32(priv, 0x120058);
@ -60,12 +59,12 @@ gk20a_ibus_intr(struct nouveau_subdev *subdev)
} }
static int static int
gk20a_ibus_init(struct nouveau_object *object) gk20a_ibus_init(struct nvkm_object *object)
{ {
struct gk20a_ibus_priv *priv = (void *)object; struct gk20a_ibus_priv *priv = (void *)object;
int ret; int ret;
ret = _nouveau_ibus_init(object); ret = _nvkm_ibus_init(object);
if (ret) if (ret)
return ret; return ret;
@ -75,14 +74,14 @@ gk20a_ibus_init(struct nouveau_object *object)
} }
static int static int
gk20a_ibus_ctor(struct nouveau_object *parent, struct nouveau_object *engine, gk20a_ibus_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size, struct nvkm_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject) struct nvkm_object **pobject)
{ {
struct gk20a_ibus_priv *priv; struct gk20a_ibus_priv *priv;
int ret; int ret;
ret = nouveau_ibus_create(parent, engine, oclass, &priv); ret = nvkm_ibus_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv); *pobject = nv_object(priv);
if (ret) if (ret)
return ret; return ret;
@ -91,13 +90,13 @@ gk20a_ibus_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0; return 0;
} }
struct nouveau_oclass struct nvkm_oclass
gk20a_ibus_oclass = { gk20a_ibus_oclass = {
.handle = NV_SUBDEV(IBUS, 0xea), .handle = NV_SUBDEV(IBUS, 0xea),
.ofuncs = &(struct nouveau_ofuncs) { .ofuncs = &(struct nvkm_ofuncs) {
.ctor = gk20a_ibus_ctor, .ctor = gk20a_ibus_ctor,
.dtor = _nouveau_ibus_dtor, .dtor = _nvkm_ibus_dtor,
.init = gk20a_ibus_init, .init = gk20a_ibus_init,
.fini = _nouveau_ibus_fini, .fini = _nvkm_ibus_fini,
}, },
}; };