leandrof/linux
1
0
Fork 0
forked from Minki/linux
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Pin control bulk changes for v6.0:

Browse Source 
Core changes:
 
 - Add PINCTRL_PINGROUP() helper macro (and use it in the AMD driver).
 
 New drivers:
 
 - Intel Meteor Lake support.
 
 - Reneasas RZ/V2M and r8a779g0 (R-Car V4H).
 
 - AXP209 variants AXP221, AXP223 and AXP809.
 
 - Qualcomm MSM8909, PM8226, PMP8074 and SM6375.
 
 - Allwinner D1.
 
 Improvements:
 
 - Proper pin multiplexing in the AMD driver.
 
 - Mediatek MT8192 can use generic drive strength and pin
   bias, then fixes on top plus some I2C pin group fixes.
 
 - Have the Allwinner Sunplus SP7021 use the generic DT schema and
   make interrupts optional.
 
 - Handle Qualcomm SC7280 ADSP.
 
 - Handle Qualcomm MSM8916 CAMSS GP clock muxing.
 
 - High impedance bias on ZynqMP.
 
 - Serialize StarFive access to MMIO.
 
 - Immutable gpiochip for BCM2835, Ingenic, Qualcomm SPMI GPIO.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAmLy1PoACgkQQRCzN7AZ
 XXOavA/+O9lIcZqt/I3ZzA4+paEJsXM/win6NKGUHlAE76D5qOvMEXPYCszccGVl
 0ZV9s3A3xmlb0AQZONeiK5M6FTghnIHiPMI5Ewzw358hZQg68Mgaba5+/yTqc9ZT
 L5zs6whboB1Mlr05L3g5e5ImM1FdFklGHimI6G/evE5r1ZXAAdoyXbSzWgtgLwp9
 Gn3rstfqxwwPa9QWIjCXXIeZ/EFnX6BRFT5Pu47dRz/67UWB3xzJjRkZXBf8Nag9
 /H/TpmkXSFNaP8HK2kN8m5eNtfWLYM1AmjFPNICWtKLhH12ArD3j+MBYLcJoDnAI
 JZryrMSFi2P14Ov42zYeJaSjReTt/QBcRAlWBhSiuotJHl6wrFXzM6wA6JirfvsJ
 XQsNm7rKfkmfJ84VjqmCg6QF+39fwKw9MYY9IMXsey7864pBWSyl2xYXUjwXFLua
 EWh+6I1CX4db/S6I/uqvluDenT0NKAPZ3rwK5Al1m1DMI47kz0qoW5ZxAW10xeYB
 BNGN7IyRvYZhfA/DHcxMB5XgateIKTJqfcYnmHD29Ep4skEetOSac0wVytd3S+Hw
 v1zklpcGDLHNiCBXmTYniTlfgBkWJUmVCLA4K6TjSNUKfeoR+33wlpnPHveq8ckn
 PJLf79A+5Br3IsLnr6AzDrmtCd0sV46Gy8Vi5I1TD1i/LUUhnL0=
 =enmk
 -----END PGP SIGNATURE-----

Merge tag 'pinctrl-v6.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "Outside the pinctrl driver and DT bindings we hit some Arm DT files,
  patched by the maintainers.

  Other than that it is business as usual.

  Core changes:

   - Add PINCTRL_PINGROUP() helper macro (and use it in the AMD driver).

  New drivers:

   - Intel Meteor Lake support.

   - Reneasas RZ/V2M and r8a779g0 (R-Car V4H).

   - AXP209 variants AXP221, AXP223 and AXP809.

   - Qualcomm MSM8909, PM8226, PMP8074 and SM6375.

   - Allwinner D1.

  Improvements:

   - Proper pin multiplexing in the AMD driver.

   - Mediatek MT8192 can use generic drive strength and pin bias, then
     fixes on top plus some I2C pin group fixes.

   - Have the Allwinner Sunplus SP7021 use the generic DT schema and
     make interrupts optional.

   - Handle Qualcomm SC7280 ADSP.

   - Handle Qualcomm MSM8916 CAMSS GP clock muxing.

   - High impedance bias on ZynqMP.

   - Serialize StarFive access to MMIO.

   - Immutable gpiochip for BCM2835, Ingenic, Qualcomm SPMI GPIO"

* tag 'pinctrl-v6.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (117 commits)
  dt-bindings: pinctrl: qcom,pmic-gpio: add PM8226 constraints
  pinctrl: qcom: Make PINCTRL_SM8450 depend on PINCTRL_MSM
  pinctrl: qcom: sm8250: Fix PDC map
  pinctrl: amd: Fix an unused variable
  dt-bindings: pinctrl: mt8186: Add and use drive-strength-microamp
  dt-bindings: pinctrl: mt8186: Add gpio-line-names property
  ARM: dts: imxrt1170-pinfunc: Add pinctrl binding header
  pinctrl: amd: Use unicode for debugfs output
  pinctrl: amd: Fix newline declaration in debugfs output
  pinctrl: at91: Fix typo 'the the' in comment
  dt-bindings: pinctrl: st,stm32: Correct 'resets' property name
  pinctrl: mvebu: Missing a blank line after declarations.
  pinctrl: qcom: Add SM6375 TLMM driver
  dt-bindings: pinctrl: Add DT schema for SM6375 TLMM
  dt-bindings: pinctrl: mt8195: Use drive-strength-microamp in examples
  Revert "pinctrl: qcom: spmi-gpio: make the irqchip immutable"
  pinctrl: imx93: Add MODULE_DEVICE_TABLE()
  pinctrl: sunxi: Add driver for Allwinner D1
  pinctrl: sunxi: Make some layout parameters dynamic
  pinctrl: sunxi: Refactor register/offset calculation
  ...
This commit is contained in:
Linus Torvalds 2022-08-10 11:01:44 -07:00
commit 5e2e7383b5
88 changed files with 13352 additions and 665 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
Documentation/devicetree/bindings/gpio/x-powers,axp209-gpio.yaml
View File

@ -19,7 +19,13 @@ properties:
oneOf:
- enum:
- x-powers,axp209-gpio
- x-powers,axp221-gpio
- x-powers,axp813-gpio
- items:
- enum:
- x-powers,axp223-gpio
- x-powers,axp809-gpio
- const: x-powers,axp221-gpio
- items:
- const: x-powers,axp803-gpio
- const: x-powers,axp813-gpio

16
Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
View File

@ -46,6 +46,7 @@ properties:
- allwinner,sun8i-v3s-pinctrl
- allwinner,sun9i-a80-pinctrl
- allwinner,sun9i-a80-r-pinctrl
- allwinner,sun20i-d1-pinctrl
- allwinner,sun50i-a64-pinctrl
- allwinner,sun50i-a64-r-pinctrl
- allwinner,sun50i-a100-pinctrl
@ -80,9 +81,6 @@ properties:
- const: hosc
- const: losc
resets:
maxItems: 1
gpio-controller: true
interrupt-controller: true
gpio-line-names: true
@ -181,6 +179,18 @@ allOf:
minItems: 7
maxItems: 7
- if:
properties:
compatible:
enum:
- allwinner,sun20i-d1-pinctrl
then:
properties:
interrupts:
minItems: 6
maxItems: 6
- if:
properties:
compatible:

2
Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml
View File

@ -152,7 +152,7 @@ examples:
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uid>, <&pinmux_uid>;
uid {
button-uid {
label = "UID";
linux,code = <102>;
gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;

31
Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml
View File

@ -28,6 +28,8 @@ properties:
gpio-ranges:
maxItems: 1
gpio-line-names: true
reg:
description: |
Physical address base for gpio base registers. There are 8 different GPIO
@ -105,31 +107,8 @@ patternProperties:
drive-strength:
enum: [2, 4, 6, 8, 10, 12, 14, 16]
mediatek,drive-strength-adv:
description: |
Describe the specific driving setup property.
For I2C pins, the existing generic driving setup can only support
2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they
can support 0.125/0.25/0.5/1mA adjustment. If we enable specific
driving setup, the existing generic setup will be disabled.
The specific driving setup is controlled by E1E0EN.
When E1=0/E0=0, the strength is 0.125mA.
When E1=0/E0=1, the strength is 0.25mA.
When E1=1/E0=0, the strength is 0.5mA.
When E1=1/E0=1, the strength is 1mA.
EN is used to enable or disable the specific driving setup.
Valid arguments are described as below:
0: (E1, E0, EN) = (0, 0, 0)
1: (E1, E0, EN) = (0, 0, 1)
2: (E1, E0, EN) = (0, 1, 0)
3: (E1, E0, EN) = (0, 1, 1)
4: (E1, E0, EN) = (1, 0, 0)
5: (E1, E0, EN) = (1, 0, 1)
6: (E1, E0, EN) = (1, 1, 0)
7: (E1, E0, EN) = (1, 1, 1)
So the valid arguments are from 0 to 7.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3, 4, 5, 6, 7]
drive-strength-microamp:
enum: [125, 250, 500, 1000]
bias-pull-down:
oneOf:
@ -291,7 +270,7 @@ examples:
pinmux = <PINMUX_GPIO127__FUNC_SCL0>,
<PINMUX_GPIO128__FUNC_SDA0>;
bias-pull-up = <MTK_PULL_SET_RSEL_001>;
mediatek,drive-strength-adv = <7>;
drive-strength-microamp = <1000>;
};
};
};

60
Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml
View File

@ -80,46 +80,30 @@ patternProperties:
dt-bindings/pinctrl/mt65xx.h. It can only support 2/4/6/8/10/12/14/16mA in mt8192.
enum: [2, 4, 6, 8, 10, 12, 14, 16]
mediatek,drive-strength-adv:
description: |
Describe the specific driving setup property.
For I2C pins, the existing generic driving setup can only support
2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they
can support 0.125/0.25/0.5/1mA adjustment. If we enable specific
driving setup, the existing generic setup will be disabled.
The specific driving setup is controlled by E1E0EN.
When E1=0/E0=0, the strength is 0.125mA.
When E1=0/E0=1, the strength is 0.25mA.
When E1=1/E0=0, the strength is 0.5mA.
When E1=1/E0=1, the strength is 1mA.
EN is used to enable or disable the specific driving setup.
Valid arguments are described as below:
0: (E1, E0, EN) = (0, 0, 0)
1: (E1, E0, EN) = (0, 0, 1)
2: (E1, E0, EN) = (0, 1, 0)
3: (E1, E0, EN) = (0, 1, 1)
4: (E1, E0, EN) = (1, 0, 0)
5: (E1, E0, EN) = (1, 0, 1)
6: (E1, E0, EN) = (1, 1, 0)
7: (E1, E0, EN) = (1, 1, 1)
So the valid arguments are from 0 to 7.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3, 4, 5, 6, 7]
drive-strength-microamp:
enum: [125, 250, 500, 1000]
mediatek,pull-up-adv:
description: |
Pull up settings for 2 pull resistors, R0 and R1. User can
configure those special pins. Valid arguments are described as below:
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
bias-pull-down:
oneOf:
- type: boolean
description: normal pull down.
- enum: [100, 101, 102, 103]
description: PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0_
defines in dt-bindings/pinctrl/mt65xx.h.
- enum: [200, 201, 202, 203]
description: RSEL pull down type. See MTK_PULL_SET_RSEL_
defines in dt-bindings/pinctrl/mt65xx.h.
bias-pull-down: true
bias-pull-up: true
bias-pull-up:
oneOf:
- type: boolean
description: normal pull up.
- enum: [100, 101, 102, 103]
description: PUPD/R1/R0 pull up type. See MTK_PUPD_SET_R1R0_
defines in dt-bindings/pinctrl/mt65xx.h.
- enum: [200, 201, 202, 203]
description: RSEL pull up type. See MTK_PULL_SET_RSEL_
defines in dt-bindings/pinctrl/mt65xx.h.
bias-disable: true

41
Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml
View File

@ -29,6 +29,8 @@ properties:
description: gpio valid number range.
maxItems: 1
gpio-line-names: true
reg:
description: |
Physical address base for gpio base registers. There are 8 GPIO
@ -49,7 +51,7 @@ properties:
description: The interrupt outputs to sysirq.
maxItems: 1
mediatek,rsel_resistance_in_si_unit:
mediatek,rsel-resistance-in-si-unit:
type: boolean
description: |
Identifying i2c pins pull up/down type which is RSEL. It can support
@ -98,31 +100,8 @@ patternProperties:
drive-strength:
enum: [2, 4, 6, 8, 10, 12, 14, 16]
mediatek,drive-strength-adv:
description: |
Describe the specific driving setup property.
For I2C pins, the existing generic driving setup can only support
2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they
can support 0.125/0.25/0.5/1mA adjustment. If we enable specific
driving setup, the existing generic setup will be disabled.
The specific driving setup is controlled by E1E0EN.
When E1=0/E0=0, the strength is 0.125mA.
When E1=0/E0=1, the strength is 0.25mA.
When E1=1/E0=0, the strength is 0.5mA.
When E1=1/E0=1, the strength is 1mA.
EN is used to enable or disable the specific driving setup.
Valid arguments are described as below:
0: (E1, E0, EN) = (0, 0, 0)
1: (E1, E0, EN) = (0, 0, 1)
2: (E1, E0, EN) = (0, 1, 0)
3: (E1, E0, EN) = (0, 1, 1)
4: (E1, E0, EN) = (1, 0, 0)
5: (E1, E0, EN) = (1, 0, 1)
6: (E1, E0, EN) = (1, 1, 0)
7: (E1, E0, EN) = (1, 1, 1)
So the valid arguments are from 0 to 7.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3, 4, 5, 6, 7]
drive-strength-microamp:
enum: [125, 250, 500, 1000]
bias-pull-down:
oneOf:
@ -142,7 +121,7 @@ patternProperties:
"MTK_PUPD_SET_R1R0_11" define in mt8195.
For pull down type is RSEL, it can add RSEL define & resistance
value(ohm) to set different resistance by identifying property
"mediatek,rsel_resistance_in_si_unit".
"mediatek,rsel-resistance-in-si-unit".
It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001"
& "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011"
& "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101"
@ -161,7 +140,7 @@ patternProperties:
};
An example of using si unit resistance value(ohm):
&pio {
mediatek,rsel_resistance_in_si_unit;
mediatek,rsel-resistance-in-si-unit;
}
pincontroller {
i2c0_pin {
@ -190,7 +169,7 @@ patternProperties:
"MTK_PUPD_SET_R1R0_11" define in mt8195.
For pull up type is RSEL, it can add RSEL define & resistance
value(ohm) to set different resistance by identifying property
"mediatek,rsel_resistance_in_si_unit".
"mediatek,rsel-resistance-in-si-unit".
It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001"
& "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011"
& "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101"
@ -209,7 +188,7 @@ patternProperties:
};
An example of using si unit resistance value(ohm):
&pio {
mediatek,rsel_resistance_in_si_unit;
mediatek,rsel-resistance-in-si-unit;
}
pincontroller {
i2c0-pins {
@ -302,7 +281,7 @@ examples:
pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
<PINMUX_GPIO9__FUNC_SCL0>;
bias-disable;
mediatek,drive-strength-adv = <7>;
drive-strength-microamp = <1000>;
};
};
};

152
Documentation/devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml Normal file
View File

@ -0,0 +1,152 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,msm8909-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. MSM8909 TLMM block
maintainers:
- Stephan Gerhold <stephan@gerhold.net>
description: |
This binding describes the Top Level Mode Multiplexer (TLMM) block found
in the MSM8909 platform.
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
properties:
compatible:
const: qcom,msm8909-tlmm
reg:
maxItems: 1
interrupts: true
interrupt-controller: true
'#interrupt-cells': true
gpio-controller: true
gpio-reserved-ranges: true
'#gpio-cells': true
gpio-ranges: true
wakeup-parent: true
required:
- compatible
- reg
additionalProperties: false
patternProperties:
'-state$':
oneOf:
- $ref: "#/$defs/qcom-msm8909-tlmm-state"
- patternProperties:
".*":
$ref: "#/$defs/qcom-msm8909-tlmm-state"
$defs:
qcom-msm8909-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-7])$"
- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
sdc2_data, qdsd_clk, qdsd_cmd, qdsd_data0, qdsd_data1,
qdsd_data2, qdsd_data3 ]
minItems: 1
maxItems: 16
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ adsp_ext, atest_bbrx0, atest_bbrx1, atest_char, atest_char0,
atest_char1, atest_char2, atest_char3, atest_combodac,
atest_gpsadc0, atest_gpsadc1, atest_wlan0, atest_wlan1,
bimc_dte0, bimc_dte1, blsp_i2c1, blsp_i2c2, blsp_i2c3,
blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_spi1, blsp_spi1_cs1,
blsp_spi1_cs2, blsp_spi1_cs3, blsp_spi2, blsp_spi2_cs1,
blsp_spi2_cs2, blsp_spi2_cs3, blsp_spi3, blsp_spi3_cs1,
blsp_spi3_cs2, blsp_spi3_cs3, blsp_spi4, blsp_spi5, blsp_spi6,
blsp_uart1, blsp_uart2, blsp_uim1, blsp_uim2, cam_mclk,
cci_async, cci_timer0, cci_timer1, cci_timer2, cdc_pdm0,
dbg_out, dmic0_clk, dmic0_data, ebi0_wrcdc, ebi2_a, ebi2_lcd,
ext_lpass, gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a,
gcc_gp2_clk_b, gcc_gp3_clk_a, gcc_gp3_clk_b, gcc_plltest, gpio,
gsm0_tx, ldo_en, ldo_update, m_voc, mdp_vsync, modem_tsync,
nav_pps, nav_tsync, pa_indicator, pbs0, pbs1, pbs2,
pri_mi2s_data0_a, pri_mi2s_data0_b, pri_mi2s_data1_a,
pri_mi2s_data1_b, pri_mi2s_mclk_a, pri_mi2s_mclk_b,
pri_mi2s_sck_a, pri_mi2s_sck_b, pri_mi2s_ws_a, pri_mi2s_ws_b,
prng_rosc, pwr_crypto_enabled_a, pwr_crypto_enabled_b,
pwr_modem_enabled_a, pwr_modem_enabled_b, pwr_nav_enabled_a,
pwr_nav_enabled_b, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1,
qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_a0,
qdss_cti_trig_out_a1, qdss_cti_trig_out_b0,
qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_tracectl_a,
qdss_tracedata_a, qdss_tracedata_b, sd_write, sec_mi2s,
smb_int, ssbi0, ssbi1, uim1_clk, uim1_data, uim1_present,
uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset,
uim3_clk, uim3_data, uim3_present, uim3_reset, uim_batt,
wcss_bt, wcss_fm, wcss_wlan ]
bias-disable: true
bias-pull-down: true
bias-pull-up: true
drive-strength: true
input-enable: true
output-high: true
output-low: true
required:
- pins
- function
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
pinctrl@1000000 {
compatible = "qcom,msm8909-tlmm";
reg = <0x1000000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 117>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-wo-subnode-state {
pins = "gpio1";
function = "gpio";
};
uart-w-subnodes-state {
rx {
pins = "gpio4";
function = "blsp_uart1";
bias-pull-up;
};
tx {
pins = "gpio5";
function = "blsp_uart1";
bias-disable;
};
};
};
...

4
Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml
View File

@ -52,6 +52,7 @@ properties:
- qcom,pmi8998-gpio
- qcom,pmk8350-gpio
- qcom,pmm8155au-gpio
- qcom,pmp8074-gpio
- qcom,pmr735a-gpio
- qcom,pmr735b-gpio
- qcom,pms405-gpio
@ -158,6 +159,7 @@ allOf:
compatible:
contains:
enum:
- qcom,pm8226-gpio
- qcom,pm8350b-gpio
- qcom,pm8950-gpio
then:
@ -233,6 +235,7 @@ allOf:
- qcom,pm8150b-gpio
- qcom,pm8150l-gpio
- qcom,pmc8180c-gpio
- qcom,pmp8074-gpio
- qcom,pms405-gpio
then:
properties:
@ -415,6 +418,7 @@ $defs:
- gpio1-gpio10 for pmi8994
- gpio1-gpio4 for pmk8350
- gpio1-gpio10 for pmm8155au
- gpio1-gpio12 for pmp8074 (holes on gpio1 and gpio12)
- gpio1-gpio4 for pmr735a
- gpio1-gpio4 for pmr735b
- gpio1-gpio12 for pms405 (holes on gpio1, gpio9

5
Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml
View File

@ -19,6 +19,11 @@ properties:
compatible:
const: qcom,sc7280-lpass-lpi-pinctrl
qcom,adsp-bypass-mode:
description:
Tells ADSP is in bypass mode.
type: boolean
reg:
minItems: 2
maxItems: 2

158
Documentation/devicetree/bindings/pinctrl/qcom,sm6375-tlmm.yaml Normal file
View File

@ -0,0 +1,158 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sm6375-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. SM6375 TLMM block
maintainers:
- Konrad Dybcio <konrad.dybcio@somainline.org>
description: |
This binding describes the Top Level Mode Multiplexer (TLMM) block found
in the SM6375 platform.
allOf:
- $ref: "pinctrl.yaml#"
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
properties:
compatible:
const: qcom,sm6375-tlmm
reg:
maxItems: 1
interrupts: true
interrupt-controller: true
'#interrupt-cells': true
gpio-controller: true
gpio-reserved-ranges: true
'#gpio-cells': true
gpio-ranges: true
wakeup-parent: true
required:
- compatible
- reg
additionalProperties: false
patternProperties:
'-state$':
oneOf:
- $ref: "#/$defs/qcom-sm6375-tlmm-state"
- patternProperties:
".*":
$ref: "#/$defs/qcom-sm6375-tlmm-state"
$defs:
qcom-sm6375-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-6])$"
- enum: [ ufs_reset, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
sdc2_cmd, sdc2_data ]
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ adsp_ext, agera_pll, atest_char, atest_char0, atest_char1,
atest_char2, atest_char3, atest_tsens, atest_tsens2,
atest_usb1, atest_usb10, atest_usb11, atest_usb12,
atest_usb13, atest_usb2, atest_usb20, atest_usb21,
atest_usb22, atest_usb23, audio_ref, btfm_slimbus, cam_mclk,
cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2,
cci_timer3, cci_timer4, cri_trng, dbg_out, ddr_bist,
ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, edp_lcd,
gcc_gp1, gcc_gp2, gcc_gp3, gp_pdm0, gp_pdm1, gp_pdm2, gpio,
gps_tx, ibi_i3c, jitter_bist, ldo_en, ldo_update, lpass_ext,
m_voc, mclk, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
mdp_vsync3, mi2s_0, mi2s_1, mi2s_2, mss_lte, nav_gpio,
nav_pps, pa_indicator, phase_flag0, phase_flag1, phase_flag10,
phase_flag11, phase_flag12, phase_flag13, phase_flag14,
phase_flag15, phase_flag16, phase_flag17, phase_flag18,
phase_flag19, phase_flag2, phase_flag20, phase_flag21,
phase_flag22, phase_flag23, phase_flag24, phase_flag25,
phase_flag26, phase_flag27, phase_flag28, phase_flag29,
phase_flag3, phase_flag30, phase_flag31, phase_flag4,
phase_flag5, phase_flag6, phase_flag7, phase_flag8,
phase_flag9, pll_bist, pll_bypassnl, pll_clk, pll_reset,
prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti,
qdss_gpio, qdss_gpio0, qdss_gpio1, qdss_gpio10, qdss_gpio11,
qdss_gpio12, qdss_gpio13, qdss_gpio14, qdss_gpio15,
qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6,
qdss_gpio7, qdss_gpio8, qdss_gpio9, qlink0_enable,
qlink0_request, qlink0_wmss, qlink1_enable, qlink1_request,
qlink1_wmss, qup00, qup01, qup02, qup10, qup11_f1, qup11_f2,
qup12, qup13_f1, qup13_f2, qup14, sd_write, sdc1_tb, sdc2_tb,
sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1,
tsense_pwm2, uim1_clk, uim1_data, uim1_present, uim1_reset,
uim2_clk, uim2_data, uim2_present, uim2_reset, usb2phy_ac,
usb_phy, vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1,
wlan2_adc0, wlan2_adc1 ]
bias-disable: true
bias-pull-down: true
bias-pull-up: true
drive-strength: true
input-enable: true
output-high: true
output-low: true
required:
- pins
- function
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
pinctrl@500000 {
compatible = "qcom,sm6375-tlmm";
reg = <0x00500000 0x800000>;
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 157>;
gpio-wo-subnode-state {
pins = "gpio1";
function = "gpio";
};
uart-w-subnodes-state {
rx {
pins = "gpio18";
function = "qup13_f2";
bias-pull-up;
};
tx {
pins = "gpio19";
function = "qup13_f2";
bias-disable;
};
};
};
...

1
Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml
View File

@ -45,6 +45,7 @@ properties:
- renesas,pfc-r8a77995 # R-Car D3
- renesas,pfc-r8a779a0 # R-Car V3U
- renesas,pfc-r8a779f0 # R-Car S4-8
- renesas,pfc-r8a779g0 # R-Car V4H
- renesas,pfc-sh73a0 # SH-Mobile AG5
reg:

170
Documentation/devicetree/bindings/pinctrl/renesas,rzv2m-pinctrl.yaml Normal file
View File

@ -0,0 +1,170 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/renesas,rzv2m-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/V2M combined Pin and GPIO controller
maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
- Phil Edworthy <phil.edworthy@renesas.com>
description:
The Renesas RZ/V2M SoC features a combined Pin and GPIO controller.
Pin multiplexing and GPIO configuration is performed on a per-pin basis.
Each port features up to 16 pins, each of them configurable for GPIO function
(port mode) or in alternate function mode.
Up to 8 different alternate function modes exist for each single pin.
properties:
compatible:
const: renesas,r9a09g011-pinctrl # RZ/V2M
reg:
maxItems: 1
gpio-controller: true
'#gpio-cells':
const: 2
description:
The first cell contains the global GPIO port index, constructed using the
RZV2M_GPIO() helper macro in <dt-bindings/pinctrl/rzv2m-pinctrl.h> and the
second cell represents consumer flag as mentioned in ../gpio/gpio.txt
E.g. "RZV2M_GPIO(8, 1)" for P8_1.
gpio-ranges:
maxItems: 1
interrupts:
description: INEXINT[0..38] corresponding to individual pin inputs.
maxItems: 39
clocks:
maxItems: 1
power-domains:
maxItems: 1
resets:
maxItems: 1
additionalProperties:
anyOf:
- type: object
allOf:
- $ref: pincfg-node.yaml#
- $ref: pinmux-node.yaml#
description:
Pin controller client devices use pin configuration subnodes (children
and grandchildren) for desired pin configuration.
Client device subnodes use below standard properties.
properties:
phandle: true
pinmux:
description:
Values are constructed from GPIO port number, pin number, and
alternate function configuration number using the RZV2M_PORT_PINMUX()
helper macro in <dt-bindings/pinctrl/rzv2m-pinctrl.h>.
pins: true
bias-disable: true
bias-pull-down: true
bias-pull-up: true
drive-strength-microamp:
# Superset of supported values
enum: [ 1600, 1800, 2000, 3200, 3800, 4000, 6400, 7800, 8000,
9000, 9600, 11000, 12000, 13000, 18000 ]
slew-rate:
description: 0 is slow slew rate, 1 is fast slew rate
enum: [ 0, 1 ]
gpio-hog: true
gpios: true
output-high: true
output-low: true
line-name: true
- type: object
properties:
phandle: true
additionalProperties:
$ref: "#/additionalProperties/anyOf/0"
allOf:
- $ref: "pinctrl.yaml#"
required:
- compatible
- reg
- gpio-controller
- '#gpio-cells'
- gpio-ranges
- interrupts
- clocks
- power-domains
- resets
examples:
- |
#include <dt-bindings/pinctrl/rzv2m-pinctrl.h>
#include <dt-bindings/clock/r9a09g011-cpg.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
pinctrl: pinctrl@b6250000 {
compatible = "renesas,r9a09g011-pinctrl";
reg = <0xb6250000 0x800>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 352>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A09G011_PFC_PCLK>;
resets = <&cpg R9A09G011_PFC_PRESETN>;
power-domains = <&cpg>;
i2c2_pins: i2c2 {
pinmux = <RZV2M_PORT_PINMUX(3, 8, 2)>, /* SDA */
<RZV2M_PORT_PINMUX(3, 9, 2)>; /* SCL */
};
};

4
Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
View File

@ -59,6 +59,7 @@ properties:
patternProperties:
'^gpio@[0-9a-f]*$':
type: object
additionalProperties: false
properties:
gpio-controller: true
'#gpio-cells':
@ -68,8 +69,7 @@ patternProperties:
maxItems: 1
clocks:
maxItems: 1
reset:
minItems: 1
resets:
maxItems: 1
gpio-ranges:
minItems: 1

5
Documentation/devicetree/bindings/pinctrl/sunplus,sp7021-pinctrl.yaml
View File

@ -288,11 +288,14 @@ required:
additionalProperties: false
allOf:
- $ref: "pinctrl.yaml#"
examples:
- |
#include <dt-bindings/pinctrl/sppctl-sp7021.h>
pinctl@9c000100 {
pinctrl@9c000100 {
compatible = "sunplus,sp7021-pctl";
reg = <0x9c000100 0x100>, <0x9c000300 0x100>,
<0x9c0032e4 0x1c>, <0x9c000080 0x20>;

4
Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml
View File

@ -274,6 +274,10 @@ patternProperties:
slew-rate:
enum: [0, 1]
output-enable:
description:
This will internally disable the tri-state for MIO pins.
drive-strength:
description:
Selects the drive strength for MIO pins, in mA.

1
MAINTAINERS
View File

@ -16061,6 +16061,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git
F: Documentation/devicetree/bindings/pinctrl/
F: Documentation/driver-api/pin-control.rst
F: drivers/pinctrl/
F: include/dt-bindings/pinctrl/
F: include/linux/pinctrl/
PIN CONTROLLER - AMD

1561
arch/arm/boot/dts/imxrt1170-pinfunc.h Normal file
View File

File diff suppressed because it is too large Load Diff

1
arch/arm/boot/dts/sun6i-a31.dtsi
View File

@ -1389,7 +1389,6 @@
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apb0_gates 0>, <&osc24M>, <&rtc CLK_OSC32K>;
clock-names = "apb", "hosc", "losc";
resets = <&apb0_rst 0>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;

1
arch/arm/boot/dts/sun8i-a23-a33.dtsi
View File

@ -814,7 +814,6 @@
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apb0_gates 0>, <&osc24M>, <&rtc CLK_OSC32K>;
clock-names = "apb", "hosc", "losc";
resets = <&apb0_rst 0>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;

1
arch/arm/boot/dts/sun9i-a80.dtsi
View File

@ -1218,7 +1218,6 @@
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apbs_gates 0>, <&osc24M>, <&osc32k>;
clock-names = "apb", "hosc", "losc";
resets = <&apbs_rst 0>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;

2
drivers/pinctrl/Kconfig
View File

@ -311,7 +311,7 @@ config PINCTRL_MICROCHIP_SGPIO
LED controller.
config PINCTRL_OCELOT
bool "Pinctrl driver for the Microsemi Ocelot and Jaguar2 SoCs"
tristate "Pinctrl driver for the Microsemi Ocelot and Jaguar2 SoCs"
depends on OF
depends on HAS_IOMEM
select GPIOLIB

2
drivers/pinctrl/aspeed/pinmux-aspeed.h
View File

@ -632,7 +632,7 @@ struct aspeed_pin_desc {
SIG_EXPR_LIST_ALIAS(pin, sig, group)
/**
* Similar to the above, but for pins with a dual expressions (DE) and
* Similar to the above, but for pins with a dual expressions (DE)
* and a single group (SG) of pins.
*
* @pin: The pin the signal will be routed to

21
drivers/pinctrl/bcm/pinctrl-bcm2835.c
View File

@ -507,7 +507,7 @@ static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
}
}
static void bcm2835_gpio_irq_enable(struct irq_data *data)
static void bcm2835_gpio_irq_unmask(struct irq_data *data)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
@ -516,13 +516,15 @@ static void bcm2835_gpio_irq_enable(struct irq_data *data)
unsigned bank = GPIO_REG_OFFSET(gpio);
unsigned long flags;
gpiochip_enable_irq(chip, gpio);
raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
set_bit(offset, &pc->enabled_irq_map[bank]);
bcm2835_gpio_irq_config(pc, gpio, true);
raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
}
static void bcm2835_gpio_irq_disable(struct irq_data *data)
static void bcm2835_gpio_irq_mask(struct irq_data *data)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
@ -537,6 +539,8 @@ static void bcm2835_gpio_irq_disable(struct irq_data *data)
bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
clear_bit(offset, &pc->enabled_irq_map[bank]);
raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
gpiochip_disable_irq(chip, gpio);
}
static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc,
@ -693,16 +697,15 @@ static int bcm2835_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
return ret;
}
static struct irq_chip bcm2835_gpio_irq_chip = {
static const struct irq_chip bcm2835_gpio_irq_chip = {
.name = MODULE_NAME,
.irq_enable = bcm2835_gpio_irq_enable,
.irq_disable = bcm2835_gpio_irq_disable,
.irq_set_type = bcm2835_gpio_irq_set_type,
.irq_ack = bcm2835_gpio_irq_ack,
.irq_mask = bcm2835_gpio_irq_disable,
.irq_unmask = bcm2835_gpio_irq_enable,
.irq_mask = bcm2835_gpio_irq_mask,
.irq_unmask = bcm2835_gpio_irq_unmask,
.irq_set_wake = bcm2835_gpio_irq_set_wake,
.flags = IRQCHIP_MASK_ON_SUSPEND,
.flags = (IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE),
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)
@ -1280,7 +1283,7 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev)
pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
girq = &pc->gpio_chip.irq;
girq->chip = &bcm2835_gpio_irq_chip;
gpio_irq_chip_set_chip(girq, &bcm2835_gpio_irq_chip);
girq->parent_handler = bcm2835_gpio_irq_handler;
girq->num_parents = BCM2835_NUM_IRQS;
girq->parents = devm_kcalloc(dev, BCM2835_NUM_IRQS,

2
drivers/pinctrl/core.c
View File

@ -126,7 +126,7 @@ struct pinctrl_dev *get_pinctrl_dev_from_of_node(struct device_node *np)
mutex_lock(&pinctrldev_list_mutex);
list_for_each_entry(pctldev, &pinctrldev_list, node)
if (pctldev->dev->of_node == np) {
if (device_match_of_node(pctldev->dev, np)) {
mutex_unlock(&pinctrldev_list_mutex);
return pctldev;
}

1
drivers/pinctrl/freescale/pinctrl-imx93.c
View File

@ -247,6 +247,7 @@ static const struct of_device_id imx93_pinctrl_of_match[] = {
{ .compatible = "fsl,imx93-iomuxc", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx93_pinctrl_of_match);
static int imx93_pinctrl_probe(struct platform_device *pdev)
{

8
drivers/pinctrl/intel/Kconfig
View File

@ -151,6 +151,14 @@ config PINCTRL_LEWISBURG
This pinctrl driver provides an interface that allows configuring
of Intel Lewisburg pins and using them as GPIOs.
config PINCTRL_METEORLAKE
tristate "Intel Meteor Lake pinctrl and GPIO driver"
depends on ACPI
select PINCTRL_INTEL
help
This pinctrl driver provides an interface that allows configuring
of Intel Meteor Lake pins and using them as GPIOs.
config PINCTRL_SUNRISEPOINT
tristate "Intel Sunrisepoint pinctrl and GPIO driver"
depends on ACPI

1
drivers/pinctrl/intel/Makefile
View File

@ -18,5 +18,6 @@ obj-$(CONFIG_PINCTRL_ICELAKE) += pinctrl-icelake.o
obj-$(CONFIG_PINCTRL_JASPERLAKE) += pinctrl-jasperlake.o
obj-$(CONFIG_PINCTRL_LAKEFIELD) += pinctrl-lakefield.o
obj-$(CONFIG_PINCTRL_LEWISBURG) += pinctrl-lewisburg.o
obj-$(CONFIG_PINCTRL_METEORLAKE) += pinctrl-meteorlake.o
obj-$(CONFIG_PINCTRL_SUNRISEPOINT) += pinctrl-sunrisepoint.o
obj-$(CONFIG_PINCTRL_TIGERLAKE) += pinctrl-tigerlake.o

18
drivers/pinctrl/intel/pinctrl-baytrail.c
View File

@ -603,7 +603,7 @@ static const char *byt_get_group_name(struct pinctrl_dev *pctldev,
{
struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
return vg->soc->groups[selector].name;
return vg->soc->groups[selector].grp.name;
}
static int byt_get_group_pins(struct pinctrl_dev *pctldev,
@ -613,8 +613,8 @@ static int byt_get_group_pins(struct pinctrl_dev *pctldev,
{
struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
*pins = vg->soc->groups[selector].pins;
*num_pins = vg->soc->groups[selector].npins;
*pins = vg->soc->groups[selector].grp.pins;
*num_pins = vg->soc->groups[selector].grp.npins;
return 0;
}
@ -662,15 +662,15 @@ static void byt_set_group_simple_mux(struct intel_pinctrl *vg,
raw_spin_lock_irqsave(&byt_lock, flags);
for (i = 0; i < group.npins; i++) {
for (i = 0; i < group.grp.npins; i++) {
void __iomem *padcfg0;
u32 value;
padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
padcfg0 = byt_gpio_reg(vg, group.grp.pins[i], BYT_CONF0_REG);
if (!padcfg0) {
dev_warn(vg->dev,
"Group %s, pin %i not muxed (no padcfg0)\n",
group.name, i);
group.grp.name, i);
continue;
}
@ -692,15 +692,15 @@ static void byt_set_group_mixed_mux(struct intel_pinctrl *vg,
raw_spin_lock_irqsave(&byt_lock, flags);
for (i = 0; i < group.npins; i++) {
for (i = 0; i < group.grp.npins; i++) {
void __iomem *padcfg0;
u32 value;
padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
padcfg0 = byt_gpio_reg(vg, group.grp.pins[i], BYT_CONF0_REG);
if (!padcfg0) {
dev_warn(vg->dev,
"Group %s, pin %i not muxed (no padcfg0)\n",
group.name, i);
group.grp.name, i);
continue;
}

16
drivers/pinctrl/intel/pinctrl-cherryview.c
View File

@ -627,7 +627,7 @@ static const char *chv_get_group_name(struct pinctrl_dev *pctldev,
{
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
return pctrl->soc->groups[group].name;
return pctrl->soc->groups[group].grp.name;
}
static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
@ -635,8 +635,8 @@ static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
{
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
*pins = pctrl->soc->groups[group].pins;
*npins = pctrl->soc->groups[group].npins;
*pins = pctrl->soc->groups[group].grp.pins;
*npins = pctrl->soc->groups[group].grp.npins;
return 0;
}
@ -721,16 +721,16 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev,
raw_spin_lock_irqsave(&chv_lock, flags);
/* Check first that the pad is not locked */
for (i = 0; i < grp->npins; i++) {
if (chv_pad_locked(pctrl, grp->pins[i])) {
for (i = 0; i < grp->grp.npins; i++) {
if (chv_pad_locked(pctrl, grp->grp.pins[i])) {
raw_spin_unlock_irqrestore(&chv_lock, flags);
dev_warn(dev, "unable to set mode for locked pin %u\n", grp->pins[i]);
dev_warn(dev, "unable to set mode for locked pin %u\n", grp->grp.pins[i]);
return -EBUSY;
}
}
for (i = 0; i < grp->npins; i++) {
int pin = grp->pins[i];
for (i = 0; i < grp->grp.npins; i++) {
int pin = grp->grp.pins[i];
unsigned int mode;
bool invert_oe;
u32 value;

14
drivers/pinctrl/intel/pinctrl-intel.c
View File

@ -279,7 +279,7 @@ static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
{
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
return pctrl->soc->groups[group].name;
return pctrl->soc->groups[group].grp.name;
}
static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
@ -287,8 +287,8 @@ static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
{
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
*pins = pctrl->soc->groups[group].pins;
*npins = pctrl->soc->groups[group].npins;
*pins = pctrl->soc->groups[group].grp.pins;
*npins = pctrl->soc->groups[group].grp.npins;
return 0;
}
@ -391,19 +391,19 @@ static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev,
* All pins in the groups needs to be accessible and writable
* before we can enable the mux for this group.
*/
for (i = 0; i < grp->npins; i++) {
if (!intel_pad_usable(pctrl, grp->pins[i])) {
for (i = 0; i < grp->grp.npins; i++) {
if (!intel_pad_usable(pctrl, grp->grp.pins[i])) {
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
return -EBUSY;
}
}
/* Now enable the mux setting for each pin in the group */
for (i = 0; i < grp->npins; i++) {
for (i = 0; i < grp->grp.npins; i++) {
void __iomem *padcfg0;
u32 value;
padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0);
padcfg0 = intel_get_padcfg(pctrl, grp->grp.pins[i], PADCFG0);
value = readl(padcfg0);
value &= ~PADCFG0_PMODE_MASK;

25
drivers/pinctrl/intel/pinctrl-intel.h
View File

@ -24,17 +24,12 @@ struct device;
/**
* struct intel_pingroup - Description about group of pins
* @name: Name of the groups
* @pins: All pins in this group
* @npins: Number of pins in this groups
* @mode: Native mode in which the group is muxed out @pins. Used if @modes
* is %NULL.
* @grp: Generic data of the pin group (name and pins)
* @mode: Native mode in which the group is muxed out @pins. Used if @modes is %NULL.
* @modes: If not %NULL this will hold mode for each pin in @pins
*/
struct intel_pingroup {
const char *name;
const unsigned int *pins;
size_t npins;
struct pingroup grp;
unsigned short mode;
const unsigned int *modes;
};
@ -156,15 +151,11 @@ struct intel_community {
* a single integer or an array of integers in which case mode is per
* pin.
*/
#define PIN_GROUP(n, p, m) \
{ \
.name = (n), \
.pins = (p), \
.npins = ARRAY_SIZE((p)), \
.mode = __builtin_choose_expr( \
__builtin_constant_p((m)), (m), 0), \
.modes = __builtin_choose_expr( \
__builtin_constant_p((m)), NULL, (m)), \
#define PIN_GROUP(n, p, m) \
{ \
.grp = PINCTRL_PINGROUP((n), (p), ARRAY_SIZE((p))), \
.mode = __builtin_choose_expr(__builtin_constant_p((m)), (m), 0), \
.modes = __builtin_choose_expr(__builtin_constant_p((m)), NULL, (m)), \
}
#define FUNCTION(n, g) \

10
drivers/pinctrl/intel/pinctrl-lynxpoint.c
View File

@ -282,7 +282,7 @@ static const char *lp_get_group_name(struct pinctrl_dev *pctldev,
{
struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
return lg->soc->groups[selector].name;
return lg->soc->groups[selector].grp.name;
}
static int lp_get_group_pins(struct pinctrl_dev *pctldev,
@ -292,8 +292,8 @@ static int lp_get_group_pins(struct pinctrl_dev *pctldev,
{
struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
*pins = lg->soc->groups[selector].pins;
*num_pins = lg->soc->groups[selector].npins;
*pins = lg->soc->groups[selector].grp.pins;
*num_pins = lg->soc->groups[selector].grp.npins;
return 0;
}
@ -366,8 +366,8 @@ static int lp_pinmux_set_mux(struct pinctrl_dev *pctldev,
raw_spin_lock_irqsave(&lg->lock, flags);
/* Now enable the mux setting for each pin in the group */
for (i = 0; i < grp->npins; i++) {
void __iomem *reg = lp_gpio_reg(&lg->chip, grp->pins[i], LP_CONFIG1);
for (i = 0; i < grp->grp.npins; i++) {
void __iomem *reg = lp_gpio_reg(&lg->chip, grp->grp.pins[i], LP_CONFIG1);
u32 value;
value = ioread32(reg);

14
drivers/pinctrl/intel/pinctrl-merrifield.c
View File

@ -520,7 +520,7 @@ static const char *mrfld_get_group_name(struct pinctrl_dev *pctldev,
{
struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
return mp->groups[group].name;
return mp->groups[group].grp.name;
}
static int mrfld_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
@ -528,8 +528,8 @@ static int mrfld_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
{
struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
*pins = mp->groups[group].pins;
*npins = mp->groups[group].npins;
*pins = mp->groups[group].grp.pins;
*npins = mp->groups[group].grp.npins;
return 0;
}
@ -604,15 +604,15 @@ static int mrfld_pinmux_set_mux(struct pinctrl_dev *pctldev,
* All pins in the groups needs to be accessible and writable
* before we can enable the mux for this group.
*/
for (i = 0; i < grp->npins; i++) {
if (!mrfld_buf_available(mp, grp->pins[i]))
for (i = 0; i < grp->grp.npins; i++) {
if (!mrfld_buf_available(mp, grp->grp.pins[i]))
return -EBUSY;
}
/* Now enable the mux setting for each pin in the group */
raw_spin_lock_irqsave(&mp->lock, flags);
for (i = 0; i < grp->npins; i++)
mrfld_update_bufcfg(mp, grp->pins[i], bits, mask);
for (i = 0; i < grp->grp.npins; i++)
mrfld_update_bufcfg(mp, grp->grp.pins[i], bits, mask);
raw_spin_unlock_irqrestore(&mp->lock, flags);
return 0;

417
drivers/pinctrl/intel/pinctrl-meteorlake.c Normal file
View File

@ -0,0 +1,417 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Intel Meteor Lake PCH pinctrl/GPIO driver
*
* Copyright (C) 2022, Intel Corporation
* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
*/
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-intel.h"
#define MTL_PAD_OWN 0x0b0
#define MTL_PADCFGLOCK 0x110
#define MTL_HOSTSW_OWN 0x140
#define MTL_GPI_IS 0x200
#define MTL_GPI_IE 0x210
#define MTL_GPP(r, s, e, g) \
{ \
.reg_num = (r), \
.base = (s), \
.size = ((e) - (s) + 1), \
.gpio_base = (g), \
}
#define MTL_COMMUNITY(b, s, e, g) \
{ \
.barno = (b), \
.padown_offset = MTL_PAD_OWN, \
.padcfglock_offset = MTL_PADCFGLOCK, \
.hostown_offset = MTL_HOSTSW_OWN, \
.is_offset = MTL_GPI_IS, \
.ie_offset = MTL_GPI_IE, \
.pin_base = (s), \
.npins = ((e) - (s) + 1), \
.gpps = (g), \
.ngpps = ARRAY_SIZE(g), \
}
/* Meteor Lake-P */
static const struct pinctrl_pin_desc mtlp_pins[] = {
/* CPU */
PINCTRL_PIN(0, "PECI"),
PINCTRL_PIN(1, "UFS_RESET_B"),
PINCTRL_PIN(2, "VIDSOUT"),
PINCTRL_PIN(3, "VIDSCK"),
PINCTRL_PIN(4, "VIDALERT_B"),
/* GPP_V */
PINCTRL_PIN(5, "BATLOW_B"),
PINCTRL_PIN(6, "AC_PRESENT"),
PINCTRL_PIN(7, "SOC_WAKE_B"),
PINCTRL_PIN(8, "PWRBTN_B"),
PINCTRL_PIN(9, "SLP_S3_B"),
PINCTRL_PIN(10, "SLP_S4_B"),
PINCTRL_PIN(11, "SLP_A_B"),
PINCTRL_PIN(12, "GPP_V_7"),
PINCTRL_PIN(13, "SUSCLK"),
PINCTRL_PIN(14, "SLP_WLAN_B"),
PINCTRL_PIN(15, "SLP_S5_B"),
PINCTRL_PIN(16, "LANPHYPC"),
PINCTRL_PIN(17, "SLP_LAN_B"),
PINCTRL_PIN(18, "GPP_V_13"),
PINCTRL_PIN(19, "WAKE_B"),
PINCTRL_PIN(20, "GPP_V_15"),
PINCTRL_PIN(21, "GPP_V_16"),
PINCTRL_PIN(22, "GPP_V_17"),
PINCTRL_PIN(23, "GPP_V_18"),
PINCTRL_PIN(24, "CATERR_B"),
PINCTRL_PIN(25, "PROCHOT_B"),
PINCTRL_PIN(26, "THERMTRIP_B"),
PINCTRL_PIN(27, "DSI_DE_TE_2_GENLOCK_REF"),
PINCTRL_PIN(28, "DSI_DE_TE_1_DISP_UTILS"),
/* GPP_C */
PINCTRL_PIN(29, "SMBCLK"),
PINCTRL_PIN(30, "SMBDATA"),
PINCTRL_PIN(31, "SMBALERT_B"),
PINCTRL_PIN(32, "SML0CLK"),
PINCTRL_PIN(33, "SML0DATA"),
PINCTRL_PIN(34, "GPP_C_5"),
PINCTRL_PIN(35, "GPP_C_6"),
PINCTRL_PIN(36, "GPP_C_7"),
PINCTRL_PIN(37, "GPP_C_8"),
PINCTRL_PIN(38, "GPP_C_9"),
PINCTRL_PIN(39, "GPP_C_10"),
PINCTRL_PIN(40, "GPP_C_11"),
PINCTRL_PIN(41, "GPP_C_12"),
PINCTRL_PIN(42, "GPP_C_13"),
PINCTRL_PIN(43, "GPP_C_14"),
PINCTRL_PIN(44, "GPP_C_15"),
PINCTRL_PIN(45, "GPP_C_16"),
PINCTRL_PIN(46, "GPP_C_17"),
PINCTRL_PIN(47, "GPP_C_18"),
PINCTRL_PIN(48, "GPP_C_19"),
PINCTRL_PIN(49, "GPP_C_20"),
PINCTRL_PIN(50, "GPP_C_21"),
PINCTRL_PIN(51, "GPP_C_22"),
PINCTRL_PIN(52, "GPP_C_23"),
/* GPP_A */
PINCTRL_PIN(53, "ESPI_IO_0"),
PINCTRL_PIN(54, "ESPI_IO_1"),
PINCTRL_PIN(55, "ESPI_IO_2"),
PINCTRL_PIN(56, "ESPI_IO_3"),
PINCTRL_PIN(57, "ESPI_CS0_B"),
PINCTRL_PIN(58, "ESPI_CLK"),
PINCTRL_PIN(59, "ESPI_RESET_B"),
PINCTRL_PIN(60, "GPP_A_7"),
PINCTRL_PIN(61, "GPP_A_8"),
PINCTRL_PIN(62, "GPP_A_9"),
PINCTRL_PIN(63, "GPP_A_10"),
PINCTRL_PIN(64, "GPP_A_11"),
PINCTRL_PIN(65, "GPP_A_12"),
PINCTRL_PIN(66, "ESPI_CS1_B"),
PINCTRL_PIN(67, "ESPI_CS2_B"),
PINCTRL_PIN(68, "ESPI_CS3_B"),
PINCTRL_PIN(69, "ESPI_ALERT0_B"),
PINCTRL_PIN(70, "ESPI_ALERT1_B"),
PINCTRL_PIN(71, "ESPI_ALERT2_B"),
PINCTRL_PIN(72, "ESPI_ALERT3_B"),
PINCTRL_PIN(73, "GPP_A_20"),
PINCTRL_PIN(74, "GPP_A_21"),
PINCTRL_PIN(75, "GPP_A_22"),
PINCTRL_PIN(76, "GPP_A_23"),
PINCTRL_PIN(77, "ESPI_CLK_LOOPBK"),
/* GPP_E */
PINCTRL_PIN(78, "GPP_E_0"),
PINCTRL_PIN(79, "GPP_E_1"),
PINCTRL_PIN(80, "GPP_E_2"),
PINCTRL_PIN(81, "GPP_E_3"),
PINCTRL_PIN(82, "GPP_E_4"),
PINCTRL_PIN(83, "GPP_E_5"),
PINCTRL_PIN(84, "GPP_E_6"),
PINCTRL_PIN(85, "GPP_E_7"),
PINCTRL_PIN(86, "GPP_E_8"),
PINCTRL_PIN(87, "GPP_E_9"),
PINCTRL_PIN(88, "GPP_E_10"),
PINCTRL_PIN(89, "GPP_E_11"),
PINCTRL_PIN(90, "GPP_E_12"),
PINCTRL_PIN(91, "GPP_E_13"),
PINCTRL_PIN(92, "GPP_E_14"),
PINCTRL_PIN(93, "SLP_DRAM_B"),
PINCTRL_PIN(94, "GPP_E_16"),
PINCTRL_PIN(95, "GPP_E_17"),
PINCTRL_PIN(96, "GPP_E_18"),
PINCTRL_PIN(97, "GPP_E_19"),
PINCTRL_PIN(98, "GPP_E_20"),
PINCTRL_PIN(99, "GPP_E_21"),
PINCTRL_PIN(100, "DNX_FORCE_RELOAD"),
PINCTRL_PIN(101, "GPP_E_23"),
PINCTRL_PIN(102, "THC0_GSPI0_CLK_LOOPBK"),
/* GPP_H */
PINCTRL_PIN(103, "GPP_H_0"),
PINCTRL_PIN(104, "GPP_H_1"),
PINCTRL_PIN(105, "GPP_H_2"),
PINCTRL_PIN(106, "GPP_H_3"),
PINCTRL_PIN(107, "GPP_H_4"),
PINCTRL_PIN(108, "GPP_H_5"),
PINCTRL_PIN(109, "GPP_H_6"),
PINCTRL_PIN(110, "GPP_H_7"),
PINCTRL_PIN(111, "GPP_H_8"),
PINCTRL_PIN(112, "GPP_H_9"),
PINCTRL_PIN(113, "GPP_H_10"),
PINCTRL_PIN(114, "GPP_H_11"),
PINCTRL_PIN(115, "GPP_H_12"),
PINCTRL_PIN(116, "CPU_C10_GATE_B"),
PINCTRL_PIN(117, "GPP_H_14"),
PINCTRL_PIN(118, "GPP_H_15"),
PINCTRL_PIN(119, "GPP_H_16"),
PINCTRL_PIN(120, "GPP_H_17"),
PINCTRL_PIN(121, "GPP_H_18"),
PINCTRL_PIN(122, "GPP_H_19"),
PINCTRL_PIN(123, "GPP_H_20"),
PINCTRL_PIN(124, "GPP_H_21"),
PINCTRL_PIN(125, "GPP_H_22"),
PINCTRL_PIN(126, "GPP_H_23"),
PINCTRL_PIN(127, "LPI3C1_CLK_LOOPBK"),
PINCTRL_PIN(128, "I3C0_CLK_LOOPBK"),
/* GPP_F */
PINCTRL_PIN(129, "CNV_BRI_DT"),
PINCTRL_PIN(130, "CNV_BRI_RSP"),
PINCTRL_PIN(131, "CNV_RGI_DT"),
PINCTRL_PIN(132, "CNV_RGI_RSP"),
PINCTRL_PIN(133, "CNV_RF_RESET_B"),
PINCTRL_PIN(134, "CRF_CLKREQ"),
PINCTRL_PIN(135, "GPP_F_6"),
PINCTRL_PIN(136, "FUSA_DIAGTEST_EN"),
PINCTRL_PIN(137, "FUSA_DIAGTEST_MODE"),
PINCTRL_PIN(138, "BOOTMPC"),
PINCTRL_PIN(139, "GPP_F_10"),
PINCTRL_PIN(140, "GPP_F_11"),
PINCTRL_PIN(141, "GSXDOUT"),
PINCTRL_PIN(142, "GSXSLOAD"),
PINCTRL_PIN(143, "GSXDIN"),
PINCTRL_PIN(144, "GSXSRESETB"),
PINCTRL_PIN(145, "GSXCLK"),
PINCTRL_PIN(146, "GMII_MDC_0"),
PINCTRL_PIN(147, "GMII_MDIO_0"),
PINCTRL_PIN(148, "GPP_F_19"),
PINCTRL_PIN(149, "GPP_F_20"),
PINCTRL_PIN(150, "GPP_F_21"),
PINCTRL_PIN(151, "GPP_F_22"),
PINCTRL_PIN(152, "GPP_F_23"),
PINCTRL_PIN(153, "THC1_GSPI1_CLK_LOOPBK"),
PINCTRL_PIN(154, "GSPI0A_CLK_LOOPBK"),
/* SPI0 */
PINCTRL_PIN(155, "SPI0_IO_2"),
PINCTRL_PIN(156, "SPI0_IO_3"),
PINCTRL_PIN(157, "SPI0_MOSI_IO_0"),
PINCTRL_PIN(158, "SPI0_MISO_IO_1"),
PINCTRL_PIN(159, "SPI0_TPM_CS_B"),
PINCTRL_PIN(160, "SPI0_FLASH_0_CS_B"),
PINCTRL_PIN(161, "SPI0_FLASH_1_CS_B"),
PINCTRL_PIN(162, "SPI0_CLK"),
PINCTRL_PIN(163, "L_BKLTEN"),
PINCTRL_PIN(164, "L_BKLTCTL"),
PINCTRL_PIN(165, "L_VDDEN"),
PINCTRL_PIN(166, "SYS_PWROK"),
PINCTRL_PIN(167, "SYS_RESET_B"),
PINCTRL_PIN(168, "MLK_RST_B"),
PINCTRL_PIN(169, "SPI0_CLK_LOOPBK"),
/* vGPIO_3 */
PINCTRL_PIN(170, "ESPI_USB_OCB_0"),
PINCTRL_PIN(171, "ESPI_USB_OCB_1"),
PINCTRL_PIN(172, "ESPI_USB_OCB_2"),
PINCTRL_PIN(173, "ESPI_USB_OCB_3"),
PINCTRL_PIN(174, "USB_CPU_OCB_0"),
PINCTRL_PIN(175, "USB_CPU_OCB_1"),
PINCTRL_PIN(176, "USB_CPU_OCB_2"),
PINCTRL_PIN(177, "USB_CPU_OCB_3"),
PINCTRL_PIN(178, "TS0_IN_INT"),
PINCTRL_PIN(179, "TS1_IN_INT"),
PINCTRL_PIN(180, "THC0_WOT_INT"),
PINCTRL_PIN(181, "THC1_WOT_INT"),
PINCTRL_PIN(182, "THC0_WHC_INT"),
PINCTRL_PIN(183, "THC1_WHC_INT"),
/* GPP_S */
PINCTRL_PIN(184, "GPP_S_0"),
PINCTRL_PIN(185, "GPP_S_1"),
PINCTRL_PIN(186, "GPP_S_2"),
PINCTRL_PIN(187, "GPP_S_3"),
PINCTRL_PIN(188, "GPP_S_4"),
PINCTRL_PIN(189, "GPP_S_5"),
PINCTRL_PIN(190, "GPP_S_6"),
PINCTRL_PIN(191, "GPP_S_7"),
/* JTAG */
PINCTRL_PIN(192, "JTAG_MBPB0"),
PINCTRL_PIN(193, "JTAG_MBPB1"),
PINCTRL_PIN(194, "JTAG_MBPB2"),
PINCTRL_PIN(195, "JTAG_MBPB3"),
PINCTRL_PIN(196, "JTAG_TDO"),
PINCTRL_PIN(197, "PRDY_B"),
PINCTRL_PIN(198, "PREQ_B"),
PINCTRL_PIN(199, "JTAG_TDI"),
PINCTRL_PIN(200, "JTAG_TMS"),
PINCTRL_PIN(201, "JTAG_TCK"),
PINCTRL_PIN(202, "DBG_PMODE"),
PINCTRL_PIN(203, "JTAG_TRST_B"),
/* GPP_B */
PINCTRL_PIN(204, "ADM_VID_0"),
PINCTRL_PIN(205, "ADM_VID_1"),
PINCTRL_PIN(206, "GPP_B_2"),
PINCTRL_PIN(207, "GPP_B_3"),
PINCTRL_PIN(208, "GPP_B_4"),
PINCTRL_PIN(209, "GPP_B_5"),
PINCTRL_PIN(210, "GPP_B_6"),
PINCTRL_PIN(211, "GPP_B_7"),
PINCTRL_PIN(212, "GPP_B_8"),
PINCTRL_PIN(213, "GPP_B_9"),
PINCTRL_PIN(214, "GPP_B_10"),
PINCTRL_PIN(215, "GPP_B_11"),
PINCTRL_PIN(216, "SLP_S0_B"),
PINCTRL_PIN(217, "PLTRST_B"),
PINCTRL_PIN(218, "GPP_B_14"),
PINCTRL_PIN(219, "GPP_B_15"),
PINCTRL_PIN(220, "GPP_B_16"),
PINCTRL_PIN(221, "GPP_B_17"),
PINCTRL_PIN(222, "GPP_B_18"),
PINCTRL_PIN(223, "GPP_B_19"),
PINCTRL_PIN(224, "GPP_B_20"),
PINCTRL_PIN(225, "GPP_B_21"),
PINCTRL_PIN(226, "GPP_B_22"),
PINCTRL_PIN(227, "GPP_B_23"),
PINCTRL_PIN(228, "ISH_I3C0_CLK_LOOPBK"),
/* GPP_D */
PINCTRL_PIN(229, "GPP_D_0"),
PINCTRL_PIN(230, "GPP_D_1"),
PINCTRL_PIN(231, "GPP_D_2"),
PINCTRL_PIN(232, "GPP_D_3"),
PINCTRL_PIN(233, "GPP_D_4"),
PINCTRL_PIN(234, "GPP_D_5"),
PINCTRL_PIN(235, "GPP_D_6"),
PINCTRL_PIN(236, "GPP_D_7"),
PINCTRL_PIN(237, "GPP_D_8"),
PINCTRL_PIN(238, "GPP_D_9"),
PINCTRL_PIN(239, "HDA_BCLK"),
PINCTRL_PIN(240, "HDA_SYNC"),
PINCTRL_PIN(241, "HDA_SDO"),
PINCTRL_PIN(242, "HDA_SDI_0"),
PINCTRL_PIN(243, "GPP_D_14"),
PINCTRL_PIN(244, "GPP_D_15"),
PINCTRL_PIN(245, "GPP_D_16"),
PINCTRL_PIN(246, "HDA_RST_B"),
PINCTRL_PIN(247, "GPP_D_18"),
PINCTRL_PIN(248, "GPP_D_19"),
PINCTRL_PIN(249, "GPP_D_20"),
PINCTRL_PIN(250, "UFS_REFCLK"),
PINCTRL_PIN(251, "BPKI3C_SDA"),
PINCTRL_PIN(252, "BPKI3C_SCL"),
PINCTRL_PIN(253, "BOOTHALT_B"),
/* vGPIO */
PINCTRL_PIN(254, "CNV_BTEN"),
PINCTRL_PIN(255, "CNV_BT_HOST_WAKEB"),
PINCTRL_PIN(256, "CNV_BT_IF_SELECT"),
PINCTRL_PIN(257, "vCNV_BT_UART_TXD"),
PINCTRL_PIN(258, "vCNV_BT_UART_RXD"),
PINCTRL_PIN(259, "vCNV_BT_UART_CTS_B"),
PINCTRL_PIN(260, "vCNV_BT_UART_RTS_B"),
PINCTRL_PIN(261, "vCNV_MFUART1_TXD"),
PINCTRL_PIN(262, "vCNV_MFUART1_RXD"),
PINCTRL_PIN(263, "vCNV_MFUART1_CTS_B"),
PINCTRL_PIN(264, "vCNV_MFUART1_RTS_B"),
PINCTRL_PIN(265, "vUART0_TXD"),
PINCTRL_PIN(266, "vUART0_RXD"),
PINCTRL_PIN(267, "vUART0_CTS_B"),
PINCTRL_PIN(268, "vUART0_RTS_B"),
PINCTRL_PIN(269, "vISH_UART0_TXD"),
PINCTRL_PIN(270, "vISH_UART0_RXD"),
PINCTRL_PIN(271, "vISH_UART0_CTS_B"),
PINCTRL_PIN(272, "vISH_UART0_RTS_B"),
PINCTRL_PIN(273, "vCNV_BT_I2S_BCLK"),
PINCTRL_PIN(274, "vCNV_BT_I2S_WS_SYNC"),
PINCTRL_PIN(275, "vCNV_BT_I2S_SDO"),
PINCTRL_PIN(276, "vCNV_BT_I2S_SDI"),
PINCTRL_PIN(277, "vI2S2_SCLK"),
PINCTRL_PIN(278, "vI2S2_SFRM"),
PINCTRL_PIN(279, "vI2S2_TXD"),
PINCTRL_PIN(280, "vI2S2_RXD"),
PINCTRL_PIN(281, "vCNV_BT_I2S_BCLK_2"),
PINCTRL_PIN(282, "vCNV_BT_I2S_WS_SYNC_2"),
PINCTRL_PIN(283, "vCNV_BT_I2S_SDO_2"),
PINCTRL_PIN(284, "vCNV_BT_I2S_SDI_2"),
PINCTRL_PIN(285, "vI2S2_SCLK_2"),
PINCTRL_PIN(286, "vI2S2_SFRM_2"),
PINCTRL_PIN(287, "vI2S2_TXD_2"),
PINCTRL_PIN(288, "vI2S2_RXD_2"),
};
static const struct intel_padgroup mtlp_community0_gpps[] = {
MTL_GPP(0, 0, 4, 0), /* CPU */
MTL_GPP(1, 5, 28, 32), /* GPP_V */
MTL_GPP(2, 29, 52, 64), /* GPP_C */
};
static const struct intel_padgroup mtlp_community1_gpps[] = {
MTL_GPP(0, 53, 77, 96), /* GPP_A */
MTL_GPP(1, 78, 102, 128), /* GPP_E */
};
static const struct intel_padgroup mtlp_community3_gpps[] = {
MTL_GPP(0, 103, 128, 160), /* GPP_H */
MTL_GPP(1, 129, 154, 192), /* GPP_F */
MTL_GPP(2, 155, 169, 224), /* SPI0 */
MTL_GPP(3, 170, 183, 256), /* vGPIO_3 */
};
static const struct intel_padgroup mtlp_community4_gpps[] = {
MTL_GPP(0, 184, 191, 288), /* GPP_S */
MTL_GPP(1, 192, 203, 320), /* JTAG */
};
static const struct intel_padgroup mtlp_community5_gpps[] = {
MTL_GPP(0, 204, 228, 352), /* GPP_B */
MTL_GPP(1, 229, 253, 384), /* GPP_D */
MTL_GPP(2, 254, 285, 416), /* vGPIO_0 */
MTL_GPP(3, 286, 288, 448), /* vGPIO_1 */
};
static const struct intel_community mtlp_communities[] = {
MTL_COMMUNITY(0, 0, 52, mtlp_community0_gpps),
MTL_COMMUNITY(1, 53, 102, mtlp_community1_gpps),
MTL_COMMUNITY(2, 103, 183, mtlp_community3_gpps),
MTL_COMMUNITY(3, 184, 203, mtlp_community4_gpps),
MTL_COMMUNITY(4, 204, 288, mtlp_community5_gpps),
};
static const struct intel_pinctrl_soc_data mtlp_soc_data = {
.pins = mtlp_pins,
.npins = ARRAY_SIZE(mtlp_pins),
.communities = mtlp_communities,
.ncommunities = ARRAY_SIZE(mtlp_communities),
};
static const struct acpi_device_id mtl_pinctrl_acpi_match[] = {
{ "INTC1083", (kernel_ulong_t)&mtlp_soc_data },
{ }
};
MODULE_DEVICE_TABLE(acpi, mtl_pinctrl_acpi_match);
static INTEL_PINCTRL_PM_OPS(mtl_pinctrl_pm_ops);
static struct platform_driver mtl_pinctrl_driver = {
.probe = intel_pinctrl_probe_by_hid,
.driver = {
.name = "meteorlake-pinctrl",
.acpi_match_table = mtl_pinctrl_acpi_match,
.pm = &mtl_pinctrl_pm_ops,
},
};
module_platform_driver(mtl_pinctrl_driver);
MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
MODULE_DESCRIPTION("Intel Meteor Lake PCH pinctrl/GPIO driver");
MODULE_LICENSE("GPL v2");

296
drivers/pinctrl/mediatek/pinctrl-mt8192.c
View File

@ -1107,24 +1107,10 @@ static const struct mtk_pin_field_calc mt8192_pin_pupd_range[] = {
PIN_FIELD_BASE(54, 54, 1, 0x0060, 0x10, 2, 1),
PIN_FIELD_BASE(55, 55, 1, 0x0060, 0x10, 4, 1),
PIN_FIELD_BASE(56, 56, 1, 0x0060, 0x10, 3, 1),
PIN_FIELD_BASE(118, 118, 4, 0x00e0, 0x10, 31, 1),
PIN_FIELD_BASE(119, 119, 4, 0x00e0, 0x10, 31, 1),
PIN_FIELD_BASE(120, 120, 4, 0x00e0, 0x10, 31, 1),
PIN_FIELD_BASE(121, 121, 4, 0x00e0, 0x10, 31, 1),
PIN_FIELD_BASE(122, 122, 4, 0x00e0, 0x10, 31, 1),
PIN_FIELD_BASE(123, 123, 4, 0x00e0, 0x10, 31, 1),
PIN_FIELD_BASE(124, 124, 4, 0x00e0, 0x10, 31, 1),
PIN_FIELD_BASE(125, 125, 4, 0x00e0, 0x10, 31, 1),
PIN_FIELD_BASE(139, 139, 4, 0x00e0, 0x10, 31, 1),
PIN_FIELD_BASE(140, 140, 4, 0x00e0, 0x10, 31, 1),
PIN_FIELD_BASE(141, 141, 4, 0x00e0, 0x10, 31, 1),
PIN_FIELD_BASE(142, 142, 4, 0x00e0, 0x10, 31, 1),
PIN_FIELD_BASE(152, 152, 7, 0x0090, 0x10, 3, 1),
PIN_FIELD_BASE(153, 153, 7, 0x0090, 0x10, 2, 1),
PIN_FIELD_BASE(154, 154, 7, 0x0090, 0x10, 0, 1),
PIN_FIELD_BASE(155, 155, 7, 0x0090, 0x10, 1, 1),
PIN_FIELD_BASE(160, 160, 7, 0x00f0, 0x10, 31, 1),
PIN_FIELD_BASE(161, 161, 7, 0x00f0, 0x10, 31, 1),
PIN_FIELD_BASE(183, 183, 9, 0x0030, 0x10, 1, 1),
PIN_FIELD_BASE(184, 184, 9, 0x0030, 0x10, 2, 1),
PIN_FIELD_BASE(185, 185, 9, 0x0030, 0x10, 4, 1),
@ -1137,12 +1123,6 @@ static const struct mtk_pin_field_calc mt8192_pin_pupd_range[] = {
PIN_FIELD_BASE(192, 192, 9, 0x0030, 0x10, 0, 1),
PIN_FIELD_BASE(193, 193, 9, 0x0030, 0x10, 5, 1),
PIN_FIELD_BASE(194, 194, 9, 0x0030, 0x10, 11, 1),
PIN_FIELD_BASE(200, 200, 8, 0x0070, 0x10, 31, 1),
PIN_FIELD_BASE(201, 201, 8, 0x0070, 0x10, 31, 1),
PIN_FIELD_BASE(202, 202, 5, 0x0070, 0x10, 31, 1),
PIN_FIELD_BASE(203, 203, 5, 0x0070, 0x10, 31, 1),
PIN_FIELD_BASE(204, 204, 8, 0x0070, 0x10, 31, 1),
PIN_FIELD_BASE(205, 205, 8, 0x0070, 0x10, 31, 1),
};
static const struct mtk_pin_field_calc mt8192_pin_r0_range[] = {
@ -1164,24 +1144,10 @@ static const struct mtk_pin_field_calc mt8192_pin_r0_range[] = {
PIN_FIELD_BASE(54, 54, 1, 0x0080, 0x10, 2, 1),
PIN_FIELD_BASE(55, 55, 1, 0x0080, 0x10, 4, 1),
PIN_FIELD_BASE(56, 56, 1, 0x0080, 0x10, 3, 1),
PIN_FIELD_BASE(118, 118, 4, 0x00e0, 0x10, 0, 1),
PIN_FIELD_BASE(119, 119, 4, 0x00e0, 0x10, 12, 1),
PIN_FIELD_BASE(120, 120, 4, 0x00e0, 0x10, 10, 1),
PIN_FIELD_BASE(121, 121, 4, 0x00e0, 0x10, 22, 1),
PIN_FIELD_BASE(122, 122, 4, 0x00e0, 0x10, 8, 1),
PIN_FIELD_BASE(123, 123, 4, 0x00e0, 0x10, 20, 1),
PIN_FIELD_BASE(124, 124, 4, 0x00e0, 0x10, 6, 1),
PIN_FIELD_BASE(125, 125, 4, 0x00e0, 0x10, 18, 1),
PIN_FIELD_BASE(139, 139, 4, 0x00e0, 0x10, 4, 1),
PIN_FIELD_BASE(140, 140, 4, 0x00e0, 0x10, 16, 1),
PIN_FIELD_BASE(141, 141, 4, 0x00e0, 0x10, 2, 1),
PIN_FIELD_BASE(142, 142, 4, 0x00e0, 0x10, 14, 1),
PIN_FIELD_BASE(152, 152, 7, 0x00c0, 0x10, 3, 1),
PIN_FIELD_BASE(153, 153, 7, 0x00c0, 0x10, 2, 1),
PIN_FIELD_BASE(154, 154, 7, 0x00c0, 0x10, 0, 1),
PIN_FIELD_BASE(155, 155, 7, 0x00c0, 0x10, 1, 1),
PIN_FIELD_BASE(160, 160, 7, 0x00f0, 0x10, 0, 1),
PIN_FIELD_BASE(161, 161, 7, 0x00f0, 0x10, 2, 1),
PIN_FIELD_BASE(183, 183, 9, 0x0040, 0x10, 1, 1),
PIN_FIELD_BASE(184, 184, 9, 0x0040, 0x10, 2, 1),
PIN_FIELD_BASE(185, 185, 9, 0x0040, 0x10, 4, 1),
@ -1194,12 +1160,6 @@ static const struct mtk_pin_field_calc mt8192_pin_r0_range[] = {
PIN_FIELD_BASE(192, 192, 9, 0x0040, 0x10, 0, 1),
PIN_FIELD_BASE(193, 193, 9, 0x0040, 0x10, 5, 1),
PIN_FIELD_BASE(194, 194, 9, 0x0040, 0x10, 11, 1),
PIN_FIELD_BASE(200, 200, 8, 0x0070, 0x10, 2, 1),
PIN_FIELD_BASE(201, 201, 8, 0x0070, 0x10, 6, 1),
PIN_FIELD_BASE(202, 202, 5, 0x0070, 0x10, 0, 1),
PIN_FIELD_BASE(203, 203, 5, 0x0070, 0x10, 2, 1),
PIN_FIELD_BASE(204, 204, 8, 0x0070, 0x10, 0, 1),
PIN_FIELD_BASE(205, 205, 8, 0x0070, 0x10, 4, 1),
};
static const struct mtk_pin_field_calc mt8192_pin_r1_range[] = {
@ -1221,24 +1181,10 @@ static const struct mtk_pin_field_calc mt8192_pin_r1_range[] = {
PIN_FIELD_BASE(54, 54, 1, 0x0090, 0x10, 2, 1),
PIN_FIELD_BASE(55, 55, 1, 0x0090, 0x10, 4, 1),
PIN_FIELD_BASE(56, 56, 1, 0x0090, 0x10, 3, 1),
PIN_FIELD_BASE(118, 118, 4, 0x00e0, 0x10, 1, 1),
PIN_FIELD_BASE(119, 119, 4, 0x00e0, 0x10, 13, 1),
PIN_FIELD_BASE(120, 120, 4, 0x00e0, 0x10, 11, 1),
PIN_FIELD_BASE(121, 121, 4, 0x00e0, 0x10, 23, 1),
PIN_FIELD_BASE(122, 122, 4, 0x00e0, 0x10, 9, 1),
PIN_FIELD_BASE(123, 123, 4, 0x00e0, 0x10, 21, 1),
PIN_FIELD_BASE(124, 124, 4, 0x00e0, 0x10, 7, 1),
PIN_FIELD_BASE(125, 125, 4, 0x00e0, 0x10, 19, 1),
PIN_FIELD_BASE(139, 139, 4, 0x00e0, 0x10, 5, 1),
PIN_FIELD_BASE(140, 140, 4, 0x00e0, 0x10, 17, 1),
PIN_FIELD_BASE(141, 141, 4, 0x00e0, 0x10, 3, 1),
PIN_FIELD_BASE(142, 142, 4, 0x00e0, 0x10, 15, 1),
PIN_FIELD_BASE(152, 152, 7, 0x00d0, 0x10, 3, 1),
PIN_FIELD_BASE(153, 153, 7, 0x00d0, 0x10, 2, 1),
PIN_FIELD_BASE(154, 154, 7, 0x00d0, 0x10, 0, 1),
PIN_FIELD_BASE(155, 155, 7, 0x00d0, 0x10, 1, 1),
PIN_FIELD_BASE(160, 160, 7, 0x00f0, 0x10, 1, 1),
PIN_FIELD_BASE(161, 161, 7, 0x00f0, 0x10, 3, 1),
PIN_FIELD_BASE(183, 183, 9, 0x0050, 0x10, 1, 1),
PIN_FIELD_BASE(184, 184, 9, 0x0050, 0x10, 2, 1),
PIN_FIELD_BASE(185, 185, 9, 0x0050, 0x10, 4, 1),
@ -1251,84 +1197,170 @@ static const struct mtk_pin_field_calc mt8192_pin_r1_range[] = {
PIN_FIELD_BASE(192, 192, 9, 0x0050, 0x10, 0, 1),
PIN_FIELD_BASE(193, 193, 9, 0x0050, 0x10, 5, 1),
PIN_FIELD_BASE(194, 194, 9, 0x0050, 0x10, 11, 1),
PIN_FIELD_BASE(200, 200, 8, 0x0070, 0x10, 3, 1),
PIN_FIELD_BASE(201, 201, 8, 0x0070, 0x10, 7, 1),
PIN_FIELD_BASE(202, 202, 5, 0x0070, 0x10, 1, 1),
PIN_FIELD_BASE(203, 203, 5, 0x0070, 0x10, 3, 1),
PIN_FIELD_BASE(204, 204, 8, 0x0070, 0x10, 1, 1),
PIN_FIELD_BASE(205, 205, 8, 0x0070, 0x10, 5, 1),
};
static const struct mtk_pin_field_calc mt8192_pin_e1e0en_range[] = {
PIN_FIELD_BASE(118, 118, 4, 0x0040, 0x10, 0, 1),
PIN_FIELD_BASE(119, 119, 4, 0x0040, 0x10, 18, 1),
PIN_FIELD_BASE(120, 120, 4, 0x0040, 0x10, 15, 1),
PIN_FIELD_BASE(121, 121, 4, 0x0050, 0x10, 3, 1),
PIN_FIELD_BASE(122, 122, 4, 0x0040, 0x10, 12, 1),
PIN_FIELD_BASE(123, 123, 4, 0x0050, 0x10, 0, 1),
PIN_FIELD_BASE(124, 124, 4, 0x0040, 0x10, 9, 1),
PIN_FIELD_BASE(125, 125, 4, 0x0040, 0x10, 27, 1),
PIN_FIELD_BASE(139, 139, 4, 0x0040, 0x10, 6, 1),
PIN_FIELD_BASE(140, 140, 4, 0x0040, 0x10, 24, 1),
PIN_FIELD_BASE(141, 141, 4, 0x0040, 0x10, 3, 1),
PIN_FIELD_BASE(142, 142, 4, 0x0040, 0x10, 21, 1),
PIN_FIELD_BASE(160, 160, 7, 0x0030, 0x10, 0, 1),
PIN_FIELD_BASE(161, 161, 7, 0x0030, 0x10, 3, 1),
PIN_FIELD_BASE(200, 200, 8, 0x0010, 0x10, 3, 1),
PIN_FIELD_BASE(201, 201, 8, 0x0010, 0x10, 9, 1),
PIN_FIELD_BASE(202, 202, 5, 0x0020, 0x10, 0, 1),
PIN_FIELD_BASE(203, 203, 5, 0x0020, 0x10, 3, 1),
PIN_FIELD_BASE(204, 204, 8, 0x0010, 0x10, 0, 1),
PIN_FIELD_BASE(205, 205, 8, 0x0010, 0x10, 6, 1),
static const struct mtk_pin_field_calc mt8192_pin_drv_adv_range[] = {
PIN_FIELD_BASE(89, 89, 2, 0x0040, 0x10, 0, 5),
PIN_FIELD_BASE(90, 90, 2, 0x0040, 0x10, 5, 5),
PIN_FIELD_BASE(118, 118, 4, 0x0040, 0x10, 0, 3),
PIN_FIELD_BASE(119, 119, 4, 0x0040, 0x10, 18, 3),
PIN_FIELD_BASE(120, 120, 4, 0x0040, 0x10, 15, 3),
PIN_FIELD_BASE(121, 121, 4, 0x0050, 0x10, 3, 3),
PIN_FIELD_BASE(122, 122, 4, 0x0040, 0x10, 12, 3),
PIN_FIELD_BASE(123, 123, 4, 0x0050, 0x10, 0, 3),
PIN_FIELD_BASE(124, 124, 4, 0x0040, 0x10, 9, 3),
PIN_FIELD_BASE(125, 125, 4, 0x0040, 0x10, 27, 3),
PIN_FIELD_BASE(139, 139, 4, 0x0040, 0x10, 6, 3),
PIN_FIELD_BASE(140, 140, 4, 0x0040, 0x10, 24, 3),
PIN_FIELD_BASE(141, 141, 4, 0x0040, 0x10, 3, 3),
PIN_FIELD_BASE(142, 142, 4, 0x0040, 0x10, 21, 3),
PIN_FIELD_BASE(160, 160, 7, 0x0030, 0x10, 0, 3),
PIN_FIELD_BASE(161, 161, 7, 0x0030, 0x10, 3, 3),
PIN_FIELD_BASE(200, 200, 8, 0x0010, 0x10, 3, 3),
PIN_FIELD_BASE(201, 201, 8, 0x0010, 0x10, 9, 3),
PIN_FIELD_BASE(202, 202, 5, 0x0020, 0x10, 0, 3),
PIN_FIELD_BASE(203, 203, 5, 0x0020, 0x10, 3, 3),
PIN_FIELD_BASE(204, 204, 8, 0x0010, 0x10, 0, 3),
PIN_FIELD_BASE(205, 205, 8, 0x0010, 0x10, 6, 3),
};
static const struct mtk_pin_field_calc mt8192_pin_e0_range[] = {
PIN_FIELD_BASE(118, 118, 4, 0x0040, 0x10, 1, 1),
PIN_FIELD_BASE(119, 119, 4, 0x0040, 0x10, 19, 1),
PIN_FIELD_BASE(120, 120, 4, 0x0040, 0x10, 16, 1),
PIN_FIELD_BASE(121, 121, 4, 0x0050, 0x10, 4, 1),
PIN_FIELD_BASE(122, 122, 4, 0x0040, 0x10, 13, 1),
PIN_FIELD_BASE(123, 123, 4, 0x0050, 0x10, 1, 1),
PIN_FIELD_BASE(124, 124, 4, 0x0040, 0x10, 10, 1),
PIN_FIELD_BASE(125, 125, 4, 0x0040, 0x10, 28, 1),
PIN_FIELD_BASE(139, 139, 4, 0x0040, 0x10, 7, 1),
PIN_FIELD_BASE(140, 140, 4, 0x0040, 0x10, 25, 1),
PIN_FIELD_BASE(141, 141, 4, 0x0040, 0x10, 4, 1),
PIN_FIELD_BASE(142, 142, 4, 0x0040, 0x10, 22, 1),
PIN_FIELD_BASE(160, 160, 7, 0x0030, 0x10, 1, 1),
PIN_FIELD_BASE(161, 161, 7, 0x0030, 0x10, 4, 1),
PIN_FIELD_BASE(200, 200, 8, 0x0010, 0x10, 4, 1),
PIN_FIELD_BASE(201, 201, 8, 0x0010, 0x10, 10, 1),
PIN_FIELD_BASE(202, 202, 5, 0x0020, 0x10, 1, 1),
PIN_FIELD_BASE(203, 203, 5, 0x0020, 0x10, 4, 1),
PIN_FIELD_BASE(204, 204, 8, 0x0010, 0x10, 1, 1),
PIN_FIELD_BASE(205, 205, 8, 0x0010, 0x10, 7, 1),
static const struct mtk_pin_field_calc mt8192_pin_rsel_range[] = {
PIN_FIELD_BASE(118, 118, 4, 0x00e0, 0x10, 0, 2),
PIN_FIELD_BASE(119, 119, 4, 0x00e0, 0x10, 12, 2),
PIN_FIELD_BASE(120, 120, 4, 0x00e0, 0x10, 10, 2),
PIN_FIELD_BASE(121, 121, 4, 0x00e0, 0x10, 22, 2),
PIN_FIELD_BASE(122, 122, 4, 0x00e0, 0x10, 8, 2),
PIN_FIELD_BASE(123, 123, 4, 0x00e0, 0x10, 20, 2),
PIN_FIELD_BASE(124, 124, 4, 0x00e0, 0x10, 6, 2),
PIN_FIELD_BASE(125, 125, 4, 0x00e0, 0x10, 18, 2),
PIN_FIELD_BASE(139, 139, 4, 0x00e0, 0x10, 4, 2),
PIN_FIELD_BASE(140, 140, 4, 0x00e0, 0x10, 16, 2),
PIN_FIELD_BASE(141, 141, 4, 0x00e0, 0x10, 2, 2),
PIN_FIELD_BASE(142, 142, 4, 0x00e0, 0x10, 14, 2),
PIN_FIELD_BASE(160, 160, 7, 0x00f0, 0x10, 0, 2),
PIN_FIELD_BASE(161, 161, 7, 0x00f0, 0x10, 2, 2),
PIN_FIELD_BASE(200, 200, 8, 0x0070, 0x10, 2, 2),
PIN_FIELD_BASE(201, 201, 8, 0x0070, 0x10, 6, 2),
PIN_FIELD_BASE(202, 202, 5, 0x0070, 0x10, 0, 2),
PIN_FIELD_BASE(203, 203, 5, 0x0070, 0x10, 2, 2),
PIN_FIELD_BASE(204, 204, 8, 0x0070, 0x10, 0, 2),
PIN_FIELD_BASE(205, 205, 8, 0x0070, 0x10, 4, 2),
};
static const struct mtk_pin_field_calc mt8192_pin_e1_range[] = {
PIN_FIELD_BASE(118, 118, 4, 0x0040, 0x10, 2, 1),
PIN_FIELD_BASE(119, 119, 4, 0x0040, 0x10, 20, 1),
PIN_FIELD_BASE(120, 120, 4, 0x0040, 0x10, 17, 1),
PIN_FIELD_BASE(121, 121, 4, 0x0050, 0x10, 5, 1),
PIN_FIELD_BASE(122, 122, 4, 0x0040, 0x10, 14, 1),
PIN_FIELD_BASE(123, 123, 4, 0x0050, 0x10, 2, 1),
PIN_FIELD_BASE(124, 124, 4, 0x0040, 0x10, 11, 1),
PIN_FIELD_BASE(125, 125, 4, 0x0040, 0x10, 29, 1),
PIN_FIELD_BASE(139, 139, 4, 0x0040, 0x10, 8, 1),
PIN_FIELD_BASE(140, 140, 4, 0x0040, 0x10, 26, 1),
PIN_FIELD_BASE(141, 141, 4, 0x0040, 0x10, 5, 1),
PIN_FIELD_BASE(142, 142, 4, 0x0040, 0x10, 23, 1),
PIN_FIELD_BASE(160, 160, 7, 0x0030, 0x10, 2, 1),
PIN_FIELD_BASE(161, 161, 7, 0x0030, 0x10, 5, 1),
PIN_FIELD_BASE(200, 200, 8, 0x0010, 0x10, 5, 1),
PIN_FIELD_BASE(201, 201, 8, 0x0010, 0x10, 11, 1),
PIN_FIELD_BASE(202, 202, 5, 0x0020, 0x10, 2, 1),
PIN_FIELD_BASE(203, 203, 5, 0x0020, 0x10, 5, 1),
PIN_FIELD_BASE(204, 204, 8, 0x0010, 0x10, 2, 1),
PIN_FIELD_BASE(205, 205, 8, 0x0010, 0x10, 8, 1),
static const unsigned int mt8192_pull_type[] = {
MTK_PULL_PU_PD_TYPE,/*0*/ MTK_PULL_PU_PD_TYPE,/*1*/
MTK_PULL_PU_PD_TYPE,/*2*/ MTK_PULL_PU_PD_TYPE,/*3*/
MTK_PULL_PU_PD_TYPE,/*4*/ MTK_PULL_PU_PD_TYPE,/*5*/
MTK_PULL_PU_PD_TYPE,/*6*/ MTK_PULL_PU_PD_TYPE,/*7*/
MTK_PULL_PU_PD_TYPE,/*8*/ MTK_PULL_PU_PD_TYPE,/*9*/
MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/
MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/
MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/
MTK_PULL_PU_PD_TYPE,/*16*/ MTK_PULL_PU_PD_TYPE,/*17*/
MTK_PULL_PU_PD_TYPE,/*18*/ MTK_PULL_PU_PD_TYPE,/*19*/
MTK_PULL_PU_PD_TYPE,/*20*/ MTK_PULL_PU_PD_TYPE,/*21*/
MTK_PULL_PU_PD_TYPE,/*22*/ MTK_PULL_PU_PD_TYPE,/*23*/
MTK_PULL_PU_PD_TYPE,/*24*/ MTK_PULL_PU_PD_TYPE,/*25*/
MTK_PULL_PU_PD_TYPE,/*26*/ MTK_PULL_PU_PD_TYPE,/*27*/
MTK_PULL_PU_PD_TYPE,/*28*/ MTK_PULL_PU_PD_TYPE,/*29*/
MTK_PULL_PU_PD_TYPE,/*30*/ MTK_PULL_PU_PD_TYPE,/*31*/
MTK_PULL_PU_PD_TYPE,/*32*/ MTK_PULL_PU_PD_TYPE,/*33*/
MTK_PULL_PU_PD_TYPE,/*34*/ MTK_PULL_PU_PD_TYPE,/*35*/
MTK_PULL_PU_PD_TYPE,/*36*/ MTK_PULL_PU_PD_TYPE,/*37*/
MTK_PULL_PU_PD_TYPE,/*38*/ MTK_PULL_PU_PD_TYPE,/*39*/
MTK_PULL_PU_PD_TYPE,/*40*/ MTK_PULL_PU_PD_TYPE,/*41*/
MTK_PULL_PU_PD_TYPE,/*42*/ MTK_PULL_PU_PD_TYPE,/*43*/
MTK_PULL_PU_PD_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/
MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/
MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/
MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/
MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/
MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/
MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PU_PD_TYPE,/*57*/
MTK_PULL_PU_PD_TYPE,/*58*/ MTK_PULL_PU_PD_TYPE,/*59*/
MTK_PULL_PU_PD_TYPE,/*60*/ MTK_PULL_PU_PD_TYPE,/*61*/
MTK_PULL_PU_PD_TYPE,/*62*/ MTK_PULL_PU_PD_TYPE,/*63*/
MTK_PULL_PU_PD_TYPE,/*64*/ MTK_PULL_PU_PD_TYPE,/*65*/
MTK_PULL_PU_PD_TYPE,/*66*/ MTK_PULL_PU_PD_TYPE,/*67*/
MTK_PULL_PU_PD_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/
MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/
MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/
MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/
MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/
MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/
MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/
MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/
MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/
MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/
MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/
MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/
MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/
MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/
MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/
MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/
MTK_PULL_PU_PD_TYPE,/*100*/ MTK_PULL_PU_PD_TYPE,/*101*/
MTK_PULL_PU_PD_TYPE,/*102*/ MTK_PULL_PU_PD_TYPE,/*103*/
MTK_PULL_PU_PD_TYPE,/*104*/ MTK_PULL_PU_PD_TYPE,/*105*/
MTK_PULL_PU_PD_TYPE,/*106*/ MTK_PULL_PU_PD_TYPE,/*107*/
MTK_PULL_PU_PD_TYPE,/*108*/ MTK_PULL_PU_PD_TYPE,/*109*/
MTK_PULL_PU_PD_TYPE,/*110*/ MTK_PULL_PU_PD_TYPE,/*111*/
MTK_PULL_PU_PD_TYPE,/*112*/ MTK_PULL_PU_PD_TYPE,/*113*/
MTK_PULL_PU_PD_TYPE,/*114*/ MTK_PULL_PU_PD_TYPE,/*115*/
MTK_PULL_PU_PD_TYPE,/*116*/ MTK_PULL_PU_PD_TYPE,/*117*/
MTK_PULL_PU_PD_RSEL_TYPE,/*118*/ MTK_PULL_PU_PD_RSEL_TYPE,/*119*/
MTK_PULL_PU_PD_RSEL_TYPE,/*120*/ MTK_PULL_PU_PD_RSEL_TYPE,/*121*/
MTK_PULL_PU_PD_RSEL_TYPE,/*122*/ MTK_PULL_PU_PD_RSEL_TYPE,/*123*/
MTK_PULL_PU_PD_RSEL_TYPE,/*124*/ MTK_PULL_PU_PD_RSEL_TYPE,/*125*/
MTK_PULL_PU_PD_TYPE,/*126*/ MTK_PULL_PU_PD_TYPE,/*127*/
MTK_PULL_PU_PD_TYPE,/*128*/ MTK_PULL_PU_PD_TYPE,/*129*/
MTK_PULL_PU_PD_TYPE,/*130*/ MTK_PULL_PU_PD_TYPE,/*131*/
MTK_PULL_PU_PD_TYPE,/*132*/ MTK_PULL_PU_PD_TYPE,/*133*/
MTK_PULL_PU_PD_TYPE,/*134*/ MTK_PULL_PU_PD_TYPE,/*135*/
MTK_PULL_PU_PD_TYPE,/*136*/ MTK_PULL_PU_PD_TYPE,/*137*/
MTK_PULL_PU_PD_TYPE,/*138*/ MTK_PULL_PU_PD_RSEL_TYPE,/*139*/
MTK_PULL_PU_PD_RSEL_TYPE,/*140*/ MTK_PULL_PU_PD_RSEL_TYPE,/*141*/
MTK_PULL_PU_PD_RSEL_TYPE,/*142*/ MTK_PULL_PU_PD_TYPE,/*143*/
MTK_PULL_PU_PD_TYPE,/*144*/ MTK_PULL_PU_PD_TYPE,/*145*/
MTK_PULL_PU_PD_TYPE,/*146*/ MTK_PULL_PU_PD_TYPE,/*147*/
MTK_PULL_PU_PD_TYPE,/*148*/ MTK_PULL_PU_PD_TYPE,/*149*/
MTK_PULL_PU_PD_TYPE,/*150*/ MTK_PULL_PU_PD_TYPE,/*151*/
MTK_PULL_PUPD_R1R0_TYPE,/*152*/ MTK_PULL_PUPD_R1R0_TYPE,/*153*/
MTK_PULL_PUPD_R1R0_TYPE,/*154*/ MTK_PULL_PUPD_R1R0_TYPE,/*155*/
MTK_PULL_PU_PD_TYPE,/*156*/ MTK_PULL_PU_PD_TYPE,/*157*/
MTK_PULL_PU_PD_TYPE,/*158*/ MTK_PULL_PU_PD_TYPE,/*159*/
MTK_PULL_PU_PD_RSEL_TYPE,/*160*/ MTK_PULL_PU_PD_RSEL_TYPE,/*161*/
MTK_PULL_PU_PD_TYPE,/*162*/ MTK_PULL_PU_PD_TYPE,/*163*/
MTK_PULL_PU_PD_TYPE,/*164*/ MTK_PULL_PU_PD_TYPE,/*165*/
MTK_PULL_PU_PD_TYPE,/*166*/ MTK_PULL_PU_PD_TYPE,/*167*/
MTK_PULL_PU_PD_TYPE,/*168*/ MTK_PULL_PU_PD_TYPE,/*169*/
MTK_PULL_PU_PD_TYPE,/*170*/ MTK_PULL_PU_PD_TYPE,/*171*/
MTK_PULL_PU_PD_TYPE,/*172*/ MTK_PULL_PU_PD_TYPE,/*173*/
MTK_PULL_PU_PD_TYPE,/*174*/ MTK_PULL_PU_PD_TYPE,/*175*/
MTK_PULL_PU_PD_TYPE,/*176*/ MTK_PULL_PU_PD_TYPE,/*177*/
MTK_PULL_PU_PD_TYPE,/*178*/ MTK_PULL_PU_PD_TYPE,/*179*/
MTK_PULL_PU_PD_TYPE,/*180*/ MTK_PULL_PU_PD_TYPE,/*181*/
MTK_PULL_PU_PD_TYPE,/*182*/ MTK_PULL_PUPD_R1R0_TYPE,/*183*/
MTK_PULL_PUPD_R1R0_TYPE,/*184*/ MTK_PULL_PUPD_R1R0_TYPE,/*185*/
MTK_PULL_PUPD_R1R0_TYPE,/*186*/ MTK_PULL_PUPD_R1R0_TYPE,/*187*/
MTK_PULL_PUPD_R1R0_TYPE,/*188*/ MTK_PULL_PUPD_R1R0_TYPE,/*189*/
MTK_PULL_PUPD_R1R0_TYPE,/*190*/ MTK_PULL_PUPD_R1R0_TYPE,/*191*/
MTK_PULL_PUPD_R1R0_TYPE,/*192*/ MTK_PULL_PUPD_R1R0_TYPE,/*193*/
MTK_PULL_PUPD_R1R0_TYPE,/*194*/ MTK_PULL_PU_PD_TYPE,/*195*/
MTK_PULL_PU_PD_TYPE,/*196*/ MTK_PULL_PU_PD_TYPE,/*197*/
MTK_PULL_PU_PD_TYPE,/*198*/ MTK_PULL_PU_PD_TYPE,/*199*/
MTK_PULL_PU_PD_RSEL_TYPE,/*200*/ MTK_PULL_PU_PD_RSEL_TYPE,/*201*/
MTK_PULL_PU_PD_RSEL_TYPE,/*202*/ MTK_PULL_PU_PD_RSEL_TYPE,/*203*/
MTK_PULL_PU_PD_RSEL_TYPE,/*204*/ MTK_PULL_PU_PD_RSEL_TYPE,/*205*/
MTK_PULL_PU_PD_TYPE,/*206*/ MTK_PULL_PU_PD_TYPE,/*207*/
MTK_PULL_PU_PD_TYPE,/*208*/ MTK_PULL_PU_PD_TYPE,/*209*/
MTK_PULL_PU_PD_TYPE,/*210*/ MTK_PULL_PU_PD_TYPE,/*211*/
MTK_PULL_PU_PD_TYPE,/*212*/ MTK_PULL_PU_PD_TYPE,/*213*/
MTK_PULL_PU_PD_TYPE,/*214*/ MTK_PULL_PU_PD_TYPE,/*215*/
MTK_PULL_PU_PD_TYPE,/*216*/ MTK_PULL_PU_PD_TYPE,/*217*/
MTK_PULL_PU_PD_TYPE,/*218*/ MTK_PULL_PU_PD_TYPE,/*219*/
};
static const char * const mt8192_pinctrl_register_base_names[] = {
"iocfg0", "iocfg_rm", "iocfg_bm", "iocfg_bl", "iocfg_br",
"iocfg_lm", "iocfg_lb", "iocfg_rt", "iocfg_lt", "iocfg_tl",
@ -1355,9 +1387,8 @@ static const struct mtk_pin_reg_calc mt8192_reg_cals[PINCTRL_PIN_REG_MAX] = {
[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt8192_pin_pupd_range),
[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8192_pin_r0_range),
[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8192_pin_r1_range),
[PINCTRL_PIN_REG_DRV_EN] = MTK_RANGE(mt8192_pin_e1e0en_range),
[PINCTRL_PIN_REG_DRV_E0] = MTK_RANGE(mt8192_pin_e0_range),
[PINCTRL_PIN_REG_DRV_E1] = MTK_RANGE(mt8192_pin_e1_range),
[PINCTRL_PIN_REG_DRV_ADV] = MTK_RANGE(mt8192_pin_drv_adv_range),
[PINCTRL_PIN_REG_RSEL] = MTK_RANGE(mt8192_pin_rsel_range),
};
static const struct mtk_pin_soc mt8192_data = {
@ -1367,17 +1398,16 @@ static const struct mtk_pin_soc mt8192_data = {
.ngrps = ARRAY_SIZE(mtk_pins_mt8192),
.base_names = mt8192_pinctrl_register_base_names,
.nbase_names = ARRAY_SIZE(mt8192_pinctrl_register_base_names),
.pull_type = mt8192_pull_type,
.eint_hw = &mt8192_eint_hw,
.nfuncs = 8,
.gpio_m = 0,
.bias_set_combo = mtk_pinconf_bias_set_combo,
.bias_get_combo = mtk_pinconf_bias_get_combo,
.drive_set = mtk_pinconf_drive_set_raw,
.drive_get = mtk_pinconf_drive_get_raw,
.adv_pull_get = mtk_pinconf_adv_pull_get,
.adv_pull_set = mtk_pinconf_adv_pull_set,
.adv_drive_get = mtk_pinconf_adv_drive_get,
.adv_drive_set = mtk_pinconf_adv_drive_set,
.drive_set = mtk_pinconf_drive_set_rev1,
.drive_get = mtk_pinconf_drive_get_rev1,
.adv_drive_get = mtk_pinconf_adv_drive_get_raw,
.adv_drive_set = mtk_pinconf_adv_drive_set_raw,
};
static const struct of_device_id mt8192_pinctrl_of_match[] = {

10
drivers/pinctrl/mvebu/pinctrl-mvebu.c
View File

@ -96,10 +96,12 @@ static struct mvebu_pinctrl_group *mvebu_pinctrl_find_group_by_name(
struct mvebu_pinctrl *pctl, const char *name)
{
unsigned n;
for (n = 0; n < pctl->num_groups; n++) {
if (strcmp(name, pctl->groups[n].name) == 0)
return &pctl->groups[n];
}
return NULL;
}
@ -108,6 +110,7 @@ static struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_setting_by_val(
unsigned long config)
{
unsigned n;
for (n = 0; n < grp->num_settings; n++) {
if (config == grp->settings[n].val) {
if (!pctl->variant || (pctl->variant &
@ -115,6 +118,7 @@ static struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_setting_by_val(
return &grp->settings[n];
}
}
return NULL;
}
@ -123,6 +127,7 @@ static struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_setting_by_name(
const char *name)
{
unsigned n;
for (n = 0; n < grp->num_settings; n++) {
if (strcmp(name, grp->settings[n].name) == 0) {
if (!pctl->variant || (pctl->variant &
@ -130,6 +135,7 @@ static struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_setting_by_name(
return &grp->settings[n];
}
}
return NULL;
}
@ -137,6 +143,7 @@ static struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_gpio_setting(
struct mvebu_pinctrl *pctl, struct mvebu_pinctrl_group *grp)
{
unsigned n;
for (n = 0; n < grp->num_settings; n++) {
if (grp->settings[n].flags &
(MVEBU_SETTING_GPO | MVEBU_SETTING_GPI)) {
@ -145,6 +152,7 @@ static struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_gpio_setting(
return &grp->settings[n];
}
}
return NULL;
}
@ -152,10 +160,12 @@ static struct mvebu_pinctrl_function *mvebu_pinctrl_find_function_by_name(
struct mvebu_pinctrl *pctl, const char *name)
{
unsigned n;
for (n = 0; n < pctl->num_functions; n++) {
if (strcmp(name, pctl->functions[n].name) == 0)
return &pctl->functions[n];
}
return NULL;
}

4
drivers/pinctrl/nomadik/pinctrl-nomadik.c
View File

@ -1421,8 +1421,10 @@ static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
has_config = nmk_pinctrl_dt_get_config(np, &configs);
np_config = of_parse_phandle(np, "ste,config", 0);
if (np_config)
if (np_config) {
has_config |= nmk_pinctrl_dt_get_config(np_config, &configs);
of_node_put(np_config);
}
if (has_config) {
const char *gpio_name;
const char *pin;

242
drivers/pinctrl/pinctrl-amd.c
View File

@ -6,8 +6,6 @@
* Authors: Ken Xue <Ken.Xue@amd.com>
* Wu, Jeff <Jeff.Wu@amd.com>
*
* Contact Information: Nehal Shah <Nehal-bakulchandra.Shah@amd.com>
* Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
*/
#include <linux/err.h>
@ -31,6 +29,7 @@
#include <linux/bitops.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinmux.h>
#include "core.h"
#include "pinctrl-utils.h"
@ -203,8 +202,6 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
bool tmr_out_unit;
unsigned int time;
unsigned int unit;
bool tmr_large;
char *level_trig;
@ -218,13 +215,13 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
char *pull_up_sel;
char *pull_up_enable;
char *pull_down_enable;
char *output_value;
char *output_enable;
char *orientation;
char debounce_value[40];
char *debounce_enable;
for (bank = 0; bank < gpio_dev->hwbank_num; bank++) {
seq_printf(s, "GPIO bank%d\t", bank);
unsigned int time = 0;
unsigned int unit = 0;
switch (bank) {
case 0:
@ -247,8 +244,9 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
/* Illegal bank number, ignore */
continue;
}
seq_printf(s, "GPIO bank%d\n", bank);
for (; i < pin_num; i++) {
seq_printf(s, "pin%d\t", i);
seq_printf(s, "📌%d\t", i);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + i * 4);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
@ -256,84 +254,91 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) &
ACTIVE_LEVEL_MASK;
interrupt_enable = "interrupt is enabled|";
interrupt_enable = "+";
if (level == ACTIVE_LEVEL_HIGH)
active_level = "Active high|";
active_level = "↑";
else if (level == ACTIVE_LEVEL_LOW)
active_level = "Active low|";
active_level = "↓";
else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) &&
level == ACTIVE_LEVEL_BOTH)
active_level = "Active on both|";
active_level = "b";
else
active_level = "Unknown Active level|";
active_level = "?";
if (pin_reg & BIT(LEVEL_TRIG_OFF))
level_trig = "Level trigger|";
level_trig = "level";
else
level_trig = "Edge trigger|";
level_trig = " edge";
} else {
interrupt_enable =
"interrupt is disabled|";
active_level = " ";
level_trig = " ";
interrupt_enable = "∅";
active_level = "∅";
level_trig = " ∅";
}
if (pin_reg & BIT(INTERRUPT_MASK_OFF))
interrupt_mask =
"interrupt is unmasked|";
interrupt_mask = "-";
else
interrupt_mask =
"interrupt is masked|";
interrupt_mask = "+";
seq_printf(s, "int %s (🎭 %s)| active-%s| %s-🔫| ",
interrupt_enable,
interrupt_mask,
active_level,
level_trig);
if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3))
wake_cntrl0 = "enable wakeup in S0i3 state|";
wake_cntrl0 = "+";
else
wake_cntrl0 = "disable wakeup in S0i3 state|";
wake_cntrl0 = "∅";
seq_printf(s, "S0i3 🌅 %s| ", wake_cntrl0);
if (pin_reg & BIT(WAKE_CNTRL_OFF_S3))
wake_cntrl1 = "enable wakeup in S3 state|";
wake_cntrl1 = "+";
else
wake_cntrl1 = "disable wakeup in S3 state|";
wake_cntrl1 = "∅";
seq_printf(s, "S3 🌅 %s| ", wake_cntrl1);
if (pin_reg & BIT(WAKE_CNTRL_OFF_S4))
wake_cntrl2 = "enable wakeup in S4/S5 state|";
wake_cntrl2 = "+";
else
wake_cntrl2 = "disable wakeup in S4/S5 state|";
wake_cntrl2 = "∅";
seq_printf(s, "S4/S5 🌅 %s| ", wake_cntrl2);
if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
pull_up_enable = "pull-up is enabled|";
pull_up_enable = "+";
if (pin_reg & BIT(PULL_UP_SEL_OFF))
pull_up_sel = "8k pull-up|";
pull_up_sel = "8k";
else
pull_up_sel = "4k pull-up|";
pull_up_sel = "4k";
} else {
pull_up_enable = "pull-up is disabled|";
pull_up_sel = " ";
pull_up_enable = "∅";
pull_up_sel = " ";
}
seq_printf(s, "pull-↑ %s (%s)| ",
pull_up_enable,
pull_up_sel);
if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF))
pull_down_enable = "pull-down is enabled|";
pull_down_enable = "+";
else
pull_down_enable = "Pull-down is disabled|";
pull_down_enable = "∅";
seq_printf(s, "pull-↓ %s| ", pull_down_enable);
if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
pin_sts = " ";
output_enable = "output is enabled|";
pin_sts = "output";
if (pin_reg & BIT(OUTPUT_VALUE_OFF))
output_value = "output is high|";
orientation = "↑";
else
output_value = "output is low|";
orientation = "↓";
} else {
output_enable = "output is disabled|";
output_value = " ";
pin_sts = "input ";
if (pin_reg & BIT(PIN_STS_OFF))
pin_sts = "input is high|";
orientation = "↑";
else
pin_sts = "input is low|";
orientation = "↓";
}
seq_printf(s, "%s %s| ", pin_sts, orientation);
db_cntrl = (DB_CNTRl_MASK << DB_CNTRL_OFF) & pin_reg;
if (db_cntrl) {
@ -352,27 +357,18 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
unit = 61;
}
if ((DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF) == db_cntrl)
debounce_enable = "debouncing filter (high and low) enabled|";
debounce_enable = "b +";
else if ((DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF) == db_cntrl)
debounce_enable = "debouncing filter (low) enabled|";
debounce_enable = "↓ +";
else
debounce_enable = "debouncing filter (high) enabled|";
debounce_enable = "↑ +";
snprintf(debounce_value, sizeof(debounce_value),
"debouncing timeout is %u (us)|", time * unit);
} else {
debounce_enable = "debouncing filter disabled|";
snprintf(debounce_value, sizeof(debounce_value), " ");
debounce_enable = " ∅";
}
seq_printf(s, "%s %s %s %s %s %s\n"
" %s %s %s %s %s %s %s %s %s 0x%x\n",
level_trig, active_level, interrupt_enable,
interrupt_mask, wake_cntrl0, wake_cntrl1,
wake_cntrl2, pin_sts, pull_up_sel,
pull_up_enable, pull_down_enable,
output_value, output_enable,
debounce_enable, debounce_value, pin_reg);
snprintf(debounce_value, sizeof(debounce_value), "%u", time * unit);
seq_printf(s, "debounce %s (⏰ %sus)| ", debounce_enable, debounce_value);
seq_printf(s, " 0x%x\n", pin_reg);
}
}
}
@ -917,6 +913,7 @@ static int amd_gpio_suspend(struct device *dev)
{
struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
unsigned long flags;
int i;
for (i = 0; i < desc->npins; i++) {
@ -925,7 +922,9 @@ static int amd_gpio_suspend(struct device *dev)
if (!amd_gpio_should_save(gpio_dev, pin))
continue;
gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin*4);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin * 4) & ~PIN_IRQ_PENDING;
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
}
return 0;
@ -935,6 +934,7 @@ static int amd_gpio_resume(struct device *dev)
{
struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
unsigned long flags;
int i;
for (i = 0; i < desc->npins; i++) {
@ -943,7 +943,10 @@ static int amd_gpio_resume(struct device *dev)
if (!amd_gpio_should_save(gpio_dev, pin))
continue;
writel(gpio_dev->saved_regs[i], gpio_dev->base + pin*4);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING;
writel(gpio_dev->saved_regs[i], gpio_dev->base + pin * 4);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
}
return 0;
@ -955,14 +958,115 @@ static const struct dev_pm_ops amd_gpio_pm_ops = {
};
#endif
static int amd_get_functions_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(pmx_functions);
}
static const char *amd_get_fname(struct pinctrl_dev *pctrldev, unsigned int selector)
{
return pmx_functions[selector].name;
}
static int amd_get_groups(struct pinctrl_dev *pctrldev, unsigned int selector,
const char * const **groups,
unsigned int * const num_groups)
{
struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev);
if (!gpio_dev->iomux_base) {
dev_err(&gpio_dev->pdev->dev, "iomux function %d group not supported\n", selector);
return -EINVAL;
}
*groups = pmx_functions[selector].groups;
*num_groups = pmx_functions[selector].ngroups;
return 0;
}
static int amd_set_mux(struct pinctrl_dev *pctrldev, unsigned int function, unsigned int group)
{
struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev);
struct device *dev = &gpio_dev->pdev->dev;
struct pin_desc *pd;
int ind, index;
if (!gpio_dev->iomux_base)
return -EINVAL;
for (index = 0; index < NSELECTS; index++) {
if (strcmp(gpio_dev->groups[group].name, pmx_functions[function].groups[index]))
continue;
if (readb(gpio_dev->iomux_base + pmx_functions[function].index) ==
FUNCTION_INVALID) {
dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n",
pmx_functions[function].index);
return -EINVAL;
}
writeb(index, gpio_dev->iomux_base + pmx_functions[function].index);
if (index != (readb(gpio_dev->iomux_base + pmx_functions[function].index) &
FUNCTION_MASK)) {
dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n",
pmx_functions[function].index);
return -EINVAL;
}
for (ind = 0; ind < gpio_dev->groups[group].npins; ind++) {
if (strncmp(gpio_dev->groups[group].name, "IMX_F", strlen("IMX_F")))
continue;
pd = pin_desc_get(gpio_dev->pctrl, gpio_dev->groups[group].pins[ind]);
pd->mux_owner = gpio_dev->groups[group].name;
}
break;
}
return 0;
}
static const struct pinmux_ops amd_pmxops = {
.get_functions_count = amd_get_functions_count,
.get_function_name = amd_get_fname,
.get_function_groups = amd_get_groups,
.set_mux = amd_set_mux,
};
static struct pinctrl_desc amd_pinctrl_desc = {
.pins = kerncz_pins,
.npins = ARRAY_SIZE(kerncz_pins),
.pctlops = &amd_pinctrl_ops,
.pmxops = &amd_pmxops,
.confops = &amd_pinconf_ops,
.owner = THIS_MODULE,
};
static void amd_get_iomux_res(struct amd_gpio *gpio_dev)
{
struct pinctrl_desc *desc = &amd_pinctrl_desc;
struct device *dev = &gpio_dev->pdev->dev;
int index;
index = device_property_match_string(dev, "pinctrl-resource-names", "iomux");
if (index < 0) {
dev_warn(dev, "failed to get iomux index\n");
goto out_no_pinmux;
}
gpio_dev->iomux_base = devm_platform_ioremap_resource(gpio_dev->pdev, index);
if (IS_ERR(gpio_dev->iomux_base)) {
dev_warn(dev, "Failed to get iomux %d io resource\n", index);
goto out_no_pinmux;
}
return;
out_no_pinmux:
desc->pmxops = NULL;
}
static int amd_gpio_probe(struct platform_device *pdev)
{
int ret = 0;
@ -977,17 +1081,12 @@ static int amd_gpio_probe(struct platform_device *pdev)
raw_spin_lock_init(&gpio_dev->lock);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
gpio_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(gpio_dev->base)) {
dev_err(&pdev->dev, "Failed to get gpio io resource.\n");
return -EINVAL;
return PTR_ERR(gpio_dev->base);
}
gpio_dev->base = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
if (!gpio_dev->base)
return -ENOMEM;
gpio_dev->irq = platform_get_irq(pdev, 0);
if (gpio_dev->irq < 0)
return gpio_dev->irq;
@ -1020,6 +1119,7 @@ static int amd_gpio_probe(struct platform_device *pdev)
gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
amd_pinctrl_desc.name = dev_name(&pdev->dev);
amd_get_iomux_res(gpio_dev);
gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc,
gpio_dev);
if (IS_ERR(gpio_dev->pctrl)) {

1376
drivers/pinctrl/pinctrl-amd.h
View File

File diff suppressed because it is too large Load Diff

7
drivers/pinctrl/pinctrl-at91-pio4.c
View File

@ -237,8 +237,6 @@ static void atmel_gpio_irq_unmask(struct irq_data *d)
BIT(pin->line));
}
#ifdef CONFIG_PM_SLEEP
static int atmel_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
{
struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
@ -255,9 +253,6 @@ static int atmel_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
return 0;
}
#else
#define atmel_gpio_irq_set_wake NULL
#endif /* CONFIG_PM_SLEEP */
static struct irq_chip atmel_gpio_irq_chip = {
.name = "GPIO",
@ -265,7 +260,7 @@ static struct irq_chip atmel_gpio_irq_chip = {
.irq_mask = atmel_gpio_irq_mask,
.irq_unmask = atmel_gpio_irq_unmask,
.irq_set_type = atmel_gpio_irq_set_type,
.irq_set_wake = atmel_gpio_irq_set_wake,
.irq_set_wake = pm_sleep_ptr(atmel_gpio_irq_set_wake),
};
static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)

10
drivers/pinctrl/pinctrl-at91.c
View File

@ -1615,8 +1615,6 @@ static void gpio_irq_ack(struct irq_data *d)
/* the interrupt is already cleared before by reading ISR */
}
#ifdef CONFIG_PM
static u32 wakeups[MAX_GPIO_BANKS];
static u32 backups[MAX_GPIO_BANKS];
@ -1683,10 +1681,6 @@ void at91_pinctrl_gpio_resume(void)
}
}
#else
#define gpio_irq_set_wake NULL
#endif /* CONFIG_PM */
static void gpio_irq_handler(struct irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
@ -1741,14 +1735,14 @@ static int at91_gpio_of_irq_setup(struct platform_device *pdev,
gpio_irqchip->irq_disable = gpio_irq_mask;
gpio_irqchip->irq_mask = gpio_irq_mask;
gpio_irqchip->irq_unmask = gpio_irq_unmask;
gpio_irqchip->irq_set_wake = gpio_irq_set_wake;
gpio_irqchip->irq_set_wake = pm_ptr(gpio_irq_set_wake);
gpio_irqchip->irq_set_type = at91_gpio->ops->irq_type;
/* Disable irqs of this PIO controller */
writel_relaxed(~0, at91_gpio->regbase + PIO_IDR);
/*
* Let the generic code handle this edge IRQ, the the chained
* Let the generic code handle this edge IRQ, the chained
* handler will perform the actual work of handling the parent
* interrupt.
*/

14
drivers/pinctrl/pinctrl-axp209.c
View File

@ -73,7 +73,7 @@ static const struct pinctrl_pin_desc axp209_pins[] = {
PINCTRL_PIN(2, "GPIO2"),
};
static const struct pinctrl_pin_desc axp813_pins[] = {
static const struct pinctrl_pin_desc axp22x_pins[] = {
PINCTRL_PIN(0, "GPIO0"),
PINCTRL_PIN(1, "GPIO1"),
};
@ -87,9 +87,16 @@ static const struct axp20x_pctrl_desc axp20x_data = {
.adc_mux = AXP20X_MUX_ADC,
};
static const struct axp20x_pctrl_desc axp22x_data = {
.pins = axp22x_pins,
.npins = ARRAY_SIZE(axp22x_pins),
.ldo_mask = BIT(0) | BIT(1),
.gpio_status_offset = 0,
};
static const struct axp20x_pctrl_desc axp813_data = {
.pins = axp813_pins,
.npins = ARRAY_SIZE(axp813_pins),
.pins = axp22x_pins,
.npins = ARRAY_SIZE(axp22x_pins),
.ldo_mask = BIT(0) | BIT(1),
.adc_mask = BIT(0),
.gpio_status_offset = 0,
@ -388,6 +395,7 @@ static int axp20x_build_funcs_groups(struct platform_device *pdev)
static const struct of_device_id axp20x_pctl_match[] = {
{ .compatible = "x-powers,axp209-gpio", .data = &axp20x_data, },
{ .compatible = "x-powers,axp221-gpio", .data = &axp22x_data, },
{ .compatible = "x-powers,axp813-gpio", .data = &axp813_data, },
{ }
};

64
drivers/pinctrl/pinctrl-ingenic.c
View File

@ -21,6 +21,7 @@
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include "core.h"
@ -135,7 +136,6 @@ struct ingenic_pinctrl {
struct ingenic_gpio_chip {
struct ingenic_pinctrl *jzpc;
struct gpio_chip gc;
struct irq_chip irq_chip;
unsigned int irq, reg_base;
};
@ -3393,7 +3393,7 @@ static void ingenic_gpio_irq_mask(struct irq_data *irqd)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
int irq = irqd->hwirq;
irq_hw_number_t irq = irqd_to_hwirq(irqd);
if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
ingenic_gpio_set_bit(jzgc, GPIO_MSK, irq, true);
@ -3405,7 +3405,7 @@ static void ingenic_gpio_irq_unmask(struct irq_data *irqd)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
int irq = irqd->hwirq;
irq_hw_number_t irq = irqd_to_hwirq(irqd);
if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
ingenic_gpio_set_bit(jzgc, GPIO_MSK, irq, false);
@ -3417,7 +3417,9 @@ static void ingenic_gpio_irq_enable(struct irq_data *irqd)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
int irq = irqd->hwirq;
irq_hw_number_t irq = irqd_to_hwirq(irqd);
gpiochip_enable_irq(gc, irq);
if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, true);
@ -3433,7 +3435,7 @@ static void ingenic_gpio_irq_disable(struct irq_data *irqd)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
int irq = irqd->hwirq;
irq_hw_number_t irq = irqd_to_hwirq(irqd);
ingenic_gpio_irq_mask(irqd);
@ -3443,13 +3445,15 @@ static void ingenic_gpio_irq_disable(struct irq_data *irqd)
ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false);
else
ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIER, irq, false);
gpiochip_disable_irq(gc, irq);
}
static void ingenic_gpio_irq_ack(struct irq_data *irqd)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
int irq = irqd->hwirq;
irq_hw_number_t irq = irqd_to_hwirq(irqd);
bool high;
if ((irqd_get_trigger_type(irqd) == IRQ_TYPE_EDGE_BOTH) &&
@ -3477,6 +3481,7 @@ static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
irq_hw_number_t irq = irqd_to_hwirq(irqd);
switch (type) {
case IRQ_TYPE_EDGE_BOTH:
@ -3498,12 +3503,12 @@ static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
* best we can do is to set up a single-edge interrupt and then
* switch to the opposing edge when ACKing the interrupt.
*/
bool high = ingenic_gpio_get_value(jzgc, irqd->hwirq);
bool high = ingenic_gpio_get_value(jzgc, irq);
type = high ? IRQ_TYPE_LEVEL_LOW : IRQ_TYPE_LEVEL_HIGH;
}
irq_set_type(jzgc, irqd->hwirq, type);
irq_set_type(jzgc, irq, type);
return 0;
}
@ -3668,22 +3673,45 @@ static const struct pinctrl_ops ingenic_pctlops = {
static int ingenic_gpio_irq_request(struct irq_data *data)
{
struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
irq_hw_number_t irq = irqd_to_hwirq(data);
int ret;
ret = ingenic_gpio_direction_input(gpio_chip, data->hwirq);
ret = ingenic_gpio_direction_input(gpio_chip, irq);
if (ret)
return ret;
return gpiochip_reqres_irq(gpio_chip, data->hwirq);
return gpiochip_reqres_irq(gpio_chip, irq);
}
static void ingenic_gpio_irq_release(struct irq_data *data)
{
struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
irq_hw_number_t irq = irqd_to_hwirq(data);
return gpiochip_relres_irq(gpio_chip, data->hwirq);
return gpiochip_relres_irq(gpio_chip, irq);
}
static void ingenic_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p)
{
struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
seq_printf(p, "%s", gpio_chip->label);
}
static const struct irq_chip ingenic_gpio_irqchip = {
.irq_enable = ingenic_gpio_irq_enable,
.irq_disable = ingenic_gpio_irq_disable,
.irq_unmask = ingenic_gpio_irq_unmask,
.irq_mask = ingenic_gpio_irq_mask,
.irq_ack = ingenic_gpio_irq_ack,
.irq_set_type = ingenic_gpio_irq_set_type,
.irq_set_wake = ingenic_gpio_irq_set_wake,
.irq_request_resources = ingenic_gpio_irq_request,
.irq_release_resources = ingenic_gpio_irq_release,
.irq_print_chip = ingenic_gpio_irq_print_chip,
.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,
};
static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc,
int pin, int func)
{
@ -4172,20 +4200,8 @@ static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc,
if (!jzgc->irq)
return -EINVAL;
jzgc->irq_chip.name = jzgc->gc.label;
jzgc->irq_chip.irq_enable = ingenic_gpio_irq_enable;
jzgc->irq_chip.irq_disable = ingenic_gpio_irq_disable;
jzgc->irq_chip.irq_unmask = ingenic_gpio_irq_unmask;
jzgc->irq_chip.irq_mask = ingenic_gpio_irq_mask;
jzgc->irq_chip.irq_ack = ingenic_gpio_irq_ack;
jzgc->irq_chip.irq_set_type = ingenic_gpio_irq_set_type;
jzgc->irq_chip.irq_set_wake = ingenic_gpio_irq_set_wake;
jzgc->irq_chip.irq_request_resources = ingenic_gpio_irq_request;
jzgc->irq_chip.irq_release_resources = ingenic_gpio_irq_release;
jzgc->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND;
girq = &jzgc->gc.irq;
girq->chip = &jzgc->irq_chip;
gpio_irq_chip_set_chip(girq, &ingenic_gpio_irqchip);
girq->parent_handler = ingenic_gpio_irq_handler;
girq->num_parents = 1;
girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),

4
drivers/pinctrl/pinctrl-ocelot.c
View File

@ -1944,6 +1944,7 @@ static const struct of_device_id ocelot_pinctrl_of_match[] = {
{ .compatible = "microchip,lan966x-pinctrl", .data = &lan966x_desc },
{},
};
MODULE_DEVICE_TABLE(of, ocelot_pinctrl_of_match);
static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device *pdev,
const struct ocelot_pinctrl *info)
@ -2050,4 +2051,5 @@ static struct platform_driver ocelot_pinctrl_driver = {
},
.probe = ocelot_pinctrl_probe,
};
builtin_platform_driver(ocelot_pinctrl_driver);
module_platform_driver(ocelot_pinctrl_driver);
MODULE_LICENSE("Dual MIT/GPL");

5
drivers/pinctrl/pinctrl-starfive.c
View File

@ -207,6 +207,7 @@ struct starfive_pinctrl {
void __iomem *base;
void __iomem *padctl;
struct pinctrl_dev *pctl;
struct mutex mutex; /* serialize adding groups and functions */
};
static inline unsigned int starfive_pin_to_gpio(const struct starfive_pinctrl *sfp,
@ -522,6 +523,7 @@ static int starfive_dt_node_to_map(struct pinctrl_dev *pctldev,
nmaps = 0;
ngroups = 0;
mutex_lock(&sfp->mutex);
for_each_child_of_node(np, child) {
int npins;
int i;
@ -615,12 +617,14 @@ static int starfive_dt_node_to_map(struct pinctrl_dev *pctldev,
*maps = map;
*num_maps = nmaps;
mutex_unlock(&sfp->mutex);
return 0;
put_child:
of_node_put(child);
free_map:
pinctrl_utils_free_map(pctldev, map, nmaps);
mutex_unlock(&sfp->mutex);
return ret;
}
@ -1267,6 +1271,7 @@ static int starfive_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, sfp);
sfp->gc.parent = dev;
raw_spin_lock_init(&sfp->lock);
mutex_init(&sfp->mutex);
ret = devm_pinctrl_register_and_init(dev, &starfive_desc, sfp, &sfp->pctl);
if (ret)

11
drivers/pinctrl/pinctrl-zynqmp.c
View File

@ -163,6 +163,8 @@ static const char *zynqmp_pmux_get_function_name(struct pinctrl_dev *pctldev,
* @num_groups: Number of function groups.
*
* Get function's group count and group names.
*
* Return: 0
*/
static int zynqmp_pmux_get_function_groups(struct pinctrl_dev *pctldev,
unsigned int selector,
@ -410,6 +412,10 @@ static int zynqmp_pinconf_cfg_set(struct pinctrl_dev *pctldev,
break;
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
param = PM_PINCTRL_CONFIG_TRI_STATE;
arg = PM_PINCTRL_TRI_STATE_ENABLE;
ret = zynqmp_pm_pinctrl_set_config(pin, param, arg);
break;
case PIN_CONFIG_MODE_LOW_POWER:
/*
* These cases are mentioned in dts but configurable
@ -418,6 +424,11 @@ static int zynqmp_pinconf_cfg_set(struct pinctrl_dev *pctldev,
*/
ret = 0;
break;
case PIN_CONFIG_OUTPUT_ENABLE:
param = PM_PINCTRL_CONFIG_TRI_STATE;
arg = PM_PINCTRL_TRI_STATE_DISABLE;
ret = zynqmp_pm_pinctrl_set_config(pin, param, arg);
break;
default:
dev_warn(pctldev->dev,
"unsupported configuration parameter '%u'\n",

19
drivers/pinctrl/qcom/Kconfig
View File

@ -113,6 +113,14 @@ config PINCTRL_MSM8X74
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm 8974 platform.
config PINCTRL_MSM8909
tristate "Qualcomm 8909 pin controller driver"
depends on OF
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found on the Qualcomm MSM8909 platform.
config PINCTRL_MSM8916
tristate "Qualcomm 8916 pin controller driver"
depends on OF
@ -320,6 +328,15 @@ config PINCTRL_SM6350
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SM6350 platform.
config PINCTRL_SM6375
tristate "Qualcomm Technologies Inc SM6375 pin controller driver"
depends on GPIOLIB && OF
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SM6375 platform.
config PINCTRL_SDX65
tristate "Qualcomm Technologies Inc SDX65 pin controller driver"
depends on GPIOLIB && OF
@ -367,7 +384,7 @@ config PINCTRL_SM8350
config PINCTRL_SM8450
tristate "Qualcomm Technologies Inc SM8450 pin controller driver"
depends on GPIOLIB && OF
select PINCTRL_MSM
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm

2
drivers/pinctrl/qcom/Makefile
View File

@ -11,6 +11,7 @@ obj-$(CONFIG_PINCTRL_MSM8226) += pinctrl-msm8226.o
obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o
obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o
obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o
obj-$(CONFIG_PINCTRL_MSM8909) += pinctrl-msm8909.o
obj-$(CONFIG_PINCTRL_MSM8916) += pinctrl-msm8916.o
obj-$(CONFIG_PINCTRL_MSM8953) += pinctrl-msm8953.o
obj-$(CONFIG_PINCTRL_MSM8976) += pinctrl-msm8976.o
@ -37,6 +38,7 @@ obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o
obj-$(CONFIG_PINCTRL_SM6115) += pinctrl-sm6115.o
obj-$(CONFIG_PINCTRL_SM6125) += pinctrl-sm6125.o
obj-$(CONFIG_PINCTRL_SM6350) += pinctrl-sm6350.o
obj-$(CONFIG_PINCTRL_SM6375) += pinctrl-sm6375.o
obj-$(CONFIG_PINCTRL_SDX65) += pinctrl-sdx65.o
obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o
obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o

2
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
View File

@ -401,7 +401,7 @@ int lpi_pinctrl_probe(struct platform_device *pdev)
return dev_err_probe(dev, PTR_ERR(pctrl->slew_base),
"Slew resource not provided\n");
if (data->is_clk_optional)
if (of_property_read_bool(dev->of_node, "qcom,adsp-bypass-mode"))
ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
else
ret = devm_clk_bulk_get(dev, MAX_LPI_NUM_CLKS, pctrl->clks);

1
drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
View File

@ -77,7 +77,6 @@ struct lpi_pinctrl_variant_data {
int ngroups;
const struct lpi_function *functions;
int nfunctions;
bool is_clk_optional;
};
int lpi_pinctrl_probe(struct platform_device *pdev);

956
drivers/pinctrl/qcom/pinctrl-msm8909.c Normal file
View File

@ -0,0 +1,956 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
* Copyright (C) 2022, Kernkonzept GmbH.
*/
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
#define FUNCTION(fname) \
[msm_mux_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define REG_SIZE 0x1000
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = ARRAY_SIZE(gpio##id##_pins), \
.funcs = (int[]){ \
msm_mux_gpio, \
msm_mux_##f1, \
msm_mux_##f2, \
msm_mux_##f3, \
msm_mux_##f4, \
msm_mux_##f5, \
msm_mux_##f6, \
msm_mux_##f7, \
msm_mux_##f8, \
msm_mux_##f9, \
}, \
.nfuncs = 10, \
.ctl_reg = REG_SIZE * id, \
.io_reg = 0x4 + REG_SIZE * id, \
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
.intr_status_reg = 0xc + REG_SIZE * id, \
.intr_target_reg = 0x8 + REG_SIZE * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
.oe_bit = 9, \
.in_bit = 0, \
.out_bit = 1, \
.intr_enable_bit = 0, \
.intr_status_bit = 0, \
.intr_target_bit = 5, \
.intr_target_kpss_val = 4, \
.intr_raw_status_bit = 4, \
.intr_polarity_bit = 1, \
.intr_detection_bit = 2, \
.intr_detection_width = 2, \
}
#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = ARRAY_SIZE(pg_name##_pins), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = pull, \
.drv_bit = drv, \
.oe_bit = -1, \
.in_bit = -1, \
.out_bit = -1, \
.intr_enable_bit = -1, \
.intr_status_bit = -1, \
.intr_target_bit = -1, \
.intr_raw_status_bit = -1, \
.intr_polarity_bit = -1, \
.intr_detection_bit = -1, \
.intr_detection_width = -1, \
}
static const struct pinctrl_pin_desc msm8909_pins[] = {
PINCTRL_PIN(0, "GPIO_0"),
PINCTRL_PIN(1, "GPIO_1"),
PINCTRL_PIN(2, "GPIO_2"),
PINCTRL_PIN(3, "GPIO_3"),
PINCTRL_PIN(4, "GPIO_4"),
PINCTRL_PIN(5, "GPIO_5"),
PINCTRL_PIN(6, "GPIO_6"),
PINCTRL_PIN(7, "GPIO_7"),
PINCTRL_PIN(8, "GPIO_8"),
PINCTRL_PIN(9, "GPIO_9"),
PINCTRL_PIN(10, "GPIO_10"),
PINCTRL_PIN(11, "GPIO_11"),
PINCTRL_PIN(12, "GPIO_12"),
PINCTRL_PIN(13, "GPIO_13"),
PINCTRL_PIN(14, "GPIO_14"),
PINCTRL_PIN(15, "GPIO_15"),
PINCTRL_PIN(16, "GPIO_16"),
PINCTRL_PIN(17, "GPIO_17"),
PINCTRL_PIN(18, "GPIO_18"),
PINCTRL_PIN(19, "GPIO_19"),
PINCTRL_PIN(20, "GPIO_20"),
PINCTRL_PIN(21, "GPIO_21"),
PINCTRL_PIN(22, "GPIO_22"),
PINCTRL_PIN(23, "GPIO_23"),
PINCTRL_PIN(24, "GPIO_24"),
PINCTRL_PIN(25, "GPIO_25"),
PINCTRL_PIN(26, "GPIO_26"),
PINCTRL_PIN(27, "GPIO_27"),
PINCTRL_PIN(28, "GPIO_28"),
PINCTRL_PIN(29, "GPIO_29"),
PINCTRL_PIN(30, "GPIO_30"),
PINCTRL_PIN(31, "GPIO_31"),
PINCTRL_PIN(32, "GPIO_32"),
PINCTRL_PIN(33, "GPIO_33"),
PINCTRL_PIN(34, "GPIO_34"),
PINCTRL_PIN(35, "GPIO_35"),
PINCTRL_PIN(36, "GPIO_36"),
PINCTRL_PIN(37, "GPIO_37"),
PINCTRL_PIN(38, "GPIO_38"),
PINCTRL_PIN(39, "GPIO_39"),
PINCTRL_PIN(40, "GPIO_40"),
PINCTRL_PIN(41, "GPIO_41"),
PINCTRL_PIN(42, "GPIO_42"),
PINCTRL_PIN(43, "GPIO_43"),
PINCTRL_PIN(44, "GPIO_44"),
PINCTRL_PIN(45, "GPIO_45"),
PINCTRL_PIN(46, "GPIO_46"),
PINCTRL_PIN(47, "GPIO_47"),
PINCTRL_PIN(48, "GPIO_48"),
PINCTRL_PIN(49, "GPIO_49"),
PINCTRL_PIN(50, "GPIO_50"),
PINCTRL_PIN(51, "GPIO_51"),
PINCTRL_PIN(52, "GPIO_52"),
PINCTRL_PIN(53, "GPIO_53"),
PINCTRL_PIN(54, "GPIO_54"),
PINCTRL_PIN(55, "GPIO_55"),
PINCTRL_PIN(56, "GPIO_56"),
PINCTRL_PIN(57, "GPIO_57"),
PINCTRL_PIN(58, "GPIO_58"),
PINCTRL_PIN(59, "GPIO_59"),
PINCTRL_PIN(60, "GPIO_60"),
PINCTRL_PIN(61, "GPIO_61"),
PINCTRL_PIN(62, "GPIO_62"),
PINCTRL_PIN(63, "GPIO_63"),
PINCTRL_PIN(64, "GPIO_64"),
PINCTRL_PIN(65, "GPIO_65"),
PINCTRL_PIN(66, "GPIO_66"),
PINCTRL_PIN(67, "GPIO_67"),
PINCTRL_PIN(68, "GPIO_68"),
PINCTRL_PIN(69, "GPIO_69"),
PINCTRL_PIN(70, "GPIO_70"),
PINCTRL_PIN(71, "GPIO_71"),
PINCTRL_PIN(72, "GPIO_72"),
PINCTRL_PIN(73, "GPIO_73"),
PINCTRL_PIN(74, "GPIO_74"),
PINCTRL_PIN(75, "GPIO_75"),
PINCTRL_PIN(76, "GPIO_76"),
PINCTRL_PIN(77, "GPIO_77"),
PINCTRL_PIN(78, "GPIO_78"),
PINCTRL_PIN(79, "GPIO_79"),
PINCTRL_PIN(80, "GPIO_80"),
PINCTRL_PIN(81, "GPIO_81"),
PINCTRL_PIN(82, "GPIO_82"),
PINCTRL_PIN(83, "GPIO_83"),
PINCTRL_PIN(84, "GPIO_84"),
PINCTRL_PIN(85, "GPIO_85"),
PINCTRL_PIN(86, "GPIO_86"),
PINCTRL_PIN(87, "GPIO_87"),
PINCTRL_PIN(88, "GPIO_88"),
PINCTRL_PIN(89, "GPIO_89"),
PINCTRL_PIN(90, "GPIO_90"),
PINCTRL_PIN(91, "GPIO_91"),
PINCTRL_PIN(92, "GPIO_92"),
PINCTRL_PIN(93, "GPIO_93"),
PINCTRL_PIN(94, "GPIO_94"),
PINCTRL_PIN(95, "GPIO_95"),
PINCTRL_PIN(96, "GPIO_96"),
PINCTRL_PIN(97, "GPIO_97"),
PINCTRL_PIN(98, "GPIO_98"),
PINCTRL_PIN(99, "GPIO_99"),
PINCTRL_PIN(100, "GPIO_100"),
PINCTRL_PIN(101, "GPIO_101"),
PINCTRL_PIN(102, "GPIO_102"),
PINCTRL_PIN(103, "GPIO_103"),
PINCTRL_PIN(104, "GPIO_104"),
PINCTRL_PIN(105, "GPIO_105"),
PINCTRL_PIN(106, "GPIO_106"),
PINCTRL_PIN(107, "GPIO_107"),
PINCTRL_PIN(108, "GPIO_108"),
PINCTRL_PIN(109, "GPIO_109"),
PINCTRL_PIN(110, "GPIO_110"),
PINCTRL_PIN(111, "GPIO_111"),
PINCTRL_PIN(112, "GPIO_112"),
PINCTRL_PIN(113, "SDC1_CLK"),
PINCTRL_PIN(114, "SDC1_CMD"),
PINCTRL_PIN(115, "SDC1_DATA"),
PINCTRL_PIN(116, "SDC2_CLK"),
PINCTRL_PIN(117, "SDC2_CMD"),
PINCTRL_PIN(118, "SDC2_DATA"),
PINCTRL_PIN(119, "QDSD_CLK"),
PINCTRL_PIN(120, "QDSD_CMD"),
PINCTRL_PIN(121, "QDSD_DATA0"),
PINCTRL_PIN(122, "QDSD_DATA1"),
PINCTRL_PIN(123, "QDSD_DATA2"),
PINCTRL_PIN(124, "QDSD_DATA3"),
};
#define DECLARE_MSM_GPIO_PINS(pin) \
static const unsigned int gpio##pin##_pins[] = { pin }
DECLARE_MSM_GPIO_PINS(0);
DECLARE_MSM_GPIO_PINS(1);
DECLARE_MSM_GPIO_PINS(2);
DECLARE_MSM_GPIO_PINS(3);
DECLARE_MSM_GPIO_PINS(4);
DECLARE_MSM_GPIO_PINS(5);
DECLARE_MSM_GPIO_PINS(6);
DECLARE_MSM_GPIO_PINS(7);
DECLARE_MSM_GPIO_PINS(8);
DECLARE_MSM_GPIO_PINS(9);
DECLARE_MSM_GPIO_PINS(10);
DECLARE_MSM_GPIO_PINS(11);
DECLARE_MSM_GPIO_PINS(12);
DECLARE_MSM_GPIO_PINS(13);
DECLARE_MSM_GPIO_PINS(14);
DECLARE_MSM_GPIO_PINS(15);
DECLARE_MSM_GPIO_PINS(16);
DECLARE_MSM_GPIO_PINS(17);
DECLARE_MSM_GPIO_PINS(18);
DECLARE_MSM_GPIO_PINS(19);
DECLARE_MSM_GPIO_PINS(20);
DECLARE_MSM_GPIO_PINS(21);
DECLARE_MSM_GPIO_PINS(22);
DECLARE_MSM_GPIO_PINS(23);
DECLARE_MSM_GPIO_PINS(24);
DECLARE_MSM_GPIO_PINS(25);
DECLARE_MSM_GPIO_PINS(26);
DECLARE_MSM_GPIO_PINS(27);
DECLARE_MSM_GPIO_PINS(28);
DECLARE_MSM_GPIO_PINS(29);
DECLARE_MSM_GPIO_PINS(30);
DECLARE_MSM_GPIO_PINS(31);
DECLARE_MSM_GPIO_PINS(32);
DECLARE_MSM_GPIO_PINS(33);
DECLARE_MSM_GPIO_PINS(34);
DECLARE_MSM_GPIO_PINS(35);
DECLARE_MSM_GPIO_PINS(36);
DECLARE_MSM_GPIO_PINS(37);
DECLARE_MSM_GPIO_PINS(38);
DECLARE_MSM_GPIO_PINS(39);
DECLARE_MSM_GPIO_PINS(40);
DECLARE_MSM_GPIO_PINS(41);
DECLARE_MSM_GPIO_PINS(42);
DECLARE_MSM_GPIO_PINS(43);
DECLARE_MSM_GPIO_PINS(44);
DECLARE_MSM_GPIO_PINS(45);
DECLARE_MSM_GPIO_PINS(46);
DECLARE_MSM_GPIO_PINS(47);
DECLARE_MSM_GPIO_PINS(48);
DECLARE_MSM_GPIO_PINS(49);
DECLARE_MSM_GPIO_PINS(50);
DECLARE_MSM_GPIO_PINS(51);
DECLARE_MSM_GPIO_PINS(52);
DECLARE_MSM_GPIO_PINS(53);
DECLARE_MSM_GPIO_PINS(54);
DECLARE_MSM_GPIO_PINS(55);
DECLARE_MSM_GPIO_PINS(56);
DECLARE_MSM_GPIO_PINS(57);
DECLARE_MSM_GPIO_PINS(58);
DECLARE_MSM_GPIO_PINS(59);
DECLARE_MSM_GPIO_PINS(60);
DECLARE_MSM_GPIO_PINS(61);
DECLARE_MSM_GPIO_PINS(62);
DECLARE_MSM_GPIO_PINS(63);
DECLARE_MSM_GPIO_PINS(64);
DECLARE_MSM_GPIO_PINS(65);
DECLARE_MSM_GPIO_PINS(66);
DECLARE_MSM_GPIO_PINS(67);
DECLARE_MSM_GPIO_PINS(68);
DECLARE_MSM_GPIO_PINS(69);
DECLARE_MSM_GPIO_PINS(70);
DECLARE_MSM_GPIO_PINS(71);
DECLARE_MSM_GPIO_PINS(72);
DECLARE_MSM_GPIO_PINS(73);
DECLARE_MSM_GPIO_PINS(74);
DECLARE_MSM_GPIO_PINS(75);
DECLARE_MSM_GPIO_PINS(76);
DECLARE_MSM_GPIO_PINS(77);
DECLARE_MSM_GPIO_PINS(78);
DECLARE_MSM_GPIO_PINS(79);
DECLARE_MSM_GPIO_PINS(80);
DECLARE_MSM_GPIO_PINS(81);
DECLARE_MSM_GPIO_PINS(82);
DECLARE_MSM_GPIO_PINS(83);
DECLARE_MSM_GPIO_PINS(84);
DECLARE_MSM_GPIO_PINS(85);
DECLARE_MSM_GPIO_PINS(86);
DECLARE_MSM_GPIO_PINS(87);
DECLARE_MSM_GPIO_PINS(88);
DECLARE_MSM_GPIO_PINS(89);
DECLARE_MSM_GPIO_PINS(90);
DECLARE_MSM_GPIO_PINS(91);
DECLARE_MSM_GPIO_PINS(92);
DECLARE_MSM_GPIO_PINS(93);
DECLARE_MSM_GPIO_PINS(94);
DECLARE_MSM_GPIO_PINS(95);
DECLARE_MSM_GPIO_PINS(96);
DECLARE_MSM_GPIO_PINS(97);
DECLARE_MSM_GPIO_PINS(98);
DECLARE_MSM_GPIO_PINS(99);
DECLARE_MSM_GPIO_PINS(100);
DECLARE_MSM_GPIO_PINS(101);
DECLARE_MSM_GPIO_PINS(102);
DECLARE_MSM_GPIO_PINS(103);
DECLARE_MSM_GPIO_PINS(104);
DECLARE_MSM_GPIO_PINS(105);
DECLARE_MSM_GPIO_PINS(106);
DECLARE_MSM_GPIO_PINS(107);
DECLARE_MSM_GPIO_PINS(108);
DECLARE_MSM_GPIO_PINS(109);
DECLARE_MSM_GPIO_PINS(110);
DECLARE_MSM_GPIO_PINS(111);
DECLARE_MSM_GPIO_PINS(112);
static const unsigned int sdc1_clk_pins[] = { 113 };
static const unsigned int sdc1_cmd_pins[] = { 114 };
static const unsigned int sdc1_data_pins[] = { 115 };
static const unsigned int sdc2_clk_pins[] = { 116 };
static const unsigned int sdc2_cmd_pins[] = { 117 };
static const unsigned int sdc2_data_pins[] = { 118 };
static const unsigned int qdsd_clk_pins[] = { 119 };
static const unsigned int qdsd_cmd_pins[] = { 120 };
static const unsigned int qdsd_data0_pins[] = { 121 };
static const unsigned int qdsd_data1_pins[] = { 122 };
static const unsigned int qdsd_data2_pins[] = { 123 };
static const unsigned int qdsd_data3_pins[] = { 124 };
enum msm8909_functions {
msm_mux_gpio,
msm_mux_adsp_ext,
msm_mux_atest_bbrx0,
msm_mux_atest_bbrx1,
msm_mux_atest_char,
msm_mux_atest_char0,
msm_mux_atest_char1,
msm_mux_atest_char2,
msm_mux_atest_char3,
msm_mux_atest_combodac,
msm_mux_atest_gpsadc0,
msm_mux_atest_gpsadc1,
msm_mux_atest_wlan0,
msm_mux_atest_wlan1,
msm_mux_bimc_dte0,
msm_mux_bimc_dte1,
msm_mux_blsp_i2c1,
msm_mux_blsp_i2c2,
msm_mux_blsp_i2c3,
msm_mux_blsp_i2c4,
msm_mux_blsp_i2c5,
msm_mux_blsp_i2c6,
msm_mux_blsp_spi1,
msm_mux_blsp_spi1_cs1,
msm_mux_blsp_spi1_cs2,
msm_mux_blsp_spi1_cs3,
msm_mux_blsp_spi2,
msm_mux_blsp_spi2_cs1,
msm_mux_blsp_spi2_cs2,
msm_mux_blsp_spi2_cs3,
msm_mux_blsp_spi3,
msm_mux_blsp_spi3_cs1,
msm_mux_blsp_spi3_cs2,
msm_mux_blsp_spi3_cs3,
msm_mux_blsp_spi4,
msm_mux_blsp_spi5,
msm_mux_blsp_spi6,
msm_mux_blsp_uart1,
msm_mux_blsp_uart2,
msm_mux_blsp_uim1,
msm_mux_blsp_uim2,
msm_mux_cam_mclk,
msm_mux_cci_async,
msm_mux_cci_timer0,
msm_mux_cci_timer1,
msm_mux_cci_timer2,
msm_mux_cdc_pdm0,
msm_mux_dbg_out,
msm_mux_dmic0_clk,
msm_mux_dmic0_data,
msm_mux_ebi0_wrcdc,
msm_mux_ebi2_a,
msm_mux_ebi2_lcd,
msm_mux_ext_lpass,
msm_mux_gcc_gp1_clk_a,
msm_mux_gcc_gp1_clk_b,
msm_mux_gcc_gp2_clk_a,
msm_mux_gcc_gp2_clk_b,
msm_mux_gcc_gp3_clk_a,
msm_mux_gcc_gp3_clk_b,
msm_mux_gcc_plltest,
msm_mux_gsm0_tx,
msm_mux_ldo_en,
msm_mux_ldo_update,
msm_mux_m_voc,
msm_mux_mdp_vsync,
msm_mux_modem_tsync,
msm_mux_nav_pps,
msm_mux_nav_tsync,
msm_mux_pa_indicator,
msm_mux_pbs0,
msm_mux_pbs1,
msm_mux_pbs2,
msm_mux_pri_mi2s_data0_a,
msm_mux_pri_mi2s_data0_b,
msm_mux_pri_mi2s_data1_a,
msm_mux_pri_mi2s_data1_b,
msm_mux_pri_mi2s_mclk_a,
msm_mux_pri_mi2s_mclk_b,
msm_mux_pri_mi2s_sck_a,
msm_mux_pri_mi2s_sck_b,
msm_mux_pri_mi2s_ws_a,
msm_mux_pri_mi2s_ws_b,
msm_mux_prng_rosc,
msm_mux_pwr_crypto_enabled_a,
msm_mux_pwr_crypto_enabled_b,
msm_mux_pwr_modem_enabled_a,
msm_mux_pwr_modem_enabled_b,
msm_mux_pwr_nav_enabled_a,
msm_mux_pwr_nav_enabled_b,
msm_mux_qdss_cti_trig_in_a0,
msm_mux_qdss_cti_trig_in_a1,
msm_mux_qdss_cti_trig_in_b0,
msm_mux_qdss_cti_trig_in_b1,
msm_mux_qdss_cti_trig_out_a0,
msm_mux_qdss_cti_trig_out_a1,
msm_mux_qdss_cti_trig_out_b0,
msm_mux_qdss_cti_trig_out_b1,
msm_mux_qdss_traceclk_a,
msm_mux_qdss_tracectl_a,
msm_mux_qdss_tracedata_a,
msm_mux_qdss_tracedata_b,
msm_mux_sd_write,
msm_mux_sec_mi2s,
msm_mux_smb_int,
msm_mux_ssbi0,
msm_mux_ssbi1,
msm_mux_uim1_clk,
msm_mux_uim1_data,
msm_mux_uim1_present,
msm_mux_uim1_reset,
msm_mux_uim2_clk,
msm_mux_uim2_data,
msm_mux_uim2_present,
msm_mux_uim2_reset,
msm_mux_uim3_clk,
msm_mux_uim3_data,
msm_mux_uim3_present,
msm_mux_uim3_reset,
msm_mux_uim_batt,
msm_mux_wcss_bt,
msm_mux_wcss_fm,
msm_mux_wcss_wlan,
msm_mux__,
};
static const char * const adsp_ext_groups[] = { "gpio38" };
static const char * const atest_bbrx0_groups[] = { "gpio37" };
static const char * const atest_bbrx1_groups[] = { "gpio36" };
static const char * const atest_char0_groups[] = { "gpio62" };
static const char * const atest_char1_groups[] = { "gpio61" };
static const char * const atest_char2_groups[] = { "gpio60" };
static const char * const atest_char3_groups[] = { "gpio59" };
static const char * const atest_char_groups[] = { "gpio63" };
static const char * const atest_combodac_groups[] = {
"gpio32", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
"gpio44", "gpio45", "gpio47", "gpio48", "gpio66", "gpio81", "gpio83",
"gpio84", "gpio85", "gpio86", "gpio94", "gpio95", "gpio110"
};
static const char * const atest_gpsadc0_groups[] = { "gpio65" };
static const char * const atest_gpsadc1_groups[] = { "gpio79" };
static const char * const atest_wlan0_groups[] = { "gpio96" };
static const char * const atest_wlan1_groups[] = { "gpio97" };
static const char * const bimc_dte0_groups[] = { "gpio6", "gpio59" };
static const char * const bimc_dte1_groups[] = { "gpio7", "gpio60" };
static const char * const blsp_i2c1_groups[] = { "gpio6", "gpio7" };
static const char * const blsp_i2c2_groups[] = { "gpio111", "gpio112" };
static const char * const blsp_i2c3_groups[] = { "gpio29", "gpio30" };
static const char * const blsp_i2c4_groups[] = { "gpio14", "gpio15" };
static const char * const blsp_i2c5_groups[] = { "gpio18", "gpio19" };
static const char * const blsp_i2c6_groups[] = { "gpio10", "gpio11" };
static const char * const blsp_spi1_cs1_groups[] = { "gpio97" };
static const char * const blsp_spi1_cs2_groups[] = { "gpio37" };
static const char * const blsp_spi1_cs3_groups[] = { "gpio65" };
static const char * const blsp_spi1_groups[] = {
"gpio4", "gpio5", "gpio6", "gpio7"
};
static const char * const blsp_spi2_cs1_groups[] = { "gpio98" };
static const char * const blsp_spi2_cs2_groups[] = { "gpio17" };
static const char * const blsp_spi2_cs3_groups[] = { "gpio5" };
static const char * const blsp_spi2_groups[] = {
"gpio20", "gpio21", "gpio111", "gpio112"
};
static const char * const blsp_spi3_cs1_groups[] = { "gpio95" };
static const char * const blsp_spi3_cs2_groups[] = { "gpio65" };
static const char * const blsp_spi3_cs3_groups[] = { "gpio4" };
static const char * const blsp_spi3_groups[] = {
"gpio0", "gpio1", "gpio2", "gpio3"
};
static const char * const blsp_spi4_groups[] = {
"gpio12", "gpio13", "gpio14", "gpio15"
};
static const char * const blsp_spi5_groups[] = {
"gpio16", "gpio17", "gpio18", "gpio19"
};
static const char * const blsp_spi6_groups[] = {
"gpio8", "gpio9", "gpio10", "gpio11"
};
static const char * const blsp_uart1_groups[] = {
"gpio4", "gpio5", "gpio6", "gpio7"
};
static const char * const blsp_uart2_groups[] = {
"gpio20", "gpio21", "gpio111", "gpio112"
};
static const char * const blsp_uim1_groups[] = { "gpio4", "gpio5" };
static const char * const blsp_uim2_groups[] = { "gpio20", "gpio21" };
static const char * const cam_mclk_groups[] = { "gpio26", "gpio27" };
static const char * const cci_async_groups[] = { "gpio33" };
static const char * const cci_timer0_groups[] = { "gpio31" };
static const char * const cci_timer1_groups[] = { "gpio32" };
static const char * const cci_timer2_groups[] = { "gpio38" };
static const char * const cdc_pdm0_groups[] = {
"gpio59", "gpio60", "gpio61", "gpio62", "gpio63", "gpio64"
};
static const char * const dbg_out_groups[] = { "gpio10" };
static const char * const dmic0_clk_groups[] = { "gpio4" };
static const char * const dmic0_data_groups[] = { "gpio5" };
static const char * const ebi0_wrcdc_groups[] = { "gpio64" };
static const char * const ebi2_a_groups[] = { "gpio99" };
static const char * const ebi2_lcd_groups[] = {
"gpio24", "gpio24", "gpio25", "gpio95"
};
static const char * const ext_lpass_groups[] = { "gpio45" };
static const char * const gcc_gp1_clk_a_groups[] = { "gpio49" };
static const char * const gcc_gp1_clk_b_groups[] = { "gpio14" };
static const char * const gcc_gp2_clk_a_groups[] = { "gpio50" };
static const char * const gcc_gp2_clk_b_groups[] = { "gpio12" };
static const char * const gcc_gp3_clk_a_groups[] = { "gpio51" };
static const char * const gcc_gp3_clk_b_groups[] = { "gpio13" };
static const char * const gcc_plltest_groups[] = { "gpio66", "gpio67" };
static const char * const gpio_groups[] = {
"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
"gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
"gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
"gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
"gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
"gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
"gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
"gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
"gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
"gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
"gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
"gpio111", "gpio112"
};
static const char * const gsm0_tx_groups[] = { "gpio85" };
static const char * const ldo_en_groups[] = { "gpio99" };
static const char * const ldo_update_groups[] = { "gpio98" };
static const char * const m_voc_groups[] = { "gpio8", "gpio95" };
static const char * const mdp_vsync_groups[] = { "gpio24", "gpio25" };
static const char * const modem_tsync_groups[] = { "gpio83" };
static const char * const nav_pps_groups[] = { "gpio83" };
static const char * const nav_tsync_groups[] = { "gpio83" };
static const char * const pa_indicator_groups[] = { "gpio82" };
static const char * const pbs0_groups[] = { "gpio90" };
static const char * const pbs1_groups[] = { "gpio91" };
static const char * const pbs2_groups[] = { "gpio92" };
static const char * const pri_mi2s_data0_a_groups[] = { "gpio62" };
static const char * const pri_mi2s_data0_b_groups[] = { "gpio95" };
static const char * const pri_mi2s_data1_a_groups[] = { "gpio63" };
static const char * const pri_mi2s_data1_b_groups[] = { "gpio96" };
static const char * const pri_mi2s_mclk_a_groups[] = { "gpio59" };
static const char * const pri_mi2s_mclk_b_groups[] = { "gpio98" };
static const char * const pri_mi2s_sck_a_groups[] = { "gpio60" };
static const char * const pri_mi2s_sck_b_groups[] = { "gpio94" };
static const char * const pri_mi2s_ws_a_groups[] = { "gpio61" };
static const char * const pri_mi2s_ws_b_groups[] = { "gpio110" };
static const char * const prng_rosc_groups[] = { "gpio43" };
static const char * const pwr_crypto_enabled_a_groups[] = { "gpio35" };
static const char * const pwr_crypto_enabled_b_groups[] = { "gpio96" };
static const char * const pwr_modem_enabled_a_groups[] = { "gpio28" };
static const char * const pwr_modem_enabled_b_groups[] = { "gpio94" };
static const char * const pwr_nav_enabled_a_groups[] = { "gpio34" };
static const char * const pwr_nav_enabled_b_groups[] = { "gpio95" };
static const char * const qdss_cti_trig_in_a0_groups[] = { "gpio20" };
static const char * const qdss_cti_trig_in_a1_groups[] = { "gpio49" };
static const char * const qdss_cti_trig_in_b0_groups[] = { "gpio21" };
static const char * const qdss_cti_trig_in_b1_groups[] = { "gpio50" };
static const char * const qdss_cti_trig_out_a0_groups[] = { "gpio23" };
static const char * const qdss_cti_trig_out_a1_groups[] = { "gpio52" };
static const char * const qdss_cti_trig_out_b0_groups[] = { "gpio22" };
static const char * const qdss_cti_trig_out_b1_groups[] = { "gpio51" };
static const char * const qdss_traceclk_a_groups[] = { "gpio46" };
static const char * const qdss_tracectl_a_groups[] = { "gpio45" };
static const char * const qdss_tracedata_a_groups[] = {
"gpio8", "gpio9", "gpio10", "gpio39", "gpio40", "gpio41", "gpio42",
"gpio43", "gpio47", "gpio48", "gpio58", "gpio65", "gpio94", "gpio96",
"gpio97"
};
static const char * const qdss_tracedata_b_groups[] = {
"gpio14", "gpio16", "gpio17", "gpio29", "gpio30", "gpio31", "gpio32",
"gpio33", "gpio34", "gpio35", "gpio36", "gpio37", "gpio93"
};
static const char * const sd_write_groups[] = { "gpio99" };
static const char * const sec_mi2s_groups[] = {
"gpio0", "gpio1", "gpio2", "gpio3", "gpio98"
};
static const char * const smb_int_groups[] = { "gpio58" };
static const char * const ssbi0_groups[] = { "gpio88" };
static const char * const ssbi1_groups[] = { "gpio89" };
static const char * const uim1_clk_groups[] = { "gpio54" };
static const char * const uim1_data_groups[] = { "gpio53" };
static const char * const uim1_present_groups[] = { "gpio56" };
static const char * const uim1_reset_groups[] = { "gpio55" };
static const char * const uim2_clk_groups[] = { "gpio50" };
static const char * const uim2_data_groups[] = { "gpio49" };
static const char * const uim2_present_groups[] = { "gpio52" };
static const char * const uim2_reset_groups[] = { "gpio51" };
static const char * const uim3_clk_groups[] = { "gpio23" };
static const char * const uim3_data_groups[] = { "gpio20" };
static const char * const uim3_present_groups[] = { "gpio21" };
static const char * const uim3_reset_groups[] = { "gpio22" };
static const char * const uim_batt_groups[] = { "gpio57" };
static const char * const wcss_bt_groups[] = { "gpio39", "gpio47", "gpio48" };
static const char * const wcss_fm_groups[] = { "gpio45", "gpio46" };
static const char * const wcss_wlan_groups[] = {
"gpio40", "gpio41", "gpio42", "gpio43", "gpio44"
};
static const struct msm_function msm8909_functions[] = {
FUNCTION(adsp_ext),
FUNCTION(atest_bbrx0),
FUNCTION(atest_bbrx1),
FUNCTION(atest_char),
FUNCTION(atest_char0),
FUNCTION(atest_char1),
FUNCTION(atest_char2),
FUNCTION(atest_char3),
FUNCTION(atest_combodac),
FUNCTION(atest_gpsadc0),
FUNCTION(atest_gpsadc1),
FUNCTION(atest_wlan0),
FUNCTION(atest_wlan1),
FUNCTION(bimc_dte0),
FUNCTION(bimc_dte1),
FUNCTION(blsp_i2c1),
FUNCTION(blsp_i2c2),
FUNCTION(blsp_i2c3),
FUNCTION(blsp_i2c4),
FUNCTION(blsp_i2c5),
FUNCTION(blsp_i2c6),
FUNCTION(blsp_spi1),
FUNCTION(blsp_spi1_cs1),
FUNCTION(blsp_spi1_cs2),
FUNCTION(blsp_spi1_cs3),
FUNCTION(blsp_spi2),
FUNCTION(blsp_spi2_cs1),
FUNCTION(blsp_spi2_cs2),
FUNCTION(blsp_spi2_cs3),
FUNCTION(blsp_spi3),
FUNCTION(blsp_spi3_cs1),
FUNCTION(blsp_spi3_cs2),
FUNCTION(blsp_spi3_cs3),
FUNCTION(blsp_spi4),
FUNCTION(blsp_spi5),
FUNCTION(blsp_spi6),
FUNCTION(blsp_uart1),
FUNCTION(blsp_uart2),
FUNCTION(blsp_uim1),
FUNCTION(blsp_uim2),
FUNCTION(cam_mclk),
FUNCTION(cci_async),
FUNCTION(cci_timer0),
FUNCTION(cci_timer1),
FUNCTION(cci_timer2),
FUNCTION(cdc_pdm0),
FUNCTION(dbg_out),
FUNCTION(dmic0_clk),
FUNCTION(dmic0_data),
FUNCTION(ebi0_wrcdc),
FUNCTION(ebi2_a),
FUNCTION(ebi2_lcd),
FUNCTION(ext_lpass),
FUNCTION(gcc_gp1_clk_a),
FUNCTION(gcc_gp1_clk_b),
FUNCTION(gcc_gp2_clk_a),
FUNCTION(gcc_gp2_clk_b),
FUNCTION(gcc_gp3_clk_a),
FUNCTION(gcc_gp3_clk_b),
FUNCTION(gcc_plltest),
FUNCTION(gpio),
FUNCTION(gsm0_tx),
FUNCTION(ldo_en),
FUNCTION(ldo_update),
FUNCTION(m_voc),
FUNCTION(mdp_vsync),
FUNCTION(modem_tsync),
FUNCTION(nav_pps),
FUNCTION(nav_tsync),
FUNCTION(pa_indicator),
FUNCTION(pbs0),
FUNCTION(pbs1),
FUNCTION(pbs2),
FUNCTION(pri_mi2s_data0_a),
FUNCTION(pri_mi2s_data0_b),
FUNCTION(pri_mi2s_data1_a),
FUNCTION(pri_mi2s_data1_b),
FUNCTION(pri_mi2s_mclk_a),
FUNCTION(pri_mi2s_mclk_b),
FUNCTION(pri_mi2s_sck_a),
FUNCTION(pri_mi2s_sck_b),
FUNCTION(pri_mi2s_ws_a),
FUNCTION(pri_mi2s_ws_b),
FUNCTION(prng_rosc),
FUNCTION(pwr_crypto_enabled_a),
FUNCTION(pwr_crypto_enabled_b),
FUNCTION(pwr_modem_enabled_a),
FUNCTION(pwr_modem_enabled_b),
FUNCTION(pwr_nav_enabled_a),
FUNCTION(pwr_nav_enabled_b),
FUNCTION(qdss_cti_trig_in_a0),
FUNCTION(qdss_cti_trig_in_a1),
FUNCTION(qdss_cti_trig_in_b0),
FUNCTION(qdss_cti_trig_in_b1),
FUNCTION(qdss_cti_trig_out_a0),
FUNCTION(qdss_cti_trig_out_a1),
FUNCTION(qdss_cti_trig_out_b0),
FUNCTION(qdss_cti_trig_out_b1),
FUNCTION(qdss_traceclk_a),
FUNCTION(qdss_tracectl_a),
FUNCTION(qdss_tracedata_a),
FUNCTION(qdss_tracedata_b),
FUNCTION(sd_write),
FUNCTION(sec_mi2s),
FUNCTION(smb_int),
FUNCTION(ssbi0),
FUNCTION(ssbi1),
FUNCTION(uim1_clk),
FUNCTION(uim1_data),
FUNCTION(uim1_present),
FUNCTION(uim1_reset),
FUNCTION(uim2_clk),
FUNCTION(uim2_data),
FUNCTION(uim2_present),
FUNCTION(uim2_reset),
FUNCTION(uim3_clk),
FUNCTION(uim3_data),
FUNCTION(uim3_present),
FUNCTION(uim3_reset),
FUNCTION(uim_batt),
FUNCTION(wcss_bt),
FUNCTION(wcss_fm),
FUNCTION(wcss_wlan),
};
static const struct msm_pingroup msm8909_groups[] = {
PINGROUP(0, blsp_spi3, sec_mi2s, _, _, _, _, _, _, _),
PINGROUP(1, blsp_spi3, sec_mi2s, _, _, _, _, _, _, _),
PINGROUP(2, blsp_spi3, sec_mi2s, _, _, _, _, _, _, _),
PINGROUP(3, blsp_spi3, sec_mi2s, _, _, _, _, _, _, _),
PINGROUP(4, blsp_spi1, blsp_uart1, blsp_uim1, blsp_spi3_cs3, dmic0_clk, _, _, _, _),
PINGROUP(5, blsp_spi1, blsp_uart1, blsp_uim1, blsp_spi2_cs3, dmic0_data, _, _, _, _),
PINGROUP(6, blsp_spi1, blsp_uart1, blsp_i2c1, _, _, _, _, _, bimc_dte0),
PINGROUP(7, blsp_spi1, blsp_uart1, blsp_i2c1, _, _, _, _, _, bimc_dte1),
PINGROUP(8, blsp_spi6, m_voc, _, _, _, _, _, qdss_tracedata_a, _),
PINGROUP(9, blsp_spi6, _, _, _, _, _, qdss_tracedata_a, _, _),
PINGROUP(10, blsp_spi6, blsp_i2c6, dbg_out, qdss_tracedata_a, _, _, _, _, _),
PINGROUP(11, blsp_spi6, blsp_i2c6, _, _, _, _, _, _, _),
PINGROUP(12, blsp_spi4, gcc_gp2_clk_b, _, _, _, _, _, _, _),
PINGROUP(13, blsp_spi4, gcc_gp3_clk_b, _, _, _, _, _, _, _),
PINGROUP(14, blsp_spi4, blsp_i2c4, gcc_gp1_clk_b, _, _, _, _, _, qdss_tracedata_b),
PINGROUP(15, blsp_spi4, blsp_i2c4, _, _, _, _, _, _, _),
PINGROUP(16, blsp_spi5, _, _, _, _, _, qdss_tracedata_b, _, _),
PINGROUP(17, blsp_spi5, blsp_spi2_cs2, _, _, _, _, _, qdss_tracedata_b, _),
PINGROUP(18, blsp_spi5, blsp_i2c5, _, _, _, _, _, _, _),
PINGROUP(19, blsp_spi5, blsp_i2c5, _, _, _, _, _, _, _),
PINGROUP(20, uim3_data, blsp_spi2, blsp_uart2, blsp_uim2, _, qdss_cti_trig_in_a0, _, _, _),
PINGROUP(21, uim3_present, blsp_spi2, blsp_uart2, blsp_uim2, _, qdss_cti_trig_in_b0, _, _, _),
PINGROUP(22, uim3_reset, _, qdss_cti_trig_out_b0, _, _, _, _, _, _),
PINGROUP(23, uim3_clk, qdss_cti_trig_out_a0, _, _, _, _, _, _, _),
PINGROUP(24, mdp_vsync, ebi2_lcd, ebi2_lcd, _, _, _, _, _, _),
PINGROUP(25, mdp_vsync, ebi2_lcd, _, _, _, _, _, _, _),
PINGROUP(26, cam_mclk, _, _, _, _, _, _, _, _),
PINGROUP(27, cam_mclk, _, _, _, _, _, _, _, _),
PINGROUP(28, _, pwr_modem_enabled_a, _, _, _, _, _, _, _),
PINGROUP(29, blsp_i2c3, _, _, _, _, _, qdss_tracedata_b, _, _),
PINGROUP(30, blsp_i2c3, _, _, _, _, _, qdss_tracedata_b, _, _),
PINGROUP(31, cci_timer0, _, _, _, _, _, _, qdss_tracedata_b, _),
PINGROUP(32, cci_timer1, _, qdss_tracedata_b, _, atest_combodac, _, _, _, _),
PINGROUP(33, cci_async, qdss_tracedata_b, _, _, _, _, _, _, _),
PINGROUP(34, pwr_nav_enabled_a, qdss_tracedata_b, _, _, _, _, _, _, _),
PINGROUP(35, pwr_crypto_enabled_a, qdss_tracedata_b, _, _, _, _, _, _, _),
PINGROUP(36, qdss_tracedata_b, _, atest_bbrx1, _, _, _, _, _, _),
PINGROUP(37, blsp_spi1_cs2, qdss_tracedata_b, _, atest_bbrx0, _, _, _, _, _),
PINGROUP(38, cci_timer2, adsp_ext, _, atest_combodac, _, _, _, _, _),
PINGROUP(39, wcss_bt, qdss_tracedata_a, _, atest_combodac, _, _, _, _, _),
PINGROUP(40, wcss_wlan, qdss_tracedata_a, _, atest_combodac, _, _, _, _, _),
PINGROUP(41, wcss_wlan, qdss_tracedata_a, _, atest_combodac, _, _, _, _, _),
PINGROUP(42, wcss_wlan, qdss_tracedata_a, _, atest_combodac, _, _, _, _, _),
PINGROUP(43, wcss_wlan, prng_rosc, qdss_tracedata_a, _, atest_combodac, _, _, _, _),
PINGROUP(44, wcss_wlan, _, atest_combodac, _, _, _, _, _, _),
PINGROUP(45, wcss_fm, ext_lpass, qdss_tracectl_a, _, atest_combodac, _, _, _, _),
PINGROUP(46, wcss_fm, qdss_traceclk_a, _, _, _, _, _, _, _),
PINGROUP(47, wcss_bt, qdss_tracedata_a, _, atest_combodac, _, _, _, _, _),
PINGROUP(48, wcss_bt, qdss_tracedata_a, _, atest_combodac, _, _, _, _, _),
PINGROUP(49, uim2_data, gcc_gp1_clk_a, qdss_cti_trig_in_a1, _, _, _, _, _, _),
PINGROUP(50, uim2_clk, gcc_gp2_clk_a, qdss_cti_trig_in_b1, _, _, _, _, _, _),
PINGROUP(51, uim2_reset, gcc_gp3_clk_a, qdss_cti_trig_out_b1, _, _, _, _, _, _),
PINGROUP(52, uim2_present, qdss_cti_trig_out_a1, _, _, _, _, _, _, _),
PINGROUP(53, uim1_data, _, _, _, _, _, _, _, _),
PINGROUP(54, uim1_clk, _, _, _, _, _, _, _, _),
PINGROUP(55, uim1_reset, _, _, _, _, _, _, _, _),
PINGROUP(56, uim1_present, _, _, _, _, _, _, _, _),
PINGROUP(57, uim_batt, _, _, _, _, _, _, _, _),
PINGROUP(58, qdss_tracedata_a, smb_int, _, _, _, _, _, _, _),
PINGROUP(59, cdc_pdm0, pri_mi2s_mclk_a, atest_char3, _, _, _, _, _, bimc_dte0),
PINGROUP(60, cdc_pdm0, pri_mi2s_sck_a, atest_char2, _, _, _, _, _, bimc_dte1),
PINGROUP(61, cdc_pdm0, pri_mi2s_ws_a, atest_char1, _, _, _, _, _, _),
PINGROUP(62, cdc_pdm0, pri_mi2s_data0_a, atest_char0, _, _, _, _, _, _),
PINGROUP(63, cdc_pdm0, pri_mi2s_data1_a, atest_char, _, _, _, _, _, _),
PINGROUP(64, cdc_pdm0, _, _, _, _, _, ebi0_wrcdc, _, _),
PINGROUP(65, blsp_spi3_cs2, blsp_spi1_cs3, qdss_tracedata_a, _, atest_gpsadc0, _, _, _, _),
PINGROUP(66, _, gcc_plltest, _, atest_combodac, _, _, _, _, _),
PINGROUP(67, _, gcc_plltest, _, _, _, _, _, _, _),
PINGROUP(68, _, _, _, _, _, _, _, _, _),
PINGROUP(69, _, _, _, _, _, _, _, _, _),
PINGROUP(70, _, _, _, _, _, _, _, _, _),
PINGROUP(71, _, _, _, _, _, _, _, _, _),
PINGROUP(72, _, _, _, _, _, _, _, _, _),
PINGROUP(73, _, _, _, _, _, _, _, _, _),
PINGROUP(74, _, _, _, _, _, _, _, _, _),
PINGROUP(75, _, _, _, _, _, _, _, _, _),
PINGROUP(76, _, _, _, _, _, _, _, _, _),
PINGROUP(77, _, _, _, _, _, _, _, _, _),
PINGROUP(78, _, _, _, _, _, _, _, _, _),
PINGROUP(79, _, _, atest_gpsadc1, _, _, _, _, _, _),
PINGROUP(80, _, _, _, _, _, _, _, _, _),
PINGROUP(81, _, _, _, atest_combodac, _, _, _, _, _),
PINGROUP(82, _, pa_indicator, _, _, _, _, _, _, _),
PINGROUP(83, _, modem_tsync, nav_tsync, nav_pps, _, atest_combodac, _, _, _),
PINGROUP(84, _, _, atest_combodac, _, _, _, _, _, _),
PINGROUP(85, gsm0_tx, _, _, atest_combodac, _, _, _, _, _),
PINGROUP(86, _, _, atest_combodac, _, _, _, _, _, _),
PINGROUP(87, _, _, _, _, _, _, _, _, _),
PINGROUP(88, _, ssbi0, _, _, _, _, _, _, _),
PINGROUP(89, _, ssbi1, _, _, _, _, _, _, _),
PINGROUP(90, pbs0, _, _, _, _, _, _, _, _),
PINGROUP(91, pbs1, _, _, _, _, _, _, _, _),
PINGROUP(92, pbs2, _, _, _, _, _, _, _, _),
PINGROUP(93, qdss_tracedata_b, _, _, _, _, _, _, _, _),
PINGROUP(94, pri_mi2s_sck_b, pwr_modem_enabled_b, qdss_tracedata_a, _, atest_combodac, _, _, _, _),
PINGROUP(95, blsp_spi3_cs1, pri_mi2s_data0_b, ebi2_lcd, m_voc, pwr_nav_enabled_b, _, atest_combodac, _, _),
PINGROUP(96, pri_mi2s_data1_b, _, pwr_crypto_enabled_b, qdss_tracedata_a, _, atest_wlan0, _, _, _),
PINGROUP(97, blsp_spi1_cs1, qdss_tracedata_a, _, atest_wlan1, _, _, _, _, _),
PINGROUP(98, sec_mi2s, pri_mi2s_mclk_b, blsp_spi2_cs1, ldo_update, _, _, _, _, _),
PINGROUP(99, ebi2_a, sd_write, ldo_en, _, _, _, _, _, _),
PINGROUP(100, _, _, _, _, _, _, _, _, _),
PINGROUP(101, _, _, _, _, _, _, _, _, _),
PINGROUP(102, _, _, _, _, _, _, _, _, _),
PINGROUP(103, _, _, _, _, _, _, _, _, _),
PINGROUP(104, _, _, _, _, _, _, _, _, _),
PINGROUP(105, _, _, _, _, _, _, _, _, _),
PINGROUP(106, _, _, _, _, _, _, _, _, _),
PINGROUP(107, _, _, _, _, _, _, _, _, _),
PINGROUP(108, _, _, _, _, _, _, _, _, _),
PINGROUP(109, _, _, _, _, _, _, _, _, _),
PINGROUP(110, pri_mi2s_ws_b, _, atest_combodac, _, _, _, _, _, _),
PINGROUP(111, blsp_spi2, blsp_uart2, blsp_i2c2, _, _, _, _, _, _),
PINGROUP(112, blsp_spi2, blsp_uart2, blsp_i2c2, _, _, _, _, _, _),
SDC_QDSD_PINGROUP(sdc1_clk, 0x10a000, 13, 6),
SDC_QDSD_PINGROUP(sdc1_cmd, 0x10a000, 11, 3),
SDC_QDSD_PINGROUP(sdc1_data, 0x10a000, 9, 0),
SDC_QDSD_PINGROUP(sdc2_clk, 0x109000, 14, 6),
SDC_QDSD_PINGROUP(sdc2_cmd, 0x109000, 11, 3),
SDC_QDSD_PINGROUP(sdc2_data, 0x109000, 9, 0),
SDC_QDSD_PINGROUP(qdsd_clk, 0x19c000, 3, 0),
SDC_QDSD_PINGROUP(qdsd_cmd, 0x19c000, 8, 5),
SDC_QDSD_PINGROUP(qdsd_data0, 0x19c000, 13, 10),
SDC_QDSD_PINGROUP(qdsd_data1, 0x19c000, 18, 15),
SDC_QDSD_PINGROUP(qdsd_data2, 0x19c000, 23, 20),
SDC_QDSD_PINGROUP(qdsd_data3, 0x19c000, 28, 25),
};
static const struct msm_gpio_wakeirq_map msm8909_mpm_map[] = {
{ 65, 3 }, { 5, 4 }, { 11, 5 }, { 12, 6 }, { 64, 7 }, { 58, 8 },
{ 50, 9 }, { 13, 10 }, { 49, 11 }, { 20, 12 }, { 21, 13 }, { 25, 14 },
{ 46, 15 }, { 45, 16 }, { 28, 17 }, { 44, 18 }, { 31, 19 }, { 43, 20 },
{ 42, 21 }, { 34, 22 }, { 35, 23 }, { 36, 24 }, { 37, 25 }, { 38, 26 },
{ 39, 27 }, { 40, 28 }, { 41, 29 }, { 90, 30 }, { 91, 32 }, { 92, 33 },
{ 94, 34 }, { 95, 35 }, { 96, 36 }, { 97, 37 }, { 98, 38 },
{ 110, 39 }, { 111, 40 }, { 112, 41 }, { 105, 42 }, { 107, 43 },
{ 47, 50 }, { 48, 51 },
};
static const struct msm_pinctrl_soc_data msm8909_pinctrl = {
.pins = msm8909_pins,
.npins = ARRAY_SIZE(msm8909_pins),
.functions = msm8909_functions,
.nfunctions = ARRAY_SIZE(msm8909_functions),
.groups = msm8909_groups,
.ngroups = ARRAY_SIZE(msm8909_groups),
.ngpios = 113,
.wakeirq_map = msm8909_mpm_map,
.nwakeirq_map = ARRAY_SIZE(msm8909_mpm_map),
};
static int msm8909_pinctrl_probe(struct platform_device *pdev)
{
return msm_pinctrl_probe(pdev, &msm8909_pinctrl);
}
static const struct of_device_id msm8909_pinctrl_of_match[] = {
{ .compatible = "qcom,msm8909-tlmm", },
{ },
};
MODULE_DEVICE_TABLE(of, msm8909_pinctrl_of_match);
static struct platform_driver msm8909_pinctrl_driver = {
.driver = {
.name = "msm8909-pinctrl",
.of_match_table = msm8909_pinctrl_of_match,
},
.probe = msm8909_pinctrl_probe,
.remove = msm_pinctrl_remove,
};
static int __init msm8909_pinctrl_init(void)
{
return platform_driver_register(&msm8909_pinctrl_driver);
}
arch_initcall(msm8909_pinctrl_init);
static void __exit msm8909_pinctrl_exit(void)
{
platform_driver_unregister(&msm8909_pinctrl_driver);
}
module_exit(msm8909_pinctrl_exit);
MODULE_DESCRIPTION("Qualcomm MSM8909 TLMM pinctrl driver");
MODULE_LICENSE("GPL");

4
drivers/pinctrl/qcom/pinctrl-msm8916.c
View File

@ -844,8 +844,8 @@ static const struct msm_pingroup msm8916_groups[] = {
PINGROUP(28, pwr_modem_enabled_a, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, atest_combodac),
PINGROUP(29, cci_i2c, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, atest_combodac),
PINGROUP(30, cci_i2c, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b),
PINGROUP(31, cci_timer0, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(32, cci_timer1, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(31, cci_timer0, flash_strobe, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(32, cci_timer1, flash_strobe, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(33, cci_async, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b),
PINGROUP(34, pwr_nav_enabled_a, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b),
PINGROUP(35, pwr_crypto_enabled_a, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b),

1
drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
View File

@ -141,7 +141,6 @@ static const struct lpi_pinctrl_variant_data sc7280_lpi_data = {
.ngroups = ARRAY_SIZE(sc7280_groups),
.functions = sc7280_functions,
.nfunctions = ARRAY_SIZE(sc7280_functions),
.is_clk_optional = true,
};
static const struct of_device_id lpi_pinctrl_of_match[] = {

1544
drivers/pinctrl/qcom/pinctrl-sm6375.c Normal file
View File

File diff suppressed because it is too large Load Diff

2
drivers/pinctrl/qcom/pinctrl-sm8250.c
View File

@ -1316,7 +1316,7 @@ static const struct msm_pingroup sm8250_groups[] = {
static const struct msm_gpio_wakeirq_map sm8250_pdc_map[] = {
{ 0, 79 }, { 1, 84 }, { 2, 80 }, { 3, 82 }, { 4, 107 }, { 7, 43 },
{ 11, 42 }, { 14, 44 }, { 15, 52 }, { 19, 67 }, { 23, 68 }, { 24, 105 },
{ 27, 92 }, { 28, 106 }, { 31, 69 }, { 35, 70 }, { 39, 37 },
{ 27, 92 }, { 28, 106 }, { 31, 69 }, { 35, 70 }, { 39, 73 },
{ 40, 108 }, { 43, 71 }, { 45, 72 }, { 47, 83 }, { 51, 74 }, { 55, 77 },
{ 59, 78 }, { 63, 75 }, { 64, 81 }, { 65, 87 }, { 66, 88 }, { 67, 89 },
{ 68, 54 }, { 70, 85 }, { 77, 46 }, { 80, 90 }, { 81, 91 }, { 83, 97 },

3
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
View File

@ -1159,6 +1159,7 @@ static const struct of_device_id pmic_gpio_of_match[] = {
/* pm8150l has 12 GPIOs with holes on 7 */
{ .compatible = "qcom,pm8150l-gpio", .data = (void *) 12 },
{ .compatible = "qcom,pmc8180c-gpio", .data = (void *) 12 },
{ .compatible = "qcom,pm8226-gpio", .data = (void *) 8 },
{ .compatible = "qcom,pm8350-gpio", .data = (void *) 10 },
{ .compatible = "qcom,pm8350b-gpio", .data = (void *) 8 },
{ .compatible = "qcom,pm8350c-gpio", .data = (void *) 9 },
@ -1175,6 +1176,8 @@ static const struct of_device_id pmic_gpio_of_match[] = {
{ .compatible = "qcom,pmi8998-gpio", .data = (void *) 14 },
{ .compatible = "qcom,pmk8350-gpio", .data = (void *) 4 },
{ .compatible = "qcom,pmm8155au-gpio", .data = (void *) 10 },
/* pmp8074 has 12 GPIOs with holes on 1 and 12 */
{ .compatible = "qcom,pmp8074-gpio", .data = (void *) 12 },
{ .compatible = "qcom,pmr735a-gpio", .data = (void *) 4 },
{ .compatible = "qcom,pmr735b-gpio", .data = (void *) 4 },
/* pms405 has 12 GPIOs with holes on 1, 9, and 10 */

18
drivers/pinctrl/renesas/Kconfig
View File

@ -38,7 +38,9 @@ config PINCTRL_RENESAS
select PINCTRL_PFC_R8A77995 if ARCH_R8A77995
select PINCTRL_PFC_R8A779A0 if ARCH_R8A779A0
select PINCTRL_PFC_R8A779F0 if ARCH_R8A779F0
select PINCTRL_PFC_R8A779G0 if ARCH_R8A779G0
select PINCTRL_RZG2L if ARCH_RZG2L
select PINCTRL_RZV2M if ARCH_R9A09G011
select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203
select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264
select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269
@ -153,6 +155,10 @@ config PINCTRL_PFC_R8A779A0
bool "pin control support for R-Car V3U" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A779G0
bool "pin control support for R-Car V4H" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A7740
bool "pin control support for R-Mobile A1" if COMPILE_TEST
select PINCTRL_SH_PFC_GPIO
@ -237,6 +243,18 @@ config PINCTRL_RZN1
help
This selects pinctrl driver for Renesas RZ/N1 devices.
config PINCTRL_RZV2M
bool "pin control support for RZ/V2M"
depends on OF
depends on ARCH_R9A09G011 || COMPILE_TEST
select GPIOLIB
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select GENERIC_PINCONF
help
This selects GPIO and pinctrl driver for Renesas RZ/V2M
platforms.
config PINCTRL_PFC_SH7203
bool "pin control support for SH7203" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO

2
drivers/pinctrl/renesas/Makefile
View File

@ -31,6 +31,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A77990) += pfc-r8a77990.o
obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o
obj-$(CONFIG_PINCTRL_PFC_R8A779A0) += pfc-r8a779a0.o
obj-$(CONFIG_PINCTRL_PFC_R8A779F0) += pfc-r8a779f0.o
obj-$(CONFIG_PINCTRL_PFC_R8A779G0) += pfc-r8a779g0.o
obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o
obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o
obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o
@ -49,6 +50,7 @@ obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o
obj-$(CONFIG_PINCTRL_RZA2) += pinctrl-rza2.o
obj-$(CONFIG_PINCTRL_RZG2L) += pinctrl-rzg2l.o
obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o
obj-$(CONFIG_PINCTRL_RZV2M) += pinctrl-rzv2m.o
ifeq ($(CONFIG_COMPILE_TEST),y)
CFLAGS_pfc-sh7203.o += -I$(srctree)/arch/sh/include/cpu-sh2a

6
drivers/pinctrl/renesas/core.c
View File

@ -644,6 +644,12 @@ static const struct of_device_id sh_pfc_of_table[] = {
.data = &r8a779f0_pinmux_info,
},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A779G0
{
.compatible = "renesas,pfc-r8a779g0",
.data = &r8a779g0_pinmux_info,
},
#endif
#ifdef CONFIG_PINCTRL_PFC_SH73A0
{
.compatible = "renesas,pfc-sh73a0",

2
drivers/pinctrl/renesas/pfc-r8a779f0.c
View File

@ -1902,7 +1902,6 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
enum ioctrl_regs {
POC0,
POC1,
POC2,
POC3,
TD0SEL1,
};
@ -1910,7 +1909,6 @@ enum ioctrl_regs {
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[POC0] = { 0xe60500a0, },
[POC1] = { 0xe60508a0, },
[POC2] = { 0xe60510a0, },
[POC3] = { 0xe60518a0, },
[TD0SEL1] = { 0xe6050920, },
{ /* sentinel */ },

4262
drivers/pinctrl/renesas/pfc-r8a779g0.c Normal file
View File

File diff suppressed because it is too large Load Diff

2
drivers/pinctrl/renesas/pinctrl-rzg2l.c
View File

@ -527,6 +527,8 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
if (!(cfg & PIN_CFG_IEN))
return -EINVAL;
arg = rzg2l_read_pin_config(pctrl, IEN(port_offset), bit, IEN_MASK);
if (!arg)
return -EINVAL;
break;
case PIN_CONFIG_POWER_SOURCE: {

1119
drivers/pinctrl/renesas/pinctrl-rzv2m.c Normal file
View File

File diff suppressed because it is too large Load Diff

9
drivers/pinctrl/renesas/sh_pfc.h
View File

@ -325,6 +325,7 @@ extern const struct sh_pfc_soc_info r8a77990_pinmux_info;
extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
extern const struct sh_pfc_soc_info r8a779a0_pinmux_info;
extern const struct sh_pfc_soc_info r8a779f0_pinmux_info;
extern const struct sh_pfc_soc_info r8a779g0_pinmux_info;
extern const struct sh_pfc_soc_info sh7203_pinmux_info;
extern const struct sh_pfc_soc_info sh7264_pinmux_info;
extern const struct sh_pfc_soc_info sh7269_pinmux_info;
@ -492,9 +493,13 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
#define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0)
#define PORT_GP_CFG_14(bank, fn, sfx, cfg) \
#define PORT_GP_CFG_13(bank, fn, sfx, cfg) \
PORT_GP_CFG_12(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 12, fn, sfx, cfg)
#define PORT_GP_13(bank, fn, sfx) PORT_GP_CFG_13(bank, fn, sfx, 0)
#define PORT_GP_CFG_14(bank, fn, sfx, cfg) \
PORT_GP_CFG_13(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 13, fn, sfx, cfg)
#define PORT_GP_14(bank, fn, sfx) PORT_GP_CFG_14(bank, fn, sfx, 0)

6
drivers/pinctrl/samsung/pinctrl-exynos.c
View File

@ -27,8 +27,6 @@
#include <linux/soc/samsung/exynos-pmu.h>
#include <linux/soc/samsung/exynos-regs-pmu.h>
#include <dt-bindings/pinctrl/samsung.h>
#include "pinctrl-samsung.h"
#include "pinctrl-exynos.h"
@ -173,7 +171,7 @@ static int exynos_irq_request_resources(struct irq_data *irqd)
con = readl(bank->pctl_base + reg_con);
con &= ~(mask << shift);
con |= EXYNOS_PIN_FUNC_EINT << shift;
con |= EXYNOS_PIN_CON_FUNC_EINT << shift;
writel(con, bank->pctl_base + reg_con);
raw_spin_unlock_irqrestore(&bank->slock, flags);
@ -196,7 +194,7 @@ static void exynos_irq_release_resources(struct irq_data *irqd)
con = readl(bank->pctl_base + reg_con);
con &= ~(mask << shift);
con |= EXYNOS_PIN_FUNC_INPUT << shift;
con |= PIN_CON_FUNC_INPUT << shift;
writel(con, bank->pctl_base + reg_con);
raw_spin_unlock_irqrestore(&bank->slock, flags);

3
drivers/pinctrl/samsung/pinctrl-exynos.h
View File

@ -16,6 +16,9 @@
#ifndef __PINCTRL_SAMSUNG_EXYNOS_H
#define __PINCTRL_SAMSUNG_EXYNOS_H
/* Values for the pin CON register */
#define EXYNOS_PIN_CON_FUNC_EINT 0xf
/* External GPIO and wakeup interrupt related definitions */
#define EXYNOS_GPIO_ECON_OFFSET 0x700
#define EXYNOS_GPIO_EFLTCON_OFFSET 0x800

4
drivers/pinctrl/samsung/pinctrl-samsung.c
View File

@ -26,8 +26,6 @@
#include <linux/of_device.h>
#include <linux/spinlock.h>
#include <dt-bindings/pinctrl/samsung.h>
#include "../core.h"
#include "pinctrl-samsung.h"
@ -614,7 +612,7 @@ static int samsung_gpio_set_direction(struct gpio_chip *gc,
data = readl(reg);
data &= ~(mask << shift);
if (!input)
data |= EXYNOS_PIN_FUNC_OUTPUT << shift;
data |= PIN_CON_FUNC_OUTPUT << shift;
writel(data, reg);
return 0;

8
drivers/pinctrl/samsung/pinctrl-samsung.h
View File

@ -53,6 +53,14 @@ enum pincfg_type {
#define PINCFG_UNPACK_TYPE(cfg) ((cfg) & PINCFG_TYPE_MASK)
#define PINCFG_UNPACK_VALUE(cfg) (((cfg) & PINCFG_VALUE_MASK) >> \
PINCFG_VALUE_SHIFT)
/*
* Values for the pin CON register, choosing pin function.
* The basic set (input and output) are same between: S3C24xx, S3C64xx, S5PV210,
* Exynos ARMv7, Exynos ARMv8, Tesla FSD.
*/
#define PIN_CON_FUNC_INPUT 0x0
#define PIN_CON_FUNC_OUTPUT 0x1
/**
* enum eint_type - possible external interrupt types.
* @EINT_TYPE_NONE: bank does not support external interrupts

8
drivers/pinctrl/sunxi/Kconfig
View File

@ -29,7 +29,6 @@ config PINCTRL_SUN6I_A31
config PINCTRL_SUN6I_A31_R
bool "Support for the Allwinner A31 R-PIO"
default MACH_SUN6I
depends on RESET_CONTROLLER
select PINCTRL_SUNXI
config PINCTRL_SUN8I_A23
@ -55,7 +54,6 @@ config PINCTRL_SUN8I_A83T_R
config PINCTRL_SUN8I_A23_R
bool "Support for the Allwinner A23 and A33 R-PIO"
default MACH_SUN8I
depends on RESET_CONTROLLER
select PINCTRL_SUNXI
config PINCTRL_SUN8I_H3
@ -81,7 +79,11 @@ config PINCTRL_SUN9I_A80
config PINCTRL_SUN9I_A80_R
bool "Support for the Allwinner A80 R-PIO"
default MACH_SUN9I
depends on RESET_CONTROLLER
select PINCTRL_SUNXI
config PINCTRL_SUN20I_D1
bool "Support for the Allwinner D1 PIO"
default MACH_SUN8I || (RISCV && ARCH_SUNXI)
select PINCTRL_SUNXI
config PINCTRL_SUN50I_A64

1
drivers/pinctrl/sunxi/Makefile
View File

@ -20,6 +20,7 @@ obj-$(CONFIG_PINCTRL_SUN8I_A83T_R) += pinctrl-sun8i-a83t-r.o
obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o
obj-$(CONFIG_PINCTRL_SUN8I_H3_R) += pinctrl-sun8i-h3-r.o
obj-$(CONFIG_PINCTRL_SUN8I_V3S) += pinctrl-sun8i-v3s.o
obj-$(CONFIG_PINCTRL_SUN20I_D1) += pinctrl-sun20i-d1.o
obj-$(CONFIG_PINCTRL_SUN50I_H5) += pinctrl-sun50i-h5.o
obj-$(CONFIG_PINCTRL_SUN50I_H6) += pinctrl-sun50i-h6.o
obj-$(CONFIG_PINCTRL_SUN50I_H6_R) += pinctrl-sun50i-h6-r.o

840
drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c Normal file
View File

@ -0,0 +1,840 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Allwinner D1 SoC pinctrl driver.
*
* Copyright (c) 2020 wuyan@allwinnertech.com
* Copyright (c) 2021-2022 Samuel Holland <samuel@sholland.org>
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-sunxi.h"
static const struct sunxi_desc_pin d1_pins[] = {
/* PB */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "pwm3"),
SUNXI_FUNCTION(0x3, "ir"), /* TX */
SUNXI_FUNCTION(0x4, "i2c2"), /* SCK */
SUNXI_FUNCTION(0x5, "spi1"), /* WP */
SUNXI_FUNCTION(0x6, "uart0"), /* TX */
SUNXI_FUNCTION(0x7, "uart2"), /* TX */
SUNXI_FUNCTION(0x8, "spdif"), /* OUT */
SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 0)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "pwm4"),
SUNXI_FUNCTION(0x3, "i2s2_dout"), /* DOUT3 */
SUNXI_FUNCTION(0x4, "i2c2"), /* SDA */
SUNXI_FUNCTION(0x5, "i2s2_din"), /* DIN3 */
SUNXI_FUNCTION(0x6, "uart0"), /* RX */
SUNXI_FUNCTION(0x7, "uart2"), /* RX */
SUNXI_FUNCTION(0x8, "ir"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 1)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
SUNXI_FUNCTION(0x3, "i2s2_dout"), /* DOUT2 */
SUNXI_FUNCTION(0x4, "i2c0"), /* SDA */
SUNXI_FUNCTION(0x5, "i2s2_din"), /* DIN2 */
SUNXI_FUNCTION(0x6, "lcd0"), /* D18 */
SUNXI_FUNCTION(0x7, "uart4"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 2)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
SUNXI_FUNCTION(0x3, "i2s2_dout"), /* DOUT1 */
SUNXI_FUNCTION(0x4, "i2c0"), /* SCK */
SUNXI_FUNCTION(0x5, "i2s2_din"), /* DIN0 */
SUNXI_FUNCTION(0x6, "lcd0"), /* D19 */
SUNXI_FUNCTION(0x7, "uart4"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 3)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
SUNXI_FUNCTION(0x3, "i2s2_dout"), /* DOUT0 */
SUNXI_FUNCTION(0x4, "i2c1"), /* SCK */
SUNXI_FUNCTION(0x5, "i2s2_din"), /* DIN1 */
SUNXI_FUNCTION(0x6, "lcd0"), /* D20 */
SUNXI_FUNCTION(0x7, "uart5"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 4)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
SUNXI_FUNCTION(0x3, "i2s2"), /* BCLK */
SUNXI_FUNCTION(0x4, "i2c1"), /* SDA */
SUNXI_FUNCTION(0x5, "pwm0"),
SUNXI_FUNCTION(0x6, "lcd0"), /* D21 */
SUNXI_FUNCTION(0x7, "uart5"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 5)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
SUNXI_FUNCTION(0x3, "i2s2"), /* LRCK */
SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */
SUNXI_FUNCTION(0x5, "pwm1"),
SUNXI_FUNCTION(0x6, "lcd0"), /* D22 */
SUNXI_FUNCTION(0x7, "uart3"), /* TX */
SUNXI_FUNCTION(0x8, "bist0"), /* BIST_RESULT0 */
SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 6)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
SUNXI_FUNCTION(0x3, "i2s2"), /* MCLK */
SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */
SUNXI_FUNCTION(0x5, "ir"), /* RX */
SUNXI_FUNCTION(0x6, "lcd0"), /* D23 */
SUNXI_FUNCTION(0x7, "uart3"), /* RX */
SUNXI_FUNCTION(0x8, "bist1"), /* BIST_RESULT1 */
SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 7)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "dmic"), /* DATA3 */
SUNXI_FUNCTION(0x3, "pwm5"),
SUNXI_FUNCTION(0x4, "i2c2"), /* SCK */
SUNXI_FUNCTION(0x5, "spi1"), /* HOLD */
SUNXI_FUNCTION(0x6, "uart0"), /* TX */
SUNXI_FUNCTION(0x7, "uart1"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 8)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "dmic"), /* DATA2 */
SUNXI_FUNCTION(0x3, "pwm6"),
SUNXI_FUNCTION(0x4, "i2c2"), /* SDA */
SUNXI_FUNCTION(0x5, "spi1"), /* MISO */
SUNXI_FUNCTION(0x6, "uart0"), /* RX */
SUNXI_FUNCTION(0x7, "uart1"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 9)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "dmic"), /* DATA1 */
SUNXI_FUNCTION(0x3, "pwm7"),
SUNXI_FUNCTION(0x4, "i2c0"), /* SCK */
SUNXI_FUNCTION(0x5, "spi1"), /* MOSI */
SUNXI_FUNCTION(0x6, "clk"), /* FANOUT0 */
SUNXI_FUNCTION(0x7, "uart1"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 10)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "dmic"), /* DATA0 */
SUNXI_FUNCTION(0x3, "pwm2"),
SUNXI_FUNCTION(0x4, "i2c0"), /* SDA */
SUNXI_FUNCTION(0x5, "spi1"), /* CLK */
SUNXI_FUNCTION(0x6, "clk"), /* FANOUT1 */
SUNXI_FUNCTION(0x7, "uart1"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 11)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "dmic"), /* CLK */
SUNXI_FUNCTION(0x3, "pwm0"),
SUNXI_FUNCTION(0x4, "spdif"), /* IN */
SUNXI_FUNCTION(0x5, "spi1"), /* CS0 */
SUNXI_FUNCTION(0x6, "clk"), /* FANOUT2 */
SUNXI_FUNCTION(0x7, "ir"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 12)),
/* PC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* TX */
SUNXI_FUNCTION(0x3, "i2c2"), /* SCK */
SUNXI_FUNCTION(0x4, "ledc"),
SUNXI_FUNCTION_IRQ_BANK(0xe, 1, 0)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* RX */
SUNXI_FUNCTION(0x3, "i2c2"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0xe, 1, 1)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
SUNXI_FUNCTION(0x3, "mmc2"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0xe, 1, 2)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */
SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */
SUNXI_FUNCTION_IRQ_BANK(0xe, 1, 3)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
SUNXI_FUNCTION(0x3, "mmc2"), /* D2 */
SUNXI_FUNCTION(0x4, "boot"), /* SEL0 */
SUNXI_FUNCTION_IRQ_BANK(0xe, 1, 4)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */
SUNXI_FUNCTION(0x4, "boot"), /* SEL1 */
SUNXI_FUNCTION_IRQ_BANK(0xe, 1, 5)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* WP */
SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */
SUNXI_FUNCTION(0x4, "uart3"), /* TX */
SUNXI_FUNCTION(0x5, "i2c3"), /* SCK */
SUNXI_FUNCTION(0x6, "pll"), /* DBG-CLK */
SUNXI_FUNCTION_IRQ_BANK(0xe, 1, 6)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* HOLD */
SUNXI_FUNCTION(0x3, "mmc2"), /* D3 */
SUNXI_FUNCTION(0x4, "uart3"), /* RX */
SUNXI_FUNCTION(0x5, "i2c3"), /* SDA */
SUNXI_FUNCTION(0x6, "tcon"), /* TRIG0 */
SUNXI_FUNCTION_IRQ_BANK(0xe, 1, 7)),
/* PD */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
SUNXI_FUNCTION(0x3, "lvds0"), /* V0P */
SUNXI_FUNCTION(0x4, "dsi"), /* D0P */
SUNXI_FUNCTION(0x5, "i2c0"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 0)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
SUNXI_FUNCTION(0x3, "lvds0"), /* V0N */
SUNXI_FUNCTION(0x4, "dsi"), /* D0N */
SUNXI_FUNCTION(0x5, "uart2"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 1)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
SUNXI_FUNCTION(0x3, "lvds0"), /* V1P */
SUNXI_FUNCTION(0x4, "dsi"), /* D1P */
SUNXI_FUNCTION(0x5, "uart2"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 2)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
SUNXI_FUNCTION(0x3, "lvds0"), /* V1N */
SUNXI_FUNCTION(0x4, "dsi"), /* D1N */
SUNXI_FUNCTION(0x5, "uart2"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 3)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
SUNXI_FUNCTION(0x3, "lvds0"), /* V2P */
SUNXI_FUNCTION(0x4, "dsi"), /* CKP */
SUNXI_FUNCTION(0x5, "uart2"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 4)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
SUNXI_FUNCTION(0x3, "lvds0"), /* V2N */
SUNXI_FUNCTION(0x4, "dsi"), /* CKN */
SUNXI_FUNCTION(0x5, "uart5"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 5)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
SUNXI_FUNCTION(0x3, "lvds0"), /* CKP */
SUNXI_FUNCTION(0x4, "dsi"), /* D2P */
SUNXI_FUNCTION(0x5, "uart5"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 6)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
SUNXI_FUNCTION(0x3, "lvds0"), /* CKN */
SUNXI_FUNCTION(0x4, "dsi"), /* D2N */
SUNXI_FUNCTION(0x5, "uart4"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 7)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
SUNXI_FUNCTION(0x3, "lvds0"), /* V3P */
SUNXI_FUNCTION(0x4, "dsi"), /* D3P */
SUNXI_FUNCTION(0x5, "uart4"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 8)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
SUNXI_FUNCTION(0x3, "lvds0"), /* V3N */
SUNXI_FUNCTION(0x4, "dsi"), /* D3N */
SUNXI_FUNCTION(0x5, "pwm6"),
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 9)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
SUNXI_FUNCTION(0x3, "lvds1"), /* V0P */
SUNXI_FUNCTION(0x4, "spi1"), /* CS0 */
SUNXI_FUNCTION(0x5, "uart3"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 10)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
SUNXI_FUNCTION(0x3, "lvds1"), /* V0N */
SUNXI_FUNCTION(0x4, "spi1"), /* CLK */
SUNXI_FUNCTION(0x5, "uart3"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 11)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
SUNXI_FUNCTION(0x3, "lvds1"), /* V1P */
SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */
SUNXI_FUNCTION(0x5, "i2c0"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 12)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
SUNXI_FUNCTION(0x3, "lvds1"), /* V1N */
SUNXI_FUNCTION(0x4, "spi1"), /* MISO */
SUNXI_FUNCTION(0x5, "uart3"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 13)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
SUNXI_FUNCTION(0x3, "lvds1"), /* V2P */
SUNXI_FUNCTION(0x4, "spi1"), /* HOLD */
SUNXI_FUNCTION(0x5, "uart3"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 14)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
SUNXI_FUNCTION(0x3, "lvds1"), /* V2N */
SUNXI_FUNCTION(0x4, "spi1"), /* WP */
SUNXI_FUNCTION(0x5, "ir"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 15)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
SUNXI_FUNCTION(0x3, "lvds1"), /* CKP */
SUNXI_FUNCTION(0x4, "dmic"), /* DATA3 */
SUNXI_FUNCTION(0x5, "pwm0"),
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 16)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
SUNXI_FUNCTION(0x3, "lvds1"), /* CKN */
SUNXI_FUNCTION(0x4, "dmic"), /* DATA2 */
SUNXI_FUNCTION(0x5, "pwm1"),
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 17)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
SUNXI_FUNCTION(0x3, "lvds1"), /* V3P */
SUNXI_FUNCTION(0x4, "dmic"), /* DATA1 */
SUNXI_FUNCTION(0x5, "pwm2"),
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 18)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
SUNXI_FUNCTION(0x3, "lvds1"), /* V3N */
SUNXI_FUNCTION(0x4, "dmic"), /* DATA0 */
SUNXI_FUNCTION(0x5, "pwm3"),
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 19)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
SUNXI_FUNCTION(0x3, "i2c2"), /* SCK */
SUNXI_FUNCTION(0x4, "dmic"), /* CLK */
SUNXI_FUNCTION(0x5, "pwm4"),
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
SUNXI_FUNCTION(0x3, "i2c2"), /* SDA */
SUNXI_FUNCTION(0x4, "uart1"), /* TX */
SUNXI_FUNCTION(0x5, "pwm5"),
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 21)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spdif"), /* OUT */
SUNXI_FUNCTION(0x3, "ir"), /* RX */
SUNXI_FUNCTION(0x4, "uart1"), /* RX */
SUNXI_FUNCTION(0x5, "pwm7"),
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 22)),
/* PE */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ncsi0"), /* HSYNC */
SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
SUNXI_FUNCTION(0x4, "i2c1"), /* SCK */
SUNXI_FUNCTION(0x5, "lcd0"), /* HSYNC */
SUNXI_FUNCTION(0x8, "emac"), /* RXCTL/CRS_DV */
SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 0)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ncsi0"), /* VSYNC */
SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
SUNXI_FUNCTION(0x4, "i2c1"), /* SDA */
SUNXI_FUNCTION(0x5, "lcd0"), /* VSYNC */
SUNXI_FUNCTION(0x8, "emac"), /* RXD0 */
SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 1)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ncsi0"), /* PCLK */
SUNXI_FUNCTION(0x3, "uart2"), /* TX */
SUNXI_FUNCTION(0x4, "i2c0"), /* SCK */
SUNXI_FUNCTION(0x5, "clk"), /* FANOUT0 */
SUNXI_FUNCTION(0x6, "uart0"), /* TX */
SUNXI_FUNCTION(0x8, "emac"), /* RXD1 */
SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 2)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ncsi0"), /* MCLK */
SUNXI_FUNCTION(0x3, "uart2"), /* RX */
SUNXI_FUNCTION(0x4, "i2c0"), /* SDA */
SUNXI_FUNCTION(0x5, "clk"), /* FANOUT1 */
SUNXI_FUNCTION(0x6, "uart0"), /* RX */
SUNXI_FUNCTION(0x8, "emac"), /* TXCK */
SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 3)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ncsi0"), /* D0 */
SUNXI_FUNCTION(0x3, "uart4"), /* TX */
SUNXI_FUNCTION(0x4, "i2c2"), /* SCK */
SUNXI_FUNCTION(0x5, "clk"), /* FANOUT2 */
SUNXI_FUNCTION(0x6, "d_jtag"), /* MS */
SUNXI_FUNCTION(0x7, "r_jtag"), /* MS */
SUNXI_FUNCTION(0x8, "emac"), /* TXD0 */
SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 4)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ncsi0"), /* D1 */
SUNXI_FUNCTION(0x3, "uart4"), /* RX */
SUNXI_FUNCTION(0x4, "i2c2"), /* SDA */
SUNXI_FUNCTION(0x5, "ledc"),
SUNXI_FUNCTION(0x6, "d_jtag"), /* DI */
SUNXI_FUNCTION(0x7, "r_jtag"), /* DI */
SUNXI_FUNCTION(0x8, "emac"), /* TXD1 */
SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 5)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ncsi0"), /* D2 */
SUNXI_FUNCTION(0x3, "uart5"), /* TX */
SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */
SUNXI_FUNCTION(0x5, "spdif"), /* IN */
SUNXI_FUNCTION(0x6, "d_jtag"), /* DO */
SUNXI_FUNCTION(0x7, "r_jtag"), /* DO */
SUNXI_FUNCTION(0x8, "emac"), /* TXCTL/TXEN */
SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 6)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ncsi0"), /* D3 */
SUNXI_FUNCTION(0x3, "uart5"), /* RX */
SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */
SUNXI_FUNCTION(0x5, "spdif"), /* OUT */
SUNXI_FUNCTION(0x6, "d_jtag"), /* CK */
SUNXI_FUNCTION(0x7, "r_jtag"), /* CK */
SUNXI_FUNCTION(0x8, "emac"), /* CK */
SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 7)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ncsi0"), /* D4 */
SUNXI_FUNCTION(0x3, "uart1"), /* RTS */
SUNXI_FUNCTION(0x4, "pwm2"),
SUNXI_FUNCTION(0x5, "uart3"), /* TX */
SUNXI_FUNCTION(0x6, "jtag"), /* MS */
SUNXI_FUNCTION(0x8, "emac"), /* MDC */
SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 8)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ncsi0"), /* D5 */
SUNXI_FUNCTION(0x3, "uart1"), /* CTS */
SUNXI_FUNCTION(0x4, "pwm3"),
SUNXI_FUNCTION(0x5, "uart3"), /* RX */
SUNXI_FUNCTION(0x6, "jtag"), /* DI */
SUNXI_FUNCTION(0x8, "emac"), /* MDIO */
SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 9)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ncsi0"), /* D6 */
SUNXI_FUNCTION(0x3, "uart1"), /* TX */
SUNXI_FUNCTION(0x4, "pwm4"),
SUNXI_FUNCTION(0x5, "ir"), /* RX */
SUNXI_FUNCTION(0x6, "jtag"), /* DO */
SUNXI_FUNCTION(0x8, "emac"), /* EPHY-25M */
SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 10)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ncsi0"), /* D7 */
SUNXI_FUNCTION(0x3, "uart1"), /* RX */
SUNXI_FUNCTION(0x4, "i2s0_dout"), /* DOUT3 */
SUNXI_FUNCTION(0x5, "i2s0_din"), /* DIN3 */
SUNXI_FUNCTION(0x6, "jtag"), /* CK */
SUNXI_FUNCTION(0x8, "emac"), /* TXD2 */
SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 11)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c2"), /* SCK */
SUNXI_FUNCTION(0x3, "ncsi0"), /* FIELD */
SUNXI_FUNCTION(0x4, "i2s0_dout"), /* DOUT2 */
SUNXI_FUNCTION(0x5, "i2s0_din"), /* DIN2 */
SUNXI_FUNCTION(0x8, "emac"), /* TXD3 */
SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 12)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c2"), /* SDA */
SUNXI_FUNCTION(0x3, "pwm5"),
SUNXI_FUNCTION(0x4, "i2s0_dout"), /* DOUT0 */
SUNXI_FUNCTION(0x5, "i2s0_din"), /* DIN1 */
SUNXI_FUNCTION(0x6, "dmic"), /* DATA3 */
SUNXI_FUNCTION(0x8, "emac"), /* RXD2 */
SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 13)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */
SUNXI_FUNCTION(0x3, "d_jtag"), /* MS */
SUNXI_FUNCTION(0x4, "i2s0_dout"), /* DOUT1 */
SUNXI_FUNCTION(0x5, "i2s0_din"), /* DIN0 */
SUNXI_FUNCTION(0x6, "dmic"), /* DATA2 */
SUNXI_FUNCTION(0x8, "emac"), /* RXD3 */
SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 14)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */
SUNXI_FUNCTION(0x3, "d_jtag"), /* DI */
SUNXI_FUNCTION(0x4, "pwm6"),
SUNXI_FUNCTION(0x5, "i2s0"), /* LRCK */
SUNXI_FUNCTION(0x6, "dmic"), /* DATA1 */
SUNXI_FUNCTION(0x8, "emac"), /* RXCK */
SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 15)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */
SUNXI_FUNCTION(0x3, "d_jtag"), /* DO */
SUNXI_FUNCTION(0x4, "pwm7"),
SUNXI_FUNCTION(0x5, "i2s0"), /* BCLK */
SUNXI_FUNCTION(0x6, "dmic"), /* DATA0 */
SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 16)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */
SUNXI_FUNCTION(0x3, "d_jtag"), /* CK */
SUNXI_FUNCTION(0x4, "ir"), /* TX */
SUNXI_FUNCTION(0x5, "i2s0"), /* MCLK */
SUNXI_FUNCTION(0x6, "dmic"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 17)),
/* PF */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
SUNXI_FUNCTION(0x3, "jtag"), /* MS */
SUNXI_FUNCTION(0x4, "r_jtag"), /* MS */
SUNXI_FUNCTION(0x5, "i2s2_dout"), /* DOUT1 */
SUNXI_FUNCTION(0x6, "i2s2_din"), /* DIN0 */
SUNXI_FUNCTION_IRQ_BANK(0xe, 4, 0)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
SUNXI_FUNCTION(0x3, "jtag"), /* DI */
SUNXI_FUNCTION(0x4, "r_jtag"), /* DI */
SUNXI_FUNCTION(0x5, "i2s2_dout"), /* DOUT0 */
SUNXI_FUNCTION(0x6, "i2s2_din"), /* DIN1 */
SUNXI_FUNCTION_IRQ_BANK(0xe, 4, 1)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
SUNXI_FUNCTION(0x3, "uart0"), /* TX */
SUNXI_FUNCTION(0x4, "i2c0"), /* SCK */
SUNXI_FUNCTION(0x5, "ledc"),
SUNXI_FUNCTION(0x6, "spdif"), /* IN */
SUNXI_FUNCTION_IRQ_BANK(0xe, 4, 2)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
SUNXI_FUNCTION(0x3, "jtag"), /* DO */
SUNXI_FUNCTION(0x4, "r_jtag"), /* DO */
SUNXI_FUNCTION(0x5, "i2s2"), /* BCLK */
SUNXI_FUNCTION_IRQ_BANK(0xe, 4, 3)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
SUNXI_FUNCTION(0x3, "uart0"), /* RX */
SUNXI_FUNCTION(0x4, "i2c0"), /* SDA */
SUNXI_FUNCTION(0x5, "pwm6"),
SUNXI_FUNCTION(0x6, "ir"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 4, 4)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
SUNXI_FUNCTION(0x3, "jtag"), /* CK */
SUNXI_FUNCTION(0x4, "r_jtag"), /* CK */
SUNXI_FUNCTION(0x5, "i2s2"), /* LRCK */
SUNXI_FUNCTION_IRQ_BANK(0xe, 4, 5)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "spdif"), /* OUT */
SUNXI_FUNCTION(0x4, "ir"), /* RX */
SUNXI_FUNCTION(0x5, "i2s2"), /* MCLK */
SUNXI_FUNCTION(0x6, "pwm5"),
SUNXI_FUNCTION_IRQ_BANK(0xe, 4, 6)),
/* PG */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
SUNXI_FUNCTION(0x3, "uart3"), /* TX */
SUNXI_FUNCTION(0x4, "emac"), /* RXCTRL/CRS_DV */
SUNXI_FUNCTION(0x5, "pwm7"),
SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 0)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
SUNXI_FUNCTION(0x3, "uart3"), /* RX */
SUNXI_FUNCTION(0x4, "emac"), /* RXD0 */
SUNXI_FUNCTION(0x5, "pwm6"),
SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 1)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
SUNXI_FUNCTION(0x4, "emac"), /* RXD1 */
SUNXI_FUNCTION(0x5, "uart4"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 2)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
SUNXI_FUNCTION(0x4, "emac"), /* TXCK */
SUNXI_FUNCTION(0x5, "uart4"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 3)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
SUNXI_FUNCTION(0x3, "uart5"), /* TX */
SUNXI_FUNCTION(0x4, "emac"), /* TXD0 */
SUNXI_FUNCTION(0x5, "pwm5"),
SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 4)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
SUNXI_FUNCTION(0x3, "uart5"), /* RX */
SUNXI_FUNCTION(0x4, "emac"), /* TXD1 */
SUNXI_FUNCTION(0x5, "pwm4"),
SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 5)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* TX */
SUNXI_FUNCTION(0x3, "i2c2"), /* SCK */
SUNXI_FUNCTION(0x4, "emac"), /* TXD2 */
SUNXI_FUNCTION(0x5, "pwm1"),
SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 6)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* RX */
SUNXI_FUNCTION(0x3, "i2c2"), /* SDA */
SUNXI_FUNCTION(0x4, "emac"), /* TXD3 */
SUNXI_FUNCTION(0x5, "spdif"), /* IN */
SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 7)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */
SUNXI_FUNCTION(0x4, "emac"), /* RXD2 */
SUNXI_FUNCTION(0x5, "uart3"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 8)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */
SUNXI_FUNCTION(0x4, "emac"), /* RXD3 */
SUNXI_FUNCTION(0x5, "uart3"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 9)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "pwm3"),
SUNXI_FUNCTION(0x3, "i2c3"), /* SCK */
SUNXI_FUNCTION(0x4, "emac"), /* RXCK */
SUNXI_FUNCTION(0x5, "clk"), /* FANOUT0 */
SUNXI_FUNCTION(0x6, "ir"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 10)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s1"), /* MCLK */
SUNXI_FUNCTION(0x3, "i2c3"), /* SDA */
SUNXI_FUNCTION(0x4, "emac"), /* EPHY-25M */
SUNXI_FUNCTION(0x5, "clk"), /* FANOUT1 */
SUNXI_FUNCTION(0x6, "tcon"), /* TRIG0 */
SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 11)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s1"), /* LRCK */
SUNXI_FUNCTION(0x3, "i2c0"), /* SCK */
SUNXI_FUNCTION(0x4, "emac"), /* TXCTL/TXEN */
SUNXI_FUNCTION(0x5, "clk"), /* FANOUT2 */
SUNXI_FUNCTION(0x6, "pwm0"),
SUNXI_FUNCTION(0x7, "uart1"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 12)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s1"), /* BCLK */
SUNXI_FUNCTION(0x3, "i2c0"), /* SDA */
SUNXI_FUNCTION(0x4, "emac"), /* CLKIN/RXER */
SUNXI_FUNCTION(0x5, "pwm2"),
SUNXI_FUNCTION(0x6, "ledc"),
SUNXI_FUNCTION(0x7, "uart1"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 13)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s1_din"), /* DIN0 */
SUNXI_FUNCTION(0x3, "i2c2"), /* SCK */
SUNXI_FUNCTION(0x4, "emac"), /* MDC */
SUNXI_FUNCTION(0x5, "i2s1_dout"), /* DOUT1 */
SUNXI_FUNCTION(0x6, "spi0"), /* WP */
SUNXI_FUNCTION(0x7, "uart1"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 14)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s1_dout"), /* DOUT0 */
SUNXI_FUNCTION(0x3, "i2c2"), /* SDA */
SUNXI_FUNCTION(0x4, "emac"), /* MDIO */
SUNXI_FUNCTION(0x5, "i2s1_din"), /* DIN1 */
SUNXI_FUNCTION(0x6, "spi0"), /* HOLD */
SUNXI_FUNCTION(0x7, "uart1"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 15)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ir"), /* RX */
SUNXI_FUNCTION(0x3, "tcon"), /* TRIG0 */
SUNXI_FUNCTION(0x4, "pwm5"),
SUNXI_FUNCTION(0x5, "clk"), /* FANOUT2 */
SUNXI_FUNCTION(0x6, "spdif"), /* IN */
SUNXI_FUNCTION(0x7, "ledc"),
SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 16)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* TX */
SUNXI_FUNCTION(0x3, "i2c3"), /* SCK */
SUNXI_FUNCTION(0x4, "pwm7"),
SUNXI_FUNCTION(0x5, "clk"), /* FANOUT0 */
SUNXI_FUNCTION(0x6, "ir"), /* TX */
SUNXI_FUNCTION(0x7, "uart0"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 17)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* RX */
SUNXI_FUNCTION(0x3, "i2c3"), /* SDA */
SUNXI_FUNCTION(0x4, "pwm6"),
SUNXI_FUNCTION(0x5, "clk"), /* FANOUT1 */
SUNXI_FUNCTION(0x6, "spdif"), /* OUT */
SUNXI_FUNCTION(0x7, "uart0"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 18)),
};
static const unsigned int d1_irq_bank_map[] = { 1, 2, 3, 4, 5, 6 };
static const struct sunxi_pinctrl_desc d1_pinctrl_data = {
.pins = d1_pins,
.npins = ARRAY_SIZE(d1_pins),
.irq_banks = ARRAY_SIZE(d1_irq_bank_map),
.irq_bank_map = d1_irq_bank_map,
.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_CTL,
};
static int d1_pinctrl_probe(struct platform_device *pdev)
{
unsigned long variant = (unsigned long)of_device_get_match_data(&pdev->dev);
return sunxi_pinctrl_init_with_variant(pdev, &d1_pinctrl_data, variant);
}
static const struct of_device_id d1_pinctrl_match[] = {
{
.compatible = "allwinner,sun20i-d1-pinctrl",
.data = (void *)PINCTRL_SUN20I_D1
},
{}
};
static struct platform_driver d1_pinctrl_driver = {
.probe = d1_pinctrl_probe,
.driver = {
.name = "sun20i-d1-pinctrl",
.of_match_table = d1_pinctrl_match,
},
};
builtin_platform_driver(d1_pinctrl_driver);

1
drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c
View File

@ -82,6 +82,7 @@ static const struct sunxi_pinctrl_desc a100_r_pinctrl_data = {
.npins = ARRAY_SIZE(a100_r_pins),
.pin_base = PL_BASE,
.irq_banks = 1,
.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_CTL,
};
static int a100_r_pinctrl_probe(struct platform_device *pdev)

2
drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
View File

@ -684,7 +684,7 @@ static const struct sunxi_pinctrl_desc a100_pinctrl_data = {
.npins = ARRAY_SIZE(a100_pins),
.irq_banks = 7,
.irq_bank_map = a100_irq_bank_map,
.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_CTL,
};
static int a100_pinctrl_probe(struct platform_device *pdev)

1
drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c
View File

@ -24,7 +24,6 @@
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
#include "pinctrl-sunxi.h"

2
drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c
View File

@ -16,7 +16,6 @@
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/reset.h>
#include "pinctrl-sunxi.h"
@ -107,6 +106,7 @@ static const struct sunxi_pinctrl_desc sun50i_h6_r_pinctrl_data = {
.npins = ARRAY_SIZE(sun50i_h6_r_pins),
.pin_base = PL_BASE,
.irq_banks = 2,
.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
};
static int sun50i_h6_r_pinctrl_probe(struct platform_device *pdev)

1
drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c
View File

@ -12,7 +12,6 @@
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/reset.h>
#include "pinctrl-sunxi.h"

2
drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c
View File

@ -525,7 +525,7 @@ static const struct sunxi_pinctrl_desc h616_pinctrl_data = {
.irq_banks = ARRAY_SIZE(h616_irq_bank_map),
.irq_bank_map = h616_irq_bank_map,
.irq_read_needs_mux = true,
.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_CTL,
};
static int h616_pinctrl_probe(struct platform_device *pdev)

22
drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
View File

@ -17,7 +17,6 @@
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/reset.h>
#include "pinctrl-sunxi.h"
@ -111,26 +110,7 @@ static const struct sunxi_pinctrl_desc sun6i_a31_r_pinctrl_data = {
static int sun6i_a31_r_pinctrl_probe(struct platform_device *pdev)
{
struct reset_control *rstc;
int ret;
rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
if (IS_ERR(rstc)) {
dev_err(&pdev->dev, "Reset controller missing\n");
return PTR_ERR(rstc);
}
ret = reset_control_deassert(rstc);
if (ret)
return ret;
ret = sunxi_pinctrl_init(pdev,
&sun6i_a31_r_pinctrl_data);
if (ret)
reset_control_assert(rstc);
return ret;
return sunxi_pinctrl_init(pdev, &sun6i_a31_r_pinctrl_data);
}
static const struct of_device_id sun6i_a31_r_pinctrl_match[] = {

25
drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c
View File

@ -20,7 +20,6 @@
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/reset.h>
#include "pinctrl-sunxi.h"
@ -98,29 +97,7 @@ static const struct sunxi_pinctrl_desc sun8i_a23_r_pinctrl_data = {
static int sun8i_a23_r_pinctrl_probe(struct platform_device *pdev)
{
struct reset_control *rstc;
int ret;
rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
if (IS_ERR(rstc)) {
ret = PTR_ERR(rstc);
if (ret == -EPROBE_DEFER)
return ret;
dev_err(&pdev->dev, "Reset controller missing err=%d\n", ret);
return ret;
}
ret = reset_control_deassert(rstc);
if (ret)
return ret;
ret = sunxi_pinctrl_init(pdev,
&sun8i_a23_r_pinctrl_data);
if (ret)
reset_control_assert(rstc);
return ret;
return sunxi_pinctrl_init(pdev, &sun8i_a23_r_pinctrl_data);
}
static const struct of_device_id sun8i_a23_r_pinctrl_match[] = {

1
drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c
View File

@ -27,7 +27,6 @@
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
#include "pinctrl-sunxi.h"

1
drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c
View File

@ -14,7 +14,6 @@
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/reset.h>
#include "pinctrl-sunxi.h"

156
drivers/pinctrl/sunxi/pinctrl-sunxi.c
View File

@ -46,6 +46,67 @@ static struct lock_class_key sunxi_pinctrl_irq_request_class;
static struct irq_chip sunxi_pinctrl_edge_irq_chip;
static struct irq_chip sunxi_pinctrl_level_irq_chip;
/*
* The sunXi PIO registers are organized as a series of banks, with registers
* for each bank in the following order:
* - Mux config
* - Data value
* - Drive level
* - Pull direction
*
* Multiple consecutive registers are used for fields wider than one bit.
*
* The following functions calculate the register and the bit offset to access.
* They take a pin number which is relative to the start of the current device.
*/
static void sunxi_mux_reg(const struct sunxi_pinctrl *pctl,
u32 pin, u32 *reg, u32 *shift, u32 *mask)
{
u32 bank = pin / PINS_PER_BANK;
u32 offset = pin % PINS_PER_BANK * MUX_FIELD_WIDTH;
*reg = bank * pctl->bank_mem_size + MUX_REGS_OFFSET +
offset / BITS_PER_TYPE(u32) * sizeof(u32);
*shift = offset % BITS_PER_TYPE(u32);
*mask = (BIT(MUX_FIELD_WIDTH) - 1) << *shift;
}
static void sunxi_data_reg(const struct sunxi_pinctrl *pctl,
u32 pin, u32 *reg, u32 *shift, u32 *mask)
{
u32 bank = pin / PINS_PER_BANK;
u32 offset = pin % PINS_PER_BANK * DATA_FIELD_WIDTH;
*reg = bank * pctl->bank_mem_size + DATA_REGS_OFFSET +
offset / BITS_PER_TYPE(u32) * sizeof(u32);
*shift = offset % BITS_PER_TYPE(u32);
*mask = (BIT(DATA_FIELD_WIDTH) - 1) << *shift;
}
static void sunxi_dlevel_reg(const struct sunxi_pinctrl *pctl,
u32 pin, u32 *reg, u32 *shift, u32 *mask)
{
u32 bank = pin / PINS_PER_BANK;
u32 offset = pin % PINS_PER_BANK * pctl->dlevel_field_width;
*reg = bank * pctl->bank_mem_size + DLEVEL_REGS_OFFSET +
offset / BITS_PER_TYPE(u32) * sizeof(u32);
*shift = offset % BITS_PER_TYPE(u32);
*mask = (BIT(pctl->dlevel_field_width) - 1) << *shift;
}
static void sunxi_pull_reg(const struct sunxi_pinctrl *pctl,
u32 pin, u32 *reg, u32 *shift, u32 *mask)
{
u32 bank = pin / PINS_PER_BANK;
u32 offset = pin % PINS_PER_BANK * PULL_FIELD_WIDTH;
*reg = bank * pctl->bank_mem_size + pctl->pull_regs_offset +
offset / BITS_PER_TYPE(u32) * sizeof(u32);
*shift = offset % BITS_PER_TYPE(u32);
*mask = (BIT(PULL_FIELD_WIDTH) - 1) << *shift;
}
static struct sunxi_pinctrl_group *
sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
{
@ -451,22 +512,19 @@ static const struct pinctrl_ops sunxi_pctrl_ops = {
.get_group_pins = sunxi_pctrl_get_group_pins,
};
static int sunxi_pconf_reg(unsigned pin, enum pin_config_param param,
u32 *offset, u32 *shift, u32 *mask)
static int sunxi_pconf_reg(const struct sunxi_pinctrl *pctl,
u32 pin, enum pin_config_param param,
u32 *reg, u32 *shift, u32 *mask)
{
switch (param) {
case PIN_CONFIG_DRIVE_STRENGTH:
*offset = sunxi_dlevel_reg(pin);
*shift = sunxi_dlevel_offset(pin);
*mask = DLEVEL_PINS_MASK;
sunxi_dlevel_reg(pctl, pin, reg, shift, mask);
break;
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN:
case PIN_CONFIG_BIAS_DISABLE:
*offset = sunxi_pull_reg(pin);
*shift = sunxi_pull_offset(pin);
*mask = PULL_PINS_MASK;
sunxi_pull_reg(pctl, pin, reg, shift, mask);
break;
default:
@ -481,17 +539,17 @@ static int sunxi_pconf_get(struct pinctrl_dev *pctldev, unsigned pin,
{
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param = pinconf_to_config_param(*config);
u32 offset, shift, mask, val;
u32 reg, shift, mask, val;
u16 arg;
int ret;
pin -= pctl->desc->pin_base;
ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask);
ret = sunxi_pconf_reg(pctl, pin, param, &reg, &shift, &mask);
if (ret < 0)
return ret;
val = (readl(pctl->membase + offset) >> shift) & mask;
val = (readl(pctl->membase + reg) & mask) >> shift;
switch (pinconf_to_config_param(*config)) {
case PIN_CONFIG_DRIVE_STRENGTH:
@ -547,16 +605,15 @@ static int sunxi_pconf_set(struct pinctrl_dev *pctldev, unsigned pin,
pin -= pctl->desc->pin_base;
for (i = 0; i < num_configs; i++) {
u32 arg, reg, shift, mask, val;
enum pin_config_param param;
unsigned long flags;
u32 offset, shift, mask, reg;
u32 arg, val;
int ret;
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask);
ret = sunxi_pconf_reg(pctl, pin, param, &reg, &shift, &mask);
if (ret < 0)
return ret;
@ -593,9 +650,8 @@ static int sunxi_pconf_set(struct pinctrl_dev *pctldev, unsigned pin,
}
raw_spin_lock_irqsave(&pctl->lock, flags);
reg = readl(pctl->membase + offset);
reg &= ~(mask << shift);
writel(reg | val << shift, pctl->membase + offset);
writel((readl(pctl->membase + reg) & ~mask) | val << shift,
pctl->membase + reg);
raw_spin_unlock_irqrestore(&pctl->lock, flags);
} /* for each config */
@ -624,7 +680,7 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl,
unsigned pin,
struct regulator *supply)
{
unsigned short bank = pin / PINS_PER_BANK;
unsigned short bank;
unsigned long flags;
u32 val, reg;
int uV;
@ -640,6 +696,9 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl,
if (uV == 0)
return 0;
pin -= pctl->desc->pin_base;
bank = pin / PINS_PER_BANK;
switch (pctl->desc->io_bias_cfg_variant) {
case BIAS_VOLTAGE_GRP_CONFIG:
/*
@ -657,12 +716,20 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl,
else
val = 0xD; /* 3.3V */
pin -= pctl->desc->pin_base;
reg = readl(pctl->membase + sunxi_grp_config_reg(pin));
reg &= ~IO_BIAS_MASK;
writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin));
return 0;
case BIAS_VOLTAGE_PIO_POW_MODE_CTL:
val = uV > 1800000 && uV <= 2500000 ? BIT(bank) : 0;
raw_spin_lock_irqsave(&pctl->lock, flags);
reg = readl(pctl->membase + PIO_POW_MOD_CTL_REG);
reg &= ~BIT(bank);
writel(reg | val, pctl->membase + PIO_POW_MOD_CTL_REG);
raw_spin_unlock_irqrestore(&pctl->lock, flags);
fallthrough;
case BIAS_VOLTAGE_PIO_POW_MODE_SEL:
val = uV <= 1800000 ? 1 : 0;
@ -710,16 +777,16 @@ static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
u8 config)
{
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
u32 reg, shift, mask;
unsigned long flags;
u32 val, mask;
pin -= pctl->desc->pin_base;
sunxi_mux_reg(pctl, pin, &reg, &shift, &mask);
raw_spin_lock_irqsave(&pctl->lock, flags);
pin -= pctl->desc->pin_base;
val = readl(pctl->membase + sunxi_mux_reg(pin));
mask = MUX_PINS_MASK << sunxi_mux_offset(pin);
writel((val & ~mask) | config << sunxi_mux_offset(pin),
pctl->membase + sunxi_mux_reg(pin));
writel((readl(pctl->membase + reg) & ~mask) | config << shift,
pctl->membase + reg);
raw_spin_unlock_irqrestore(&pctl->lock, flags);
}
@ -852,43 +919,43 @@ static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip,
static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
u32 reg = sunxi_data_reg(offset);
u8 index = sunxi_data_offset(offset);
bool set_mux = pctl->desc->irq_read_needs_mux &&
gpiochip_line_is_irq(chip, offset);
u32 pin = offset + chip->base;
u32 val;
u32 reg, shift, mask, val;
sunxi_data_reg(pctl, offset, &reg, &shift, &mask);
if (set_mux)
sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT);
val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;
val = (readl(pctl->membase + reg) & mask) >> shift;
if (set_mux)
sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ);
return !!val;
return val;
}
static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
unsigned offset, int value)
{
struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
u32 reg = sunxi_data_reg(offset);
u8 index = sunxi_data_offset(offset);
u32 reg, shift, mask, val;
unsigned long flags;
u32 regval;
sunxi_data_reg(pctl, offset, &reg, &shift, &mask);
raw_spin_lock_irqsave(&pctl->lock, flags);
regval = readl(pctl->membase + reg);
val = readl(pctl->membase + reg);
if (value)
regval |= BIT(index);
val |= mask;
else
regval &= ~(BIT(index));
val &= ~mask;
writel(regval, pctl->membase + reg);
writel(val, pctl->membase + reg);
raw_spin_unlock_irqrestore(&pctl->lock, flags);
}
@ -1232,11 +1299,11 @@ static int sunxi_pinctrl_build_state(struct platform_device *pdev)
/*
* Find an upper bound for the maximum number of functions: in
* the worst case we have gpio_in, gpio_out, irq and up to four
* the worst case we have gpio_in, gpio_out, irq and up to seven
* special functions per pin, plus one entry for the sentinel.
* We'll reallocate that later anyway.
*/
pctl->functions = kcalloc(4 * pctl->ngroups + 4,
pctl->functions = kcalloc(7 * pctl->ngroups + 4,
sizeof(*pctl->functions),
GFP_KERNEL);
if (!pctl->functions)
@ -1429,6 +1496,15 @@ int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
pctl->dev = &pdev->dev;
pctl->desc = desc;
pctl->variant = variant;
if (pctl->variant >= PINCTRL_SUN20I_D1) {
pctl->bank_mem_size = D1_BANK_MEM_SIZE;
pctl->pull_regs_offset = D1_PULL_REGS_OFFSET;
pctl->dlevel_field_width = D1_DLEVEL_FIELD_WIDTH;
} else {
pctl->bank_mem_size = BANK_MEM_SIZE;
pctl->pull_regs_offset = PULL_REGS_OFFSET;
pctl->dlevel_field_width = DLEVEL_FIELD_WIDTH;
}
pctl->irq_array = devm_kcalloc(&pdev->dev,
IRQ_PER_BANK * pctl->desc->irq_banks,

109
drivers/pinctrl/sunxi/pinctrl-sunxi.h
View File

@ -36,23 +36,19 @@
#define BANK_MEM_SIZE 0x24
#define MUX_REGS_OFFSET 0x0
#define MUX_FIELD_WIDTH 4
#define DATA_REGS_OFFSET 0x10
#define DATA_FIELD_WIDTH 1
#define DLEVEL_REGS_OFFSET 0x14
#define DLEVEL_FIELD_WIDTH 2
#define PULL_REGS_OFFSET 0x1c
#define PULL_FIELD_WIDTH 2
#define D1_BANK_MEM_SIZE 0x30
#define D1_DLEVEL_FIELD_WIDTH 4
#define D1_PULL_REGS_OFFSET 0x24
#define PINS_PER_BANK 32
#define MUX_PINS_PER_REG 8
#define MUX_PINS_BITS 4
#define MUX_PINS_MASK 0x0f
#define DATA_PINS_PER_REG 32
#define DATA_PINS_BITS 1
#define DATA_PINS_MASK 0x01
#define DLEVEL_PINS_PER_REG 16
#define DLEVEL_PINS_BITS 2
#define DLEVEL_PINS_MASK 0x03
#define PULL_PINS_PER_REG 16
#define PULL_PINS_BITS 2
#define PULL_PINS_MASK 0x03
#define IRQ_PER_BANK 32
@ -96,8 +92,11 @@
#define PINCTRL_SUN8I_R40 BIT(8)
#define PINCTRL_SUN8I_V3 BIT(9)
#define PINCTRL_SUN8I_V3S BIT(10)
/* Variants below here have an updated register layout. */
#define PINCTRL_SUN20I_D1 BIT(11)
#define PIO_POW_MOD_SEL_REG 0x340
#define PIO_POW_MOD_CTL_REG 0x344
enum sunxi_desc_bias_voltage {
BIAS_VOLTAGE_NONE,
@ -111,6 +110,12 @@ enum sunxi_desc_bias_voltage {
* register, as seen on H6 SoC, for example.
*/
BIAS_VOLTAGE_PIO_POW_MODE_SEL,
/*
* Bias voltage is set through PIO_POW_MOD_SEL_REG
* and PIO_POW_MOD_CTL_REG register, as seen on
* A100 and D1 SoC, for example.
*/
BIAS_VOLTAGE_PIO_POW_MODE_CTL,
};
struct sunxi_desc_function {
@ -170,6 +175,9 @@ struct sunxi_pinctrl {
raw_spinlock_t lock;
struct pinctrl_dev *pctl_dev;
unsigned long variant;
u32 bank_mem_size;
u32 pull_regs_offset;
u32 dlevel_field_width;
};
#define SUNXI_PIN(_pin, ...) \
@ -215,83 +223,6 @@ struct sunxi_pinctrl {
.irqnum = _irq, \
}
/*
* The sunXi PIO registers are organized as is:
* 0x00 - 0x0c Muxing values.
* 8 pins per register, each pin having a 4bits value
* 0x10 Pin values
* 32 bits per register, each pin corresponding to one bit
* 0x14 - 0x18 Drive level
* 16 pins per register, each pin having a 2bits value
* 0x1c - 0x20 Pull-Up values
* 16 pins per register, each pin having a 2bits value
*
* This is for the first bank. Each bank will have the same layout,
* with an offset being a multiple of 0x24.
*
* The following functions calculate from the pin number the register
* and the bit offset that we should access.
*/
static inline u32 sunxi_mux_reg(u16 pin)
{
u8 bank = pin / PINS_PER_BANK;
u32 offset = bank * BANK_MEM_SIZE;
offset += MUX_REGS_OFFSET;
offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04;
return round_down(offset, 4);
}
static inline u32 sunxi_mux_offset(u16 pin)
{
u32 pin_num = pin % MUX_PINS_PER_REG;
return pin_num * MUX_PINS_BITS;
}
static inline u32 sunxi_data_reg(u16 pin)
{
u8 bank = pin / PINS_PER_BANK;
u32 offset = bank * BANK_MEM_SIZE;
offset += DATA_REGS_OFFSET;
offset += pin % PINS_PER_BANK / DATA_PINS_PER_REG * 0x04;
return round_down(offset, 4);
}
static inline u32 sunxi_data_offset(u16 pin)
{
u32 pin_num = pin % DATA_PINS_PER_REG;
return pin_num * DATA_PINS_BITS;
}
static inline u32 sunxi_dlevel_reg(u16 pin)
{
u8 bank = pin / PINS_PER_BANK;
u32 offset = bank * BANK_MEM_SIZE;
offset += DLEVEL_REGS_OFFSET;
offset += pin % PINS_PER_BANK / DLEVEL_PINS_PER_REG * 0x04;
return round_down(offset, 4);
}
static inline u32 sunxi_dlevel_offset(u16 pin)
{
u32 pin_num = pin % DLEVEL_PINS_PER_REG;
return pin_num * DLEVEL_PINS_BITS;
}
static inline u32 sunxi_pull_reg(u16 pin)
{
u8 bank = pin / PINS_PER_BANK;
u32 offset = bank * BANK_MEM_SIZE;
offset += PULL_REGS_OFFSET;
offset += pin % PINS_PER_BANK / PULL_PINS_PER_REG * 0x04;
return round_down(offset, 4);
}
static inline u32 sunxi_pull_offset(u16 pin)
{
u32 pin_num = pin % PULL_PINS_PER_REG;
return pin_num * PULL_PINS_BITS;
}
static inline u32 sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc *desc, u8 bank)
{
if (!desc->irq_bank_map)

2
include/dt-bindings/pinctrl/r7s9210-pinctrl.h
View File

@ -42,6 +42,6 @@
/*
* Convert a port and pin label to its global pin index
*/
#define RZA2_PIN(port, pin) ((port) * RZA2_PINS_PER_PORT + (pin))
#define RZA2_PIN(port, pin) ((port) * RZA2_PINS_PER_PORT + (pin))
#endif /* __DT_BINDINGS_PINCTRL_RENESAS_RZA2_H */

2
include/dt-bindings/pinctrl/rzg2l-pinctrl.h
View File

@ -18,6 +18,6 @@
#define RZG2L_PORT_PINMUX(b, p, f) ((b) * RZG2L_PINS_PER_PORT + (p) | ((f) << 16))
/* Convert a port and pin label to its global pin index */
#define RZG2L_GPIO(port, pin) ((port) * RZG2L_PINS_PER_PORT + (pin))
#define RZG2L_GPIO(port, pin) ((port) * RZG2L_PINS_PER_PORT + (pin))
#endif /* __DT_BINDINGS_RZG2L_PINCTRL_H */

23
include/dt-bindings/pinctrl/rzv2m-pinctrl.h Normal file
View File

@ -0,0 +1,23 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* This header provides constants for Renesas RZ/V2M pinctrl bindings.
*
* Copyright (C) 2022 Renesas Electronics Corp.
*
*/
#ifndef __DT_BINDINGS_RZV2M_PINCTRL_H
#define __DT_BINDINGS_RZV2M_PINCTRL_H
#define RZV2M_PINS_PER_PORT 16
/*
* Create the pin index from its bank and position numbers and store in
* the upper 16 bits the alternate function identifier
*/
#define RZV2M_PORT_PINMUX(b, p, f) ((b) * RZV2M_PINS_PER_PORT + (p) | ((f) << 16))
/* Convert a port and pin label to its global pin index */
#define RZV2M_GPIO(port, pin) ((port) * RZV2M_PINS_PER_PORT + (pin))
#endif /* __DT_BINDINGS_RZV2M_PINCTRL_H */

5
include/linux/firmware/xlnx-zynqmp.h
View File

@ -369,6 +369,11 @@ enum pm_pinctrl_drive_strength {
PM_PINCTRL_DRIVE_STRENGTH_12MA = 3,
};
enum pm_pinctrl_tri_state {
PM_PINCTRL_TRI_STATE_DISABLE = 0,
PM_PINCTRL_TRI_STATE_ENABLE = 1,
};
enum zynqmp_pm_shutdown_type {
ZYNQMP_PM_SHUTDOWN_TYPE_SHUTDOWN = 0,
ZYNQMP_PM_SHUTDOWN_TYPE_RESET = 1,

20
include/linux/pinctrl/pinctrl.h
View File

@ -26,6 +26,26 @@ struct pin_config_item;
struct gpio_chip;
struct device_node;
/**
* struct pingroup - provides information on pingroup
* @name: a name for pingroup
* @pins: an array of pins in the pingroup
* @npins: number of pins in the pingroup
*/
struct pingroup {
const char *name;
const unsigned int *pins;
size_t npins;
};
/* Convenience macro to define a single named or anonymous pingroup */
#define PINCTRL_PINGROUP(_name, _pins, _npins) \
(struct pingroup){ \
.name = _name, \
.pins = _pins, \
.npins = _npins, \
}
/**
* struct pinctrl_pin_desc - boards/machines provide information on their
* pins, pads or other muxable units in this struct