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drm/i915: Make IS_GEN macros only take dev_priv

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Saves 1416 bytes of .rodata strings.

v2: Add parantheses around dev_priv. (Ville Syrjala)

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Jani Nikula <jani.nikula@linux.intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1476352990-2504-1-git-send-email-tvrtko.ursulin@linux.intel.com
This commit is contained in:
Tvrtko Ursulin 2016-10-13 11:03:10 +01:00
parent 55b8f2a76d
commit 5db9401983
21 changed files with 126 additions and 124 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/i915/i915_debugfs.c
View File

@ -4558,7 +4558,7 @@ static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
else if (IS_VALLEYVIEW(dev_priv)) else if (IS_VALLEYVIEW(dev_priv))
num_levels = 1; num_levels = 1;
else else
num_levels = ilk_wm_max_level(dev) + 1; num_levels = ilk_wm_max_level(dev_priv) + 1;
drm_modeset_lock_all(dev); drm_modeset_lock_all(dev);
@ -4674,7 +4674,7 @@ static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
else if (IS_VALLEYVIEW(dev_priv)) else if (IS_VALLEYVIEW(dev_priv))
num_levels = 1; num_levels = 1;
else else
num_levels = ilk_wm_max_level(dev) + 1; num_levels = ilk_wm_max_level(dev_priv) + 1;
if (len >= sizeof(tmp)) if (len >= sizeof(tmp))
return -EINVAL; return -EINVAL;

6
drivers/gpu/drm/i915/i915_drv.c
View File

@ -174,7 +174,7 @@ static void intel_detect_pch(struct drm_device *dev)
if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_IBX; dev_priv->pch_type = PCH_IBX;
DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
WARN_ON(!IS_GEN5(dev)); WARN_ON(!IS_GEN5(dev_priv));
} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_CPT; dev_priv->pch_type = PCH_CPT;
DRM_DEBUG_KMS("Found CougarPoint PCH\n"); DRM_DEBUG_KMS("Found CougarPoint PCH\n");
@ -860,7 +860,7 @@ static int i915_mmio_setup(struct drm_device *dev)
int mmio_bar; int mmio_bar;
int mmio_size; int mmio_size;
mmio_bar = IS_GEN2(dev) ? 1 : 0; mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
/* /*
* Before gen4, the registers and the GTT are behind different BARs. * Before gen4, the registers and the GTT are behind different BARs.
* However, from gen4 onwards, the registers and the GTT are shared * However, from gen4 onwards, the registers and the GTT are shared
@ -1013,7 +1013,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
pci_set_master(pdev); pci_set_master(pdev);
/* overlay on gen2 is broken and can't address above 1G */ /* overlay on gen2 is broken and can't address above 1G */
if (IS_GEN2(dev)) { if (IS_GEN2(dev_priv)) {
ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30)); ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
if (ret) { if (ret) {
DRM_ERROR("failed to set DMA mask\n"); DRM_ERROR("failed to set DMA mask\n");

16
drivers/gpu/drm/i915/i915_drv.h
View File

@ -2738,14 +2738,14 @@ struct drm_i915_cmd_table {
* have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
* chips, etc.). * chips, etc.).
*/ */
#define IS_GEN2(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(1))) #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
#define IS_GEN3(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(2))) #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
#define IS_GEN4(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(3))) #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
#define IS_GEN5(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(4))) #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
#define IS_GEN6(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(5))) #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
#define IS_GEN7(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(6))) #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
#define IS_GEN8(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(7))) #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
#define IS_GEN9(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(8))) #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
#define ENGINE_MASK(id) BIT(id) #define ENGINE_MASK(id) BIT(id)
#define RENDER_RING ENGINE_MASK(RCS) #define RENDER_RING ENGINE_MASK(RCS)

8
drivers/gpu/drm/i915/i915_gem.c
View File

@ -4375,15 +4375,15 @@ void i915_gem_init_swizzling(struct drm_device *dev)
I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
DISP_TILE_SURFACE_SWIZZLING); DISP_TILE_SURFACE_SWIZZLING);
if (IS_GEN5(dev)) if (IS_GEN5(dev_priv))
return; return;
I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
if (IS_GEN6(dev)) if (IS_GEN6(dev_priv))
I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
else if (IS_GEN7(dev)) else if (IS_GEN7(dev_priv))
I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
else if (IS_GEN8(dev)) else if (IS_GEN8(dev_priv))
I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
else else
BUG(); BUG();

4
drivers/gpu/drm/i915/i915_gem_execbuffer.c
View File

@ -572,7 +572,7 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
struct drm_i915_gem_relocation_entry *reloc, struct drm_i915_gem_relocation_entry *reloc,
struct reloc_cache *cache) struct reloc_cache *cache)
{ {
struct drm_device *dev = obj->base.dev; struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
struct drm_gem_object *target_obj; struct drm_gem_object *target_obj;
struct drm_i915_gem_object *target_i915_obj; struct drm_i915_gem_object *target_i915_obj;
struct i915_vma *target_vma; struct i915_vma *target_vma;
@ -591,7 +591,7 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
/* Sandybridge PPGTT errata: We need a global gtt mapping for MI and /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
* pipe_control writes because the gpu doesn't properly redirect them * pipe_control writes because the gpu doesn't properly redirect them
* through the ppgtt for non_secure batchbuffers. */ * through the ppgtt for non_secure batchbuffers. */
if (unlikely(IS_GEN6(dev) && if (unlikely(IS_GEN6(dev_priv) &&
reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION)) { reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION)) {
ret = i915_vma_bind(target_vma, target_i915_obj->cache_level, ret = i915_vma_bind(target_vma, target_i915_obj->cache_level,
PIN_GLOBAL); PIN_GLOBAL);

9
drivers/gpu/drm/i915/i915_gem_fence.c
View File

@ -504,19 +504,20 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
swizzle_y = I915_BIT_6_SWIZZLE_NONE; swizzle_y = I915_BIT_6_SWIZZLE_NONE;
} }
} }
} else if (IS_GEN5(dev)) { } else if (IS_GEN5(dev_priv)) {
/* On Ironlake whatever DRAM config, GPU always do /* On Ironlake whatever DRAM config, GPU always do
* same swizzling setup. * same swizzling setup.
*/ */
swizzle_x = I915_BIT_6_SWIZZLE_9_10; swizzle_x = I915_BIT_6_SWIZZLE_9_10;
swizzle_y = I915_BIT_6_SWIZZLE_9; swizzle_y = I915_BIT_6_SWIZZLE_9;
} else if (IS_GEN2(dev)) { } else if (IS_GEN2(dev_priv)) {
/* As far as we know, the 865 doesn't have these bit 6 /* As far as we know, the 865 doesn't have these bit 6
* swizzling issues. * swizzling issues.
*/ */
swizzle_x = I915_BIT_6_SWIZZLE_NONE; swizzle_x = I915_BIT_6_SWIZZLE_NONE;
swizzle_y = I915_BIT_6_SWIZZLE_NONE; swizzle_y = I915_BIT_6_SWIZZLE_NONE;
} else if (IS_MOBILE(dev) || (IS_GEN3(dev) && !IS_G33(dev))) { } else if (IS_MOBILE(dev_priv) || (IS_GEN3(dev_priv) &&
!IS_G33(dev_priv))) {
uint32_t dcc; uint32_t dcc;
/* On 9xx chipsets, channel interleave by the CPU is /* On 9xx chipsets, channel interleave by the CPU is
@ -554,7 +555,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
} }
/* check for L-shaped memory aka modified enhanced addressing */ /* check for L-shaped memory aka modified enhanced addressing */
if (IS_GEN4(dev) && if (IS_GEN4(dev_priv) &&
!(I915_READ(DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) { !(I915_READ(DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) {
swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;

10
drivers/gpu/drm/i915/i915_gem_gtt.c
View File

@ -2060,11 +2060,11 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
int ret; int ret;
ppgtt->base.pte_encode = ggtt->base.pte_encode; ppgtt->base.pte_encode = ggtt->base.pte_encode;
if (intel_vgpu_active(dev_priv) || IS_GEN6(dev)) if (intel_vgpu_active(dev_priv) || IS_GEN6(dev_priv))
ppgtt->switch_mm = gen6_mm_switch; ppgtt->switch_mm = gen6_mm_switch;
else if (IS_HASWELL(dev_priv)) else if (IS_HASWELL(dev_priv))
ppgtt->switch_mm = hsw_mm_switch; ppgtt->switch_mm = hsw_mm_switch;
else if (IS_GEN7(dev)) else if (IS_GEN7(dev_priv))
ppgtt->switch_mm = gen7_mm_switch; ppgtt->switch_mm = gen7_mm_switch;
else else
BUG(); BUG();
@ -2161,6 +2161,8 @@ static int i915_ppgtt_init(struct i915_hw_ppgtt *ppgtt,
int i915_ppgtt_init_hw(struct drm_device *dev) int i915_ppgtt_init_hw(struct drm_device *dev)
{ {
struct drm_i915_private *dev_priv = to_i915(dev);
gtt_write_workarounds(dev); gtt_write_workarounds(dev);
/* In the case of execlists, PPGTT is enabled by the context descriptor /* In the case of execlists, PPGTT is enabled by the context descriptor
@ -2172,9 +2174,9 @@ int i915_ppgtt_init_hw(struct drm_device *dev)
if (!USES_PPGTT(dev)) if (!USES_PPGTT(dev))
return 0; return 0;
if (IS_GEN6(dev)) if (IS_GEN6(dev_priv))
gen6_ppgtt_enable(dev); gen6_ppgtt_enable(dev);
else if (IS_GEN7(dev)) else if (IS_GEN7(dev_priv))
gen7_ppgtt_enable(dev); gen7_ppgtt_enable(dev);
else if (INTEL_INFO(dev)->gen >= 8) else if (INTEL_INFO(dev)->gen >= 8)
gen8_ppgtt_enable(dev); gen8_ppgtt_enable(dev);

4
drivers/gpu/drm/i915/i915_gem_stolen.c
View File

@ -215,7 +215,7 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev)
u64 ggtt_start, ggtt_end; u64 ggtt_start, ggtt_end;
ggtt_start = I915_READ(PGTBL_CTL); ggtt_start = I915_READ(PGTBL_CTL);
if (IS_GEN4(dev)) if (IS_GEN4(dev_priv))
ggtt_start = (ggtt_start & PGTBL_ADDRESS_LO_MASK) | ggtt_start = (ggtt_start & PGTBL_ADDRESS_LO_MASK) |
(ggtt_start & PGTBL_ADDRESS_HI_MASK) << 28; (ggtt_start & PGTBL_ADDRESS_HI_MASK) << 28;
else else
@ -271,7 +271,7 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev)
* GEN3 firmware likes to smash pci bridges into the stolen * GEN3 firmware likes to smash pci bridges into the stolen
* range. Apparently this works. * range. Apparently this works.
*/ */
if (r == NULL && !IS_GEN3(dev)) { if (r == NULL && !IS_GEN3(dev_priv)) {
DRM_ERROR("conflict detected with stolen region: [0x%08x - 0x%08x]\n", DRM_ERROR("conflict detected with stolen region: [0x%08x - 0x%08x]\n",
base, base + (uint32_t)ggtt->stolen_size); base, base + (uint32_t)ggtt->stolen_size);
base = 0; base = 0;

4
drivers/gpu/drm/i915/i915_gem_tiling.c
View File

@ -72,7 +72,7 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
if (tiling_mode > I915_TILING_LAST) if (tiling_mode > I915_TILING_LAST)
return false; return false;
if (IS_GEN2(dev) || if (IS_GEN2(dev_priv) ||
(tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev_priv))) (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev_priv)))
tile_width = 128; tile_width = 128;
else else
@ -91,7 +91,7 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
if (stride > 8192) if (stride > 8192)
return false; return false;
if (IS_GEN3(dev)) { if (IS_GEN3(dev_priv)) {
if (size > I830_FENCE_MAX_SIZE_VAL << 20) if (size > I830_FENCE_MAX_SIZE_VAL << 20)
return false; return false;
} else { } else {

10
drivers/gpu/drm/i915/i915_gpu_error.c
View File

@ -610,7 +610,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
} }
if (IS_GEN7(dev)) if (IS_GEN7(dev_priv))
err_printf(m, "ERR_INT: 0x%08x\n", error->err_int); err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
for (i = 0; i < ARRAY_SIZE(error->engine); i++) { for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
@ -1430,7 +1430,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
error->forcewake = I915_READ_FW(FORCEWAKE_VLV); error->forcewake = I915_READ_FW(FORCEWAKE_VLV);
} }
if (IS_GEN7(dev)) if (IS_GEN7(dev_priv))
error->err_int = I915_READ(GEN7_ERR_INT); error->err_int = I915_READ(GEN7_ERR_INT);
if (INTEL_INFO(dev)->gen >= 8) { if (INTEL_INFO(dev)->gen >= 8) {
@ -1438,7 +1438,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1); error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
} }
if (IS_GEN6(dev)) { if (IS_GEN6(dev_priv)) {
error->forcewake = I915_READ_FW(FORCEWAKE); error->forcewake = I915_READ_FW(FORCEWAKE);
error->gab_ctl = I915_READ(GAB_CTL); error->gab_ctl = I915_READ(GAB_CTL);
error->gfx_mode = I915_READ(GFX_MODE); error->gfx_mode = I915_READ(GFX_MODE);
@ -1455,7 +1455,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
} }
/* 3: Feature specific registers */ /* 3: Feature specific registers */
if (IS_GEN6(dev) || IS_GEN7(dev)) { if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
error->gam_ecochk = I915_READ(GAM_ECOCHK); error->gam_ecochk = I915_READ(GAM_ECOCHK);
error->gac_eco = I915_READ(GAC_ECO_BITS); error->gac_eco = I915_READ(GAC_ECO_BITS);
} }
@ -1471,7 +1471,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
} else if (HAS_PCH_SPLIT(dev_priv)) { } else if (HAS_PCH_SPLIT(dev_priv)) {
error->ier = I915_READ(DEIER); error->ier = I915_READ(DEIER);
error->gtier[0] = I915_READ(GTIER); error->gtier[0] = I915_READ(GTIER);
} else if (IS_GEN2(dev)) { } else if (IS_GEN2(dev_priv)) {
error->ier = I915_READ16(IER); error->ier = I915_READ16(IER);
} else if (!IS_VALLEYVIEW(dev_priv)) { } else if (!IS_VALLEYVIEW(dev_priv)) {
error->ier = I915_READ(IER); error->ier = I915_READ(IER);

4
drivers/gpu/drm/i915/i915_irq.c
View File

@ -3330,7 +3330,7 @@ static void ironlake_irq_reset(struct drm_device *dev)
I915_WRITE(HWSTAM, 0xffffffff); I915_WRITE(HWSTAM, 0xffffffff);
GEN5_IRQ_RESET(DE); GEN5_IRQ_RESET(DE);
if (IS_GEN7(dev)) if (IS_GEN7(dev_priv))
I915_WRITE(GEN7_ERR_INT, 0xffffffff); I915_WRITE(GEN7_ERR_INT, 0xffffffff);
gen5_gt_irq_reset(dev); gen5_gt_irq_reset(dev);
@ -3596,7 +3596,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
} }
gt_irqs |= GT_RENDER_USER_INTERRUPT; gt_irqs |= GT_RENDER_USER_INTERRUPT;
if (IS_GEN5(dev)) { if (IS_GEN5(dev_priv)) {
gt_irqs |= ILK_BSD_USER_INTERRUPT; gt_irqs |= ILK_BSD_USER_INTERRUPT;
} else { } else {
gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;

4
drivers/gpu/drm/i915/i915_suspend.c
View File

@ -70,7 +70,7 @@ int i915_save_state(struct drm_device *dev)
i915_save_display(dev); i915_save_display(dev);
if (IS_GEN4(dev)) if (IS_GEN4(dev_priv))
pci_read_config_word(pdev, GCDGMBUS, pci_read_config_word(pdev, GCDGMBUS,
&dev_priv->regfile.saveGCDGMBUS); &dev_priv->regfile.saveGCDGMBUS);
@ -116,7 +116,7 @@ int i915_restore_state(struct drm_device *dev)
i915_gem_restore_fences(dev); i915_gem_restore_fences(dev);
if (IS_GEN4(dev)) if (IS_GEN4(dev_priv))
pci_write_config_word(pdev, GCDGMBUS, pci_write_config_word(pdev, GCDGMBUS,
dev_priv->regfile.saveGCDGMBUS); dev_priv->regfile.saveGCDGMBUS);
i915_restore_display(dev); i915_restore_display(dev);

6
drivers/gpu/drm/i915/intel_crt.c
View File

@ -259,7 +259,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
* DAC limit supposedly 355 MHz. * DAC limit supposedly 355 MHz.
*/ */
max_clock = 270000; max_clock = 270000;
else if (IS_GEN3(dev) || IS_GEN4(dev)) else if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv))
max_clock = 400000; max_clock = 400000;
else else
max_clock = 350000; max_clock = 350000;
@ -567,7 +567,7 @@ intel_crt_load_detect(struct intel_crt *crt, uint32_t pipe)
/* Set the border color to purple. */ /* Set the border color to purple. */
I915_WRITE(bclrpat_reg, 0x500050); I915_WRITE(bclrpat_reg, 0x500050);
if (!IS_GEN2(dev)) { if (!IS_GEN2(dev_priv)) {
uint32_t pipeconf = I915_READ(pipeconf_reg); uint32_t pipeconf = I915_READ(pipeconf_reg);
I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
POSTING_READ(pipeconf_reg); POSTING_READ(pipeconf_reg);
@ -899,7 +899,7 @@ void intel_crt_init(struct drm_device *dev)
else else
crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
if (IS_GEN2(dev)) if (IS_GEN2(dev_priv))
connector->interlace_allowed = 0; connector->interlace_allowed = 0;
else else
connector->interlace_allowed = 1; connector->interlace_allowed = 1;

41
drivers/gpu/drm/i915/intel_display.c
View File

@ -1045,7 +1045,7 @@ static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
u32 line1, line2; u32 line1, line2;
u32 line_mask; u32 line_mask;
if (IS_GEN2(dev)) if (IS_GEN2(dev_priv))
line_mask = DSL_LINEMASK_GEN2; line_mask = DSL_LINEMASK_GEN2;
else else
line_mask = DSL_LINEMASK_GEN3; line_mask = DSL_LINEMASK_GEN3;
@ -3945,7 +3945,7 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
temp = I915_READ(reg); temp = I915_READ(reg);
temp &= ~FDI_LINK_TRAIN_NONE; temp &= ~FDI_LINK_TRAIN_NONE;
temp |= FDI_LINK_TRAIN_PATTERN_2; temp |= FDI_LINK_TRAIN_PATTERN_2;
if (IS_GEN6(dev)) { if (IS_GEN6(dev_priv)) {
temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
/* SNB-B */ /* SNB-B */
temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
@ -4983,7 +4983,7 @@ intel_post_enable_primary(struct drm_crtc *crtc)
* FIXME: Need to fix the logic to work when we turn off all planes * FIXME: Need to fix the logic to work when we turn off all planes
* but leave the pipe running. * but leave the pipe running.
*/ */
if (IS_GEN2(dev)) if (IS_GEN2(dev_priv))
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
/* Underruns don't always raise interrupts, so check manually. */ /* Underruns don't always raise interrupts, so check manually. */
@ -5006,7 +5006,7 @@ intel_pre_disable_primary(struct drm_crtc *crtc)
* FIXME: Need to fix the logic to work when we turn off all planes * FIXME: Need to fix the logic to work when we turn off all planes
* but leave the pipe running. * but leave the pipe running.
*/ */
if (IS_GEN2(dev)) if (IS_GEN2(dev_priv))
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
/* /*
@ -6773,7 +6773,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
intel_crtc->active = true; intel_crtc->active = true;
if (!IS_GEN2(dev)) if (!IS_GEN2(dev_priv))
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
intel_encoders_pre_enable(crtc, pipe_config, old_state); intel_encoders_pre_enable(crtc, pipe_config, old_state);
@ -6821,7 +6821,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
* On gen2 planes are double buffered but the pipe isn't, so we must * On gen2 planes are double buffered but the pipe isn't, so we must
* wait for planes to fully turn off before disabling the pipe. * wait for planes to fully turn off before disabling the pipe.
*/ */
if (IS_GEN2(dev)) if (IS_GEN2(dev_priv))
intel_wait_for_vblank(dev, pipe); intel_wait_for_vblank(dev, pipe);
intel_encoders_disable(crtc, old_crtc_state, old_state); intel_encoders_disable(crtc, old_crtc_state, old_state);
@ -6846,7 +6846,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state); intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
if (!IS_GEN2(dev)) if (!IS_GEN2(dev_priv))
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
} }
@ -9844,7 +9844,7 @@ static void ironlake_get_pfit_config(struct intel_crtc *crtc,
/* We currently do not free assignements of panel fitters on /* We currently do not free assignements of panel fitters on
* ivb/hsw (since we don't use the higher upscaling modes which * ivb/hsw (since we don't use the higher upscaling modes which
* differentiates them) so just WARN about this case for now. */ * differentiates them) so just WARN about this case for now. */
if (IS_GEN7(dev)) { if (IS_GEN7(dev_priv)) {
WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
PF_PIPE_SEL_IVB(crtc->pipe)); PF_PIPE_SEL_IVB(crtc->pipe));
} }
@ -11320,7 +11320,7 @@ static int i9xx_pll_refclk(struct drm_device *dev,
return dev_priv->vbt.lvds_ssc_freq; return dev_priv->vbt.lvds_ssc_freq;
else if (HAS_PCH_SPLIT(dev_priv)) else if (HAS_PCH_SPLIT(dev_priv))
return 120000; return 120000;
else if (!IS_GEN2(dev)) else if (!IS_GEN2(dev_priv))
return 96000; return 96000;
else else
return 48000; return 48000;
@ -11353,7 +11353,7 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
} }
if (!IS_GEN2(dev)) { if (!IS_GEN2(dev_priv)) {
if (IS_PINEVIEW(dev)) if (IS_PINEVIEW(dev))
clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
@ -11852,6 +11852,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
struct drm_i915_gem_request *req, struct drm_i915_gem_request *req,
uint32_t flags) uint32_t flags)
{ {
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_ring *ring = req->ring; struct intel_ring *ring = req->ring;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
uint32_t plane_bit = 0; uint32_t plane_bit = 0;
@ -11880,7 +11881,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
* 48bits addresses, and we need a NOOP for the batch size to * 48bits addresses, and we need a NOOP for the batch size to
* stay even. * stay even.
*/ */
if (IS_GEN8(dev)) if (IS_GEN8(dev_priv))
len += 2; len += 2;
} }
@ -11917,7 +11918,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
DERRMR_PIPEB_PRI_FLIP_DONE | DERRMR_PIPEB_PRI_FLIP_DONE |
DERRMR_PIPEC_PRI_FLIP_DONE)); DERRMR_PIPEC_PRI_FLIP_DONE));
if (IS_GEN8(dev)) if (IS_GEN8(dev_priv))
intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
MI_SRM_LRM_GLOBAL_GTT); MI_SRM_LRM_GLOBAL_GTT);
else else
@ -11926,7 +11927,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
intel_ring_emit_reg(ring, DERRMR); intel_ring_emit_reg(ring, DERRMR);
intel_ring_emit(ring, intel_ring_emit(ring,
i915_ggtt_offset(req->engine->scratch) + 256); i915_ggtt_offset(req->engine->scratch) + 256);
if (IS_GEN8(dev)) { if (IS_GEN8(dev_priv)) {
intel_ring_emit(ring, 0); intel_ring_emit(ring, 0);
intel_ring_emit(ring, MI_NOOP); intel_ring_emit(ring, MI_NOOP);
} }
@ -15320,7 +15321,7 @@ static bool has_edp_a(struct drm_device *dev)
if ((I915_READ(DP_A) & DP_DETECTED) == 0) if ((I915_READ(DP_A) & DP_DETECTED) == 0)
return false; return false;
if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
return false; return false;
return true; return true;
@ -15522,7 +15523,7 @@ static void intel_setup_outputs(struct drm_device *dev)
} }
intel_dsi_init(dev); intel_dsi_init(dev);
} else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) { } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
bool found = false; bool found = false;
if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
@ -15556,7 +15557,7 @@ static void intel_setup_outputs(struct drm_device *dev)
if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED)) if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
intel_dp_init(dev, DP_D, PORT_D); intel_dp_init(dev, DP_D, PORT_D);
} else if (IS_GEN2(dev)) } else if (IS_GEN2(dev_priv))
intel_dvo_init(dev); intel_dvo_init(dev);
if (SUPPORTS_TV(dev)) if (SUPPORTS_TV(dev))
@ -16381,10 +16382,10 @@ void intel_modeset_init(struct drm_device *dev)
} }
} }
if (IS_GEN2(dev)) { if (IS_GEN2(dev_priv)) {
dev->mode_config.max_width = 2048; dev->mode_config.max_width = 2048;
dev->mode_config.max_height = 2048; dev->mode_config.max_height = 2048;
} else if (IS_GEN3(dev)) { } else if (IS_GEN3(dev_priv)) {
dev->mode_config.max_width = 4096; dev->mode_config.max_width = 4096;
dev->mode_config.max_height = 4096; dev->mode_config.max_height = 4096;
} else { } else {
@ -16395,7 +16396,7 @@ void intel_modeset_init(struct drm_device *dev)
if (IS_845G(dev_priv) || IS_I865G(dev_priv)) { if (IS_845G(dev_priv) || IS_I865G(dev_priv)) {
dev->mode_config.cursor_width = IS_845G(dev_priv) ? 64 : 512; dev->mode_config.cursor_width = IS_845G(dev_priv) ? 64 : 512;
dev->mode_config.cursor_height = 1023; dev->mode_config.cursor_height = 1023;
} else if (IS_GEN2(dev)) { } else if (IS_GEN2(dev_priv)) {
dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
} else { } else {
@ -16916,7 +16917,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev)
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
vlv_wm_get_hw_state(dev); vlv_wm_get_hw_state(dev);
else if (IS_GEN9(dev)) else if (IS_GEN9(dev_priv))
skl_wm_get_hw_state(dev); skl_wm_get_hw_state(dev);
else if (HAS_PCH_SPLIT(dev_priv)) else if (HAS_PCH_SPLIT(dev_priv))
ilk_wm_get_hw_state(dev); ilk_wm_get_hw_state(dev);

20
drivers/gpu/drm/i915/intel_dp.c
View File

@ -1767,7 +1767,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
/* Split out the IBX/CPU vs CPT settings */ /* Split out the IBX/CPU vs CPT settings */
if (IS_GEN7(dev) && port == PORT_A) { if (IS_GEN7(dev_priv) && port == PORT_A) {
if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
intel_dp->DP |= DP_SYNC_HS_HIGH; intel_dp->DP |= DP_SYNC_HS_HIGH;
if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
@ -2113,7 +2113,7 @@ static void edp_panel_on(struct intel_dp *intel_dp)
pp_ctrl_reg = _pp_ctrl_reg(intel_dp); pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
pp = ironlake_get_pp_control(intel_dp); pp = ironlake_get_pp_control(intel_dp);
if (IS_GEN5(dev)) { if (IS_GEN5(dev_priv)) {
/* ILK workaround: disable reset around power sequence */ /* ILK workaround: disable reset around power sequence */
pp &= ~PANEL_POWER_RESET; pp &= ~PANEL_POWER_RESET;
I915_WRITE(pp_ctrl_reg, pp); I915_WRITE(pp_ctrl_reg, pp);
@ -2121,7 +2121,7 @@ static void edp_panel_on(struct intel_dp *intel_dp)
} }
pp |= PANEL_POWER_ON; pp |= PANEL_POWER_ON;
if (!IS_GEN5(dev)) if (!IS_GEN5(dev_priv))
pp |= PANEL_POWER_RESET; pp |= PANEL_POWER_RESET;
I915_WRITE(pp_ctrl_reg, pp); I915_WRITE(pp_ctrl_reg, pp);
@ -2130,7 +2130,7 @@ static void edp_panel_on(struct intel_dp *intel_dp)
wait_panel_on(intel_dp); wait_panel_on(intel_dp);
intel_dp->last_power_on = jiffies; intel_dp->last_power_on = jiffies;
if (IS_GEN5(dev)) { if (IS_GEN5(dev_priv)) {
pp |= PANEL_POWER_RESET; /* restore panel reset bit */ pp |= PANEL_POWER_RESET; /* restore panel reset bit */
I915_WRITE(pp_ctrl_reg, pp); I915_WRITE(pp_ctrl_reg, pp);
POSTING_READ(pp_ctrl_reg); POSTING_READ(pp_ctrl_reg);
@ -2443,7 +2443,7 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
if (!(tmp & DP_PORT_EN)) if (!(tmp & DP_PORT_EN))
goto out; goto out;
if (IS_GEN7(dev) && port == PORT_A) { if (IS_GEN7(dev_priv) && port == PORT_A) {
*pipe = PORT_TO_PIPE_CPT(tmp); *pipe = PORT_TO_PIPE_CPT(tmp);
} else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
enum pipe p; enum pipe p;
@ -2661,7 +2661,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
} }
I915_WRITE(DP_TP_CTL(port), temp); I915_WRITE(DP_TP_CTL(port), temp);
} else if ((IS_GEN7(dev) && port == PORT_A) || } else if ((IS_GEN7(dev_priv) && port == PORT_A) ||
(HAS_PCH_CPT(dev_priv) && port != PORT_A)) { (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
*DP &= ~DP_LINK_TRAIN_MASK_CPT; *DP &= ~DP_LINK_TRAIN_MASK_CPT;
@ -2990,7 +2990,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
else if (IS_GEN7(dev) && port == PORT_A) else if (IS_GEN7(dev_priv) && port == PORT_A)
return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
@ -3353,10 +3353,10 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
signal_levels = chv_signal_levels(intel_dp); signal_levels = chv_signal_levels(intel_dp);
} else if (IS_VALLEYVIEW(dev_priv)) { } else if (IS_VALLEYVIEW(dev_priv)) {
signal_levels = vlv_signal_levels(intel_dp); signal_levels = vlv_signal_levels(intel_dp);
} else if (IS_GEN7(dev) && port == PORT_A) { } else if (IS_GEN7(dev_priv) && port == PORT_A) {
signal_levels = gen7_edp_signal_levels(train_set); signal_levels = gen7_edp_signal_levels(train_set);
mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
} else if (IS_GEN6(dev) && port == PORT_A) { } else if (IS_GEN6(dev_priv) && port == PORT_A) {
signal_levels = gen6_edp_signal_levels(train_set); signal_levels = gen6_edp_signal_levels(train_set);
mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
} else { } else {
@ -3444,7 +3444,7 @@ intel_dp_link_down(struct intel_dp *intel_dp)
DRM_DEBUG_KMS("\n"); DRM_DEBUG_KMS("\n");
if ((IS_GEN7(dev) && port == PORT_A) || if ((IS_GEN7(dev_priv) && port == PORT_A) ||
(HAS_PCH_CPT(dev_priv) && port != PORT_A)) { (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
DP &= ~DP_LINK_TRAIN_MASK_CPT; DP &= ~DP_LINK_TRAIN_MASK_CPT;
DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;

2
drivers/gpu/drm/i915/intel_drv.h
View File

@ -1722,7 +1722,7 @@ bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
/* intel_pm.c */ /* intel_pm.c */
void intel_init_clock_gating(struct drm_device *dev); void intel_init_clock_gating(struct drm_device *dev);
void intel_suspend_hw(struct drm_device *dev); void intel_suspend_hw(struct drm_device *dev);
int ilk_wm_max_level(const struct drm_device *dev); int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
void intel_update_watermarks(struct drm_crtc *crtc); void intel_update_watermarks(struct drm_crtc *crtc);
void intel_init_pm(struct drm_device *dev); void intel_init_pm(struct drm_device *dev);
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv); void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);

6
drivers/gpu/drm/i915/intel_fifo_underrun.c
View File

@ -256,11 +256,11 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
if (HAS_GMCH_DISPLAY(dev_priv)) if (HAS_GMCH_DISPLAY(dev_priv))
i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old); i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
else if (IS_GEN5(dev) || IS_GEN6(dev)) else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv))
ironlake_set_fifo_underrun_reporting(dev, pipe, enable); ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
else if (IS_GEN7(dev)) else if (IS_GEN7(dev_priv))
ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old); ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old);
else if (IS_GEN8(dev) || IS_GEN9(dev)) else if (IS_GEN8(dev_priv) || IS_GEN9(dev_priv))
broadwell_set_fifo_underrun_reporting(dev, pipe, enable); broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
return old; return old;

3
drivers/gpu/drm/i915/intel_guc_loader.c
View File

@ -349,7 +349,6 @@ static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
static int guc_ucode_xfer(struct drm_i915_private *dev_priv) static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
{ {
struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
struct drm_device *dev = &dev_priv->drm;
struct i915_vma *vma; struct i915_vma *vma;
int ret; int ret;
@ -392,7 +391,7 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
else else
I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE); I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
if (IS_GEN9(dev)) { if (IS_GEN9(dev_priv)) {
/* DOP Clock Gating Enable for GuC clocks */ /* DOP Clock Gating Enable for GuC clocks */
I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE | I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
I915_READ(GEN7_MISCCPCTL))); I915_READ(GEN7_MISCCPCTL)));

2
drivers/gpu/drm/i915/intel_lvds.c
View File

@ -1071,7 +1071,7 @@ void intel_lvds_init(struct drm_device *dev)
intel_encoder->cloneable = 0; intel_encoder->cloneable = 0;
if (HAS_PCH_SPLIT(dev_priv)) if (HAS_PCH_SPLIT(dev_priv))
intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
else if (IS_GEN4(dev)) else if (IS_GEN4(dev_priv))
intel_encoder->crtc_mask = (1 << 0) | (1 << 1); intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
else else
intel_encoder->crtc_mask = (1 << 1); intel_encoder->crtc_mask = (1 << 1);

83
drivers/gpu/drm/i915/intel_pm.c
View File

@ -1530,7 +1530,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
if (IS_I945GM(dev)) if (IS_I945GM(dev))
wm_info = &i945_wm_info; wm_info = &i945_wm_info;
else if (!IS_GEN2(dev)) else if (!IS_GEN2(dev_priv))
wm_info = &i915_wm_info; wm_info = &i915_wm_info;
else else
wm_info = &i830_a_wm_info; wm_info = &i830_a_wm_info;
@ -1540,7 +1540,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
if (intel_crtc_active(crtc)) { if (intel_crtc_active(crtc)) {
const struct drm_display_mode *adjusted_mode; const struct drm_display_mode *adjusted_mode;
int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0); int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
if (IS_GEN2(dev)) if (IS_GEN2(dev_priv))
cpp = 4; cpp = 4;
adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
@ -1554,7 +1554,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
planea_wm = wm_info->max_wm; planea_wm = wm_info->max_wm;
} }
if (IS_GEN2(dev)) if (IS_GEN2(dev_priv))
wm_info = &i830_bc_wm_info; wm_info = &i830_bc_wm_info;
fifo_size = dev_priv->display.get_fifo_size(dev, 1); fifo_size = dev_priv->display.get_fifo_size(dev, 1);
@ -1562,7 +1562,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
if (intel_crtc_active(crtc)) { if (intel_crtc_active(crtc)) {
const struct drm_display_mode *adjusted_mode; const struct drm_display_mode *adjusted_mode;
int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0); int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
if (IS_GEN2(dev)) if (IS_GEN2(dev_priv))
cpp = 4; cpp = 4;
adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
@ -2082,10 +2082,10 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
{ {
struct drm_i915_private *dev_priv = to_i915(dev); struct drm_i915_private *dev_priv = to_i915(dev);
if (IS_GEN9(dev)) { if (IS_GEN9(dev_priv)) {
uint32_t val; uint32_t val;
int ret, i; int ret, i;
int level, max_level = ilk_wm_max_level(dev); int level, max_level = ilk_wm_max_level(dev_priv);
/* read the first set of memory latencies[0:3] */ /* read the first set of memory latencies[0:3] */
val = 0; /* data0 to be programmed to 0 for first set */ val = 0; /* data0 to be programmed to 0 for first set */
@ -2184,10 +2184,11 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
} }
} }
static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5]) static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
uint16_t wm[5])
{ {
/* ILK sprite LP0 latency is 1300 ns */ /* ILK sprite LP0 latency is 1300 ns */
if (IS_GEN5(dev)) if (IS_GEN5(dev_priv))
wm[0] = 13; wm[0] = 13;
} }
@ -2203,10 +2204,8 @@ static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
wm[3] *= 2; wm[3] *= 2;
} }
int ilk_wm_max_level(const struct drm_device *dev) int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
{ {
struct drm_i915_private *dev_priv = to_i915(dev);
/* how many WM levels are we expecting */ /* how many WM levels are we expecting */
if (INTEL_GEN(dev_priv) >= 9) if (INTEL_GEN(dev_priv) >= 9)
return 7; return 7;
@ -2218,11 +2217,11 @@ int ilk_wm_max_level(const struct drm_device *dev)
return 2; return 2;
} }
static void intel_print_wm_latency(struct drm_device *dev, static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
const char *name, const char *name,
const uint16_t wm[8]) const uint16_t wm[8])
{ {
int level, max_level = ilk_wm_max_level(dev); int level, max_level = ilk_wm_max_level(dev_priv);
for (level = 0; level <= max_level; level++) { for (level = 0; level <= max_level; level++) {
unsigned int latency = wm[level]; unsigned int latency = wm[level];
@ -2237,7 +2236,7 @@ static void intel_print_wm_latency(struct drm_device *dev,
* - latencies are in us on gen9. * - latencies are in us on gen9.
* - before then, WM1+ latency values are in 0.5us units * - before then, WM1+ latency values are in 0.5us units
*/ */
if (IS_GEN9(dev)) if (IS_GEN9(dev_priv))
latency *= 10; latency *= 10;
else if (level > 0) else if (level > 0)
latency *= 5; latency *= 5;
@ -2251,7 +2250,7 @@ static void intel_print_wm_latency(struct drm_device *dev,
static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv, static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
uint16_t wm[5], uint16_t min) uint16_t wm[5], uint16_t min)
{ {
int level, max_level = ilk_wm_max_level(&dev_priv->drm); int level, max_level = ilk_wm_max_level(dev_priv);
if (wm[0] >= min) if (wm[0] >= min)
return false; return false;
@ -2280,9 +2279,9 @@ static void snb_wm_latency_quirk(struct drm_device *dev)
return; return;
DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n"); DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
} }
static void ilk_setup_wm_latency(struct drm_device *dev) static void ilk_setup_wm_latency(struct drm_device *dev)
@ -2296,14 +2295,14 @@ static void ilk_setup_wm_latency(struct drm_device *dev)
memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency, memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
sizeof(dev_priv->wm.pri_latency)); sizeof(dev_priv->wm.pri_latency));
intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency); intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency); intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
if (IS_GEN6(dev)) if (IS_GEN6(dev_priv))
snb_wm_latency_quirk(dev); snb_wm_latency_quirk(dev);
} }
@ -2312,7 +2311,7 @@ static void skl_setup_wm_latency(struct drm_device *dev)
struct drm_i915_private *dev_priv = to_i915(dev); struct drm_i915_private *dev_priv = to_i915(dev);
intel_read_wm_latency(dev, dev_priv->wm.skl_latency); intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency); intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
} }
static bool ilk_validate_pipe_wm(struct drm_device *dev, static bool ilk_validate_pipe_wm(struct drm_device *dev,
@ -2350,7 +2349,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
struct intel_plane_state *pristate = NULL; struct intel_plane_state *pristate = NULL;
struct intel_plane_state *sprstate = NULL; struct intel_plane_state *sprstate = NULL;
struct intel_plane_state *curstate = NULL; struct intel_plane_state *curstate = NULL;
int level, max_level = ilk_wm_max_level(dev), usable_level; int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
struct ilk_wm_maximums max; struct ilk_wm_maximums max;
pipe_wm = &cstate->wm.ilk.optimal; pipe_wm = &cstate->wm.ilk.optimal;
@ -2437,7 +2436,7 @@ static int ilk_compute_intermediate_wm(struct drm_device *dev,
{ {
struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate; struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk; struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
int level, max_level = ilk_wm_max_level(dev); int level, max_level = ilk_wm_max_level(to_i915(dev));
/* /*
* Start with the final, target watermarks, then combine with the * Start with the final, target watermarks, then combine with the
@ -2521,7 +2520,7 @@ static void ilk_wm_merge(struct drm_device *dev,
struct intel_pipe_wm *merged) struct intel_pipe_wm *merged)
{ {
struct drm_i915_private *dev_priv = to_i915(dev); struct drm_i915_private *dev_priv = to_i915(dev);
int level, max_level = ilk_wm_max_level(dev); int level, max_level = ilk_wm_max_level(dev_priv);
int last_enabled_level = max_level; int last_enabled_level = max_level;
/* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */ /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
@ -2561,7 +2560,7 @@ static void ilk_wm_merge(struct drm_device *dev,
* What we should check here is whether FBC can be * What we should check here is whether FBC can be
* enabled sometime later. * enabled sometime later.
*/ */
if (IS_GEN5(dev) && !merged->fbc_wm_enabled && if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled &&
intel_fbc_is_active(dev_priv)) { intel_fbc_is_active(dev_priv)) {
for (level = 2; level <= max_level; level++) { for (level = 2; level <= max_level; level++) {
struct intel_wm_level *wm = &merged->wm[level]; struct intel_wm_level *wm = &merged->wm[level];
@ -2661,7 +2660,7 @@ static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
struct intel_pipe_wm *r1, struct intel_pipe_wm *r1,
struct intel_pipe_wm *r2) struct intel_pipe_wm *r2)
{ {
int level, max_level = ilk_wm_max_level(dev); int level, max_level = ilk_wm_max_level(to_i915(dev));
int level1 = 0, level2 = 0; int level1 = 0, level2 = 0;
for (level = 1; level <= max_level; level++) { for (level = 1; level <= max_level; level++) {
@ -3035,7 +3034,7 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state)
continue; continue;
/* Find the highest enabled wm level for this plane */ /* Find the highest enabled wm level for this plane */
for (level = ilk_wm_max_level(dev); for (level = ilk_wm_max_level(dev_priv);
intel_state->wm_results.plane[pipe][plane][level] == 0; --level) intel_state->wm_results.plane[pipe][plane][level] == 0; --level)
{ } { }
@ -3778,7 +3777,7 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
{ {
struct drm_device *dev = cstate->base.crtc->dev; struct drm_device *dev = cstate->base.crtc->dev;
const struct drm_i915_private *dev_priv = to_i915(dev); const struct drm_i915_private *dev_priv = to_i915(dev);
int level, max_level = ilk_wm_max_level(dev); int level, max_level = ilk_wm_max_level(dev_priv);
int ret; int ret;
for (level = 0; level <= max_level; level++) { for (level = 0; level <= max_level; level++) {
@ -3799,7 +3798,7 @@ static void skl_compute_wm_results(struct drm_device *dev,
struct skl_wm_values *r, struct skl_wm_values *r,
struct intel_crtc *intel_crtc) struct intel_crtc *intel_crtc)
{ {
int level, max_level = ilk_wm_max_level(dev); int level, max_level = ilk_wm_max_level(to_i915(dev));
enum pipe pipe = intel_crtc->pipe; enum pipe pipe = intel_crtc->pipe;
uint32_t temp; uint32_t temp;
int i; int i;
@ -3868,7 +3867,7 @@ void skl_write_plane_wm(struct intel_crtc *intel_crtc,
struct drm_crtc *crtc = &intel_crtc->base; struct drm_crtc *crtc = &intel_crtc->base;
struct drm_device *dev = crtc->dev; struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = to_i915(dev); struct drm_i915_private *dev_priv = to_i915(dev);
int level, max_level = ilk_wm_max_level(dev); int level, max_level = ilk_wm_max_level(dev_priv);
enum pipe pipe = intel_crtc->pipe; enum pipe pipe = intel_crtc->pipe;
for (level = 0; level <= max_level; level++) { for (level = 0; level <= max_level; level++) {
@ -3889,7 +3888,7 @@ void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
struct drm_crtc *crtc = &intel_crtc->base; struct drm_crtc *crtc = &intel_crtc->base;
struct drm_device *dev = crtc->dev; struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = to_i915(dev); struct drm_i915_private *dev_priv = to_i915(dev);
int level, max_level = ilk_wm_max_level(dev); int level, max_level = ilk_wm_max_level(dev_priv);
enum pipe pipe = intel_crtc->pipe; enum pipe pipe = intel_crtc->pipe;
for (level = 0; level <= max_level; level++) { for (level = 0; level <= max_level; level++) {
@ -4339,7 +4338,7 @@ static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
int level, i, max_level; int level, i, max_level;
uint32_t temp; uint32_t temp;
max_level = ilk_wm_max_level(dev); max_level = ilk_wm_max_level(dev_priv);
hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
@ -4439,7 +4438,7 @@ static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK; active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
active->linetime = hw->wm_linetime[pipe]; active->linetime = hw->wm_linetime[pipe];
} else { } else {
int level, max_level = ilk_wm_max_level(dev); int level, max_level = ilk_wm_max_level(dev_priv);
/* /*
* For inactive pipes, all watermark levels * For inactive pipes, all watermark levels
@ -7742,7 +7741,7 @@ void intel_init_pm(struct drm_device *dev)
/* For cxsr */ /* For cxsr */
if (IS_PINEVIEW(dev)) if (IS_PINEVIEW(dev))
i915_pineview_get_mem_freq(dev); i915_pineview_get_mem_freq(dev);
else if (IS_GEN5(dev)) else if (IS_GEN5(dev_priv))
i915_ironlake_get_mem_freq(dev); i915_ironlake_get_mem_freq(dev);
/* For FIFO watermark updates */ /* For FIFO watermark updates */
@ -7753,9 +7752,9 @@ void intel_init_pm(struct drm_device *dev)
} else if (HAS_PCH_SPLIT(dev_priv)) { } else if (HAS_PCH_SPLIT(dev_priv)) {
ilk_setup_wm_latency(dev); ilk_setup_wm_latency(dev);
if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] && if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] &&
dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
(!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] && (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] &&
dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) { dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm; dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
dev_priv->display.compute_intermediate_wm = dev_priv->display.compute_intermediate_wm =
@ -7791,12 +7790,12 @@ void intel_init_pm(struct drm_device *dev)
dev_priv->display.update_wm = pineview_update_wm; dev_priv->display.update_wm = pineview_update_wm;
} else if (IS_G4X(dev_priv)) { } else if (IS_G4X(dev_priv)) {
dev_priv->display.update_wm = g4x_update_wm; dev_priv->display.update_wm = g4x_update_wm;
} else if (IS_GEN4(dev)) { } else if (IS_GEN4(dev_priv)) {
dev_priv->display.update_wm = i965_update_wm; dev_priv->display.update_wm = i965_update_wm;
} else if (IS_GEN3(dev)) { } else if (IS_GEN3(dev_priv)) {
dev_priv->display.update_wm = i9xx_update_wm; dev_priv->display.update_wm = i9xx_update_wm;
dev_priv->display.get_fifo_size = i9xx_get_fifo_size; dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
} else if (IS_GEN2(dev)) { } else if (IS_GEN2(dev_priv)) {
if (INTEL_INFO(dev)->num_pipes == 1) { if (INTEL_INFO(dev)->num_pipes == 1) {
dev_priv->display.update_wm = i845_update_wm; dev_priv->display.update_wm = i845_update_wm;
dev_priv->display.get_fifo_size = i845_get_fifo_size; dev_priv->display.get_fifo_size = i845_get_fifo_size;

4
drivers/gpu/drm/i915/intel_sprite.c
View File

@ -680,7 +680,7 @@ ilk_update_plane(struct drm_plane *plane,
if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
dvscntr |= DVS_TILED; dvscntr |= DVS_TILED;
if (IS_GEN6(dev)) if (IS_GEN6(dev_priv))
dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */ dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
/* Sizes are 0 based */ /* Sizes are 0 based */
@ -1075,7 +1075,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
intel_plane->update_plane = ilk_update_plane; intel_plane->update_plane = ilk_update_plane;
intel_plane->disable_plane = ilk_disable_plane; intel_plane->disable_plane = ilk_disable_plane;
if (IS_GEN6(dev)) { if (IS_GEN6(dev_priv)) {
plane_formats = snb_plane_formats; plane_formats = snb_plane_formats;
num_plane_formats = ARRAY_SIZE(snb_plane_formats); num_plane_formats = ARRAY_SIZE(snb_plane_formats);
} else { } else {