Linux 3.19-rc2
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABAgAGBQJUoKU4AAoJEHm+PkMAQRiGvzYIAJOrjgTaf/vK2sSGH0398656 wkUomtfmIqDxTGr+DB5OEf59rYODcMYjnVOWwhto9lGtu49MKor35DV0/0J5gQJb l4FE+UA8p2sE22RIAqGB2992pbRVtGpAB0q4PlCGnaYl8vyP8lRe/lozL3/lwPK8 lR7dDOsix5LU75mxqLUTmVXTSwyLW4tIHLt8qwLzJWRqJEAk1Ip1MNf9RnoSSI4C clL5FMEWj3D62a5kVvgguFypqGLnLSvNALqk2RwL3u3SMBDvwnIQD9fTpg8tCihX 2MVNP3IS2KDlPg93p8lzWk8KBTbwWRJCxLT44LexPhhHUTquZTnTg7oJeJdrRy0= =p+ym -----END PGP SIGNATURE----- Merge tag 'v3.19-rc2' into for-3.20/core Linux 3.19-rc2
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3
.gitignore
vendored
3
.gitignore
vendored
@ -96,3 +96,6 @@ x509.genkey
|
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|
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# Kconfig presets
|
||||
all.config
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||||
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# Kdevelop4
|
||||
*.kdev4
|
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|
@ -74,7 +74,7 @@ the operations defined in clk.h:
|
||||
long (*determine_rate)(struct clk_hw *hw,
|
||||
unsigned long rate,
|
||||
unsigned long *best_parent_rate,
|
||||
struct clk **best_parent_clk);
|
||||
struct clk_hw **best_parent_clk);
|
||||
int (*set_parent)(struct clk_hw *hw, u8 index);
|
||||
u8 (*get_parent)(struct clk_hw *hw);
|
||||
int (*set_rate)(struct clk_hw *hw,
|
||||
|
38
Documentation/devicetree/bindings/clock/exynos4415-clock.txt
Normal file
38
Documentation/devicetree/bindings/clock/exynos4415-clock.txt
Normal file
@ -0,0 +1,38 @@
|
||||
* Samsung Exynos4415 Clock Controller
|
||||
|
||||
The Exynos4415 clock controller generates and supplies clock to various
|
||||
consumer devices within the Exynos4415 SoC.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: should be one of the following:
|
||||
- "samsung,exynos4415-cmu" - for the main system clocks controller
|
||||
(CMU_LEFTBUS, CMU_RIGHTBUS, CMU_TOP, CMU_CPU clock domains).
|
||||
- "samsung,exynos4415-cmu-dmc" - for the Exynos4415 SoC DRAM Memory
|
||||
Controller (DMC) domain clock controller.
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||||
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
||||
- #clock-cells: should be 1.
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|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume.
|
||||
|
||||
All available clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/exynos4415.h header and can be used in device
|
||||
tree sources.
|
||||
|
||||
Example 1: An example of a clock controller node is listed below.
|
||||
|
||||
cmu: clock-controller@10030000 {
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||||
compatible = "samsung,exynos4415-cmu";
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||||
reg = <0x10030000 0x18000>;
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#clock-cells = <1>;
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||||
};
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cmu-dmc: clock-controller@105C0000 {
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compatible = "samsung,exynos4415-cmu-dmc";
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reg = <0x105C0000 0x3000>;
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#clock-cells = <1>;
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};
|
93
Documentation/devicetree/bindings/clock/exynos7-clock.txt
Normal file
93
Documentation/devicetree/bindings/clock/exynos7-clock.txt
Normal file
@ -0,0 +1,93 @@
|
||||
* Samsung Exynos7 Clock Controller
|
||||
|
||||
Exynos7 clock controller has various blocks which are instantiated
|
||||
independently from the device-tree. These clock controllers
|
||||
generate and supply clocks to various hardware blocks within
|
||||
the SoC.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use
|
||||
this identifier to specify the clock which they consume. All
|
||||
available clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/exynos7-clk.h header and can be used in
|
||||
device tree sources.
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||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It
|
||||
is expected that they are defined using standard clock bindings
|
||||
with following clock-output-names:
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|
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- "fin_pll" - PLL input clock from XXTI
|
||||
|
||||
Required Properties for Clock Controller:
|
||||
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||||
- compatible: clock controllers will use one of the following
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||||
compatible strings to indicate the clock controller
|
||||
functionality.
|
||||
|
||||
- "samsung,exynos7-clock-topc"
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- "samsung,exynos7-clock-top0"
|
||||
- "samsung,exynos7-clock-top1"
|
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- "samsung,exynos7-clock-ccore"
|
||||
- "samsung,exynos7-clock-peric0"
|
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- "samsung,exynos7-clock-peric1"
|
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- "samsung,exynos7-clock-peris"
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- "samsung,exynos7-clock-fsys0"
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- "samsung,exynos7-clock-fsys1"
|
||||
|
||||
- reg: physical base address of the controller and the length of
|
||||
memory mapped region.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
- clocks: list of clock identifiers which are fed as the input to
|
||||
the given clock controller. Please refer the next section to
|
||||
find the input clocks for a given controller.
|
||||
|
||||
- clock-names: list of names of clocks which are fed as the input
|
||||
to the given clock controller.
|
||||
|
||||
Input clocks for top0 clock controller:
|
||||
- fin_pll
|
||||
- dout_sclk_bus0_pll
|
||||
- dout_sclk_bus1_pll
|
||||
- dout_sclk_cc_pll
|
||||
- dout_sclk_mfc_pll
|
||||
|
||||
Input clocks for top1 clock controller:
|
||||
- fin_pll
|
||||
- dout_sclk_bus0_pll
|
||||
- dout_sclk_bus1_pll
|
||||
- dout_sclk_cc_pll
|
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- dout_sclk_mfc_pll
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||||
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Input clocks for ccore clock controller:
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||||
- fin_pll
|
||||
- dout_aclk_ccore_133
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||||
|
||||
Input clocks for peric0 clock controller:
|
||||
- fin_pll
|
||||
- dout_aclk_peric0_66
|
||||
- sclk_uart0
|
||||
|
||||
Input clocks for peric1 clock controller:
|
||||
- fin_pll
|
||||
- dout_aclk_peric1_66
|
||||
- sclk_uart1
|
||||
- sclk_uart2
|
||||
- sclk_uart3
|
||||
|
||||
Input clocks for peris clock controller:
|
||||
- fin_pll
|
||||
- dout_aclk_peris_66
|
||||
|
||||
Input clocks for fsys0 clock controller:
|
||||
- fin_pll
|
||||
- dout_aclk_fsys0_200
|
||||
- dout_sclk_mmc2
|
||||
|
||||
Input clocks for fsys1 clock controller:
|
||||
- fin_pll
|
||||
- dout_aclk_fsys1_200
|
||||
- dout_sclk_mmc0
|
||||
- dout_sclk_mmc1
|
21
Documentation/devicetree/bindings/clock/marvell,mmp2.txt
Normal file
21
Documentation/devicetree/bindings/clock/marvell,mmp2.txt
Normal file
@ -0,0 +1,21 @@
|
||||
* Marvell MMP2 Clock Controller
|
||||
|
||||
The MMP2 clock subsystem generates and supplies clock to various
|
||||
controllers within the MMP2 SoC.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be one of the following.
|
||||
- "marvell,mmp2-clock" - controller compatible with MMP2 SoC.
|
||||
|
||||
- reg: physical base address of the clock subsystem and length of memory mapped
|
||||
region. There are 3 places in SOC has clock control logic:
|
||||
"mpmu", "apmu", "apbc". So three reg spaces need to be defined.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Each clock is assigned an identifier and client nodes use this identifier
|
||||
to specify the clock which they consume.
|
||||
|
||||
All these identifier could be found in <dt-bindings/clock/marvell-mmp2.h>.
|
21
Documentation/devicetree/bindings/clock/marvell,pxa168.txt
Normal file
21
Documentation/devicetree/bindings/clock/marvell,pxa168.txt
Normal file
@ -0,0 +1,21 @@
|
||||
* Marvell PXA168 Clock Controller
|
||||
|
||||
The PXA168 clock subsystem generates and supplies clock to various
|
||||
controllers within the PXA168 SoC.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be one of the following.
|
||||
- "marvell,pxa168-clock" - controller compatible with PXA168 SoC.
|
||||
|
||||
- reg: physical base address of the clock subsystem and length of memory mapped
|
||||
region. There are 3 places in SOC has clock control logic:
|
||||
"mpmu", "apmu", "apbc". So three reg spaces need to be defined.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Each clock is assigned an identifier and client nodes use this identifier
|
||||
to specify the clock which they consume.
|
||||
|
||||
All these identifier could be found in <dt-bindings/clock/marvell,pxa168.h>.
|
21
Documentation/devicetree/bindings/clock/marvell,pxa910.txt
Normal file
21
Documentation/devicetree/bindings/clock/marvell,pxa910.txt
Normal file
@ -0,0 +1,21 @@
|
||||
* Marvell PXA910 Clock Controller
|
||||
|
||||
The PXA910 clock subsystem generates and supplies clock to various
|
||||
controllers within the PXA910 SoC.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be one of the following.
|
||||
- "marvell,pxa910-clock" - controller compatible with PXA910 SoC.
|
||||
|
||||
- reg: physical base address of the clock subsystem and length of memory mapped
|
||||
region. There are 4 places in SOC has clock control logic:
|
||||
"mpmu", "apmu", "apbc", "apbcp". So four reg spaces need to be defined.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Each clock is assigned an identifier and client nodes use this identifier
|
||||
to specify the clock which they consume.
|
||||
|
||||
All these identifier could be found in <dt-bindings/clock/marvell-pxa910.h>.
|
@ -7,11 +7,16 @@ to 64.
|
||||
Required Properties:
|
||||
|
||||
- compatible: Must be one of the following
|
||||
- "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks
|
||||
- "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks
|
||||
- "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks
|
||||
- "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2) DIV6 clocks
|
||||
- "renesas,sh73a0-div6-clock" for SH73A0 (SH-Mobile AG5) DIV6 clocks
|
||||
- "renesas,cpg-div6-clock" for generic DIV6 clocks
|
||||
- reg: Base address and length of the memory resource used by the DIV6 clock
|
||||
- clocks: Reference to the parent clock
|
||||
- clocks: Reference to the parent clock(s); either one, four, or eight
|
||||
clocks must be specified. For clocks with multiple parents, invalid
|
||||
settings must be specified as "<0>".
|
||||
- #clock-cells: Must be 0
|
||||
- clock-output-names: The name of the clock as a free-form string
|
||||
|
||||
@ -19,10 +24,11 @@ Required Properties:
|
||||
Example
|
||||
-------
|
||||
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||||
sd2_clk: sd2_clk@e6150078 {
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||||
compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe6150078 0 4>;
|
||||
clocks = <&pll1_div2_clk>;
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||||
sdhi2_clk: sdhi2_clk@e615007c {
|
||||
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe615007c 0 4>;
|
||||
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
|
||||
<0>, <&extal2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "sd2";
|
||||
clock-output-names = "sdhi2ck";
|
||||
};
|
||||
|
@ -26,11 +26,11 @@ Required Properties:
|
||||
must appear in the same order as the output clocks.
|
||||
- #clock-cells: Must be 1
|
||||
- clock-output-names: The name of the clocks as free-form strings
|
||||
- renesas,clock-indices: Indices of the gate clocks into the group (0 to 31)
|
||||
- clock-indices: Indices of the gate clocks into the group (0 to 31)
|
||||
|
||||
The clocks, clock-output-names and renesas,clock-indices properties contain one
|
||||
entry per gate clock. The MSTP groups are sparsely populated. Unimplemented
|
||||
gate clocks must not be declared.
|
||||
The clocks, clock-output-names and clock-indices properties contain one entry
|
||||
per gate clock. The MSTP groups are sparsely populated. Unimplemented gate
|
||||
clocks must not be declared.
|
||||
|
||||
|
||||
Example
|
||||
|
@ -10,14 +10,17 @@ Required properties:
|
||||
"allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
|
||||
"allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
|
||||
"allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
|
||||
"allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80
|
||||
"allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
|
||||
"allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
|
||||
"allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
|
||||
"allwinner,sun9i-a80-gt-clk" - for the GT bus clock on A80
|
||||
"allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
|
||||
"allwinner,sun4i-a10-axi-clk" - for the AXI clock
|
||||
"allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23
|
||||
"allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
|
||||
"allwinner,sun4i-a10-ahb-clk" - for the AHB clock
|
||||
"allwinner,sun9i-a80-ahb-clk" - for the AHB bus clocks on A80
|
||||
"allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10
|
||||
"allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
|
||||
"allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
|
||||
@ -26,24 +29,29 @@ Required properties:
|
||||
"allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
|
||||
"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
|
||||
"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
|
||||
"allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80
|
||||
"allwinner,sun9i-a80-ahb1-gates-clk" - for the AHB1 gates on A80
|
||||
"allwinner,sun9i-a80-ahb2-gates-clk" - for the AHB2 gates on A80
|
||||
"allwinner,sun4i-a10-apb0-clk" - for the APB0 clock
|
||||
"allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31
|
||||
"allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23
|
||||
"allwinner,sun9i-a80-apb0-clk" - for the APB0 bus clock on A80
|
||||
"allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
|
||||
"allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
|
||||
"allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
|
||||
"allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31
|
||||
"allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
|
||||
"allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
|
||||
"allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80
|
||||
"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
|
||||
"allwinner,sun4i-a10-apb1-mux-clk" - for the APB1 clock muxing
|
||||
"allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80
|
||||
"allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
|
||||
"allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
|
||||
"allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
|
||||
"allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
|
||||
"allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
|
||||
"allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A23
|
||||
"allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
|
||||
"allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80
|
||||
"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
|
||||
"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
|
||||
"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
|
||||
@ -63,8 +71,9 @@ Required properties for all clocks:
|
||||
multiplexed clocks, the list order must match the hardware
|
||||
programming order.
|
||||
- #clock-cells : from common clock binding; shall be set to 0 except for
|
||||
"allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk" and
|
||||
"allwinner,sun4i-pll6-clk" where it shall be set to 1
|
||||
the following compatibles where it shall be set to 1:
|
||||
"allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk",
|
||||
"allwinner,sun4i-pll6-clk", "allwinner,sun6i-a31-pll6-clk"
|
||||
- clock-output-names : shall be the corresponding names of the outputs.
|
||||
If the clock module only has one output, the name shall be the
|
||||
module name.
|
||||
@ -79,6 +88,12 @@ Clock consumers should specify the desired clocks they use with a
|
||||
"clocks" phandle cell. Consumers that are using a gated clock should
|
||||
provide an additional ID in their clock property. This ID is the
|
||||
offset of the bit controlling this particular gate in the register.
|
||||
For the other clocks with "#clock-cells" = 1, the additional ID shall
|
||||
refer to the index of the output.
|
||||
|
||||
For "allwinner,sun6i-a31-pll6-clk", there are 2 outputs. The first output
|
||||
is the normal PLL6 output, or "pll6". The second output is rate doubled
|
||||
PLL6, or "pll6x2".
|
||||
|
||||
For example:
|
||||
|
||||
@ -106,6 +121,14 @@ pll5: clk@01c20020 {
|
||||
clock-output-names = "pll5_ddr", "pll5_other";
|
||||
};
|
||||
|
||||
pll6: clk@01c20028 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun6i-a31-pll6-clk";
|
||||
reg = <0x01c20028 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
clock-output-names = "pll6", "pll6x2";
|
||||
};
|
||||
|
||||
cpu: cpu@01c20054 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-cpu-clk";
|
||||
|
@ -2576,8 +2576,9 @@ F: drivers/media/platform/coda/
|
||||
|
||||
COMMON CLK FRAMEWORK
|
||||
M: Mike Turquette <mturquette@linaro.org>
|
||||
M: Stephen Boyd <sboyd@codeaurora.org>
|
||||
L: linux-kernel@vger.kernel.org
|
||||
T: git git://git.linaro.org/people/mturquette/linux.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git
|
||||
S: Maintained
|
||||
F: drivers/clk/
|
||||
X: drivers/clk/clkdev.c
|
||||
|
21
Makefile
21
Makefile
@ -1,7 +1,7 @@
|
||||
VERSION = 3
|
||||
PATCHLEVEL = 18
|
||||
PATCHLEVEL = 19
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION =
|
||||
EXTRAVERSION = -rc2
|
||||
NAME = Diseased Newt
|
||||
|
||||
# *DOCUMENTATION*
|
||||
@ -481,9 +481,10 @@ asm-generic:
|
||||
# of make so .config is not included in this case either (for *config).
|
||||
|
||||
version_h := include/generated/uapi/linux/version.h
|
||||
old_version_h := include/linux/version.h
|
||||
|
||||
no-dot-config-targets := clean mrproper distclean \
|
||||
cscope gtags TAGS tags help %docs check% coccicheck \
|
||||
cscope gtags TAGS tags help% %docs check% coccicheck \
|
||||
$(version_h) headers_% archheaders archscripts \
|
||||
kernelversion %src-pkg
|
||||
|
||||
@ -1005,6 +1006,7 @@ endef
|
||||
|
||||
$(version_h): $(srctree)/Makefile FORCE
|
||||
$(call filechk,version.h)
|
||||
$(Q)rm -f $(old_version_h)
|
||||
|
||||
include/generated/utsrelease.h: include/config/kernel.release FORCE
|
||||
$(call filechk,utsrelease.h)
|
||||
@ -1036,8 +1038,6 @@ firmware_install: FORCE
|
||||
#Default location for installed headers
|
||||
export INSTALL_HDR_PATH = $(objtree)/usr
|
||||
|
||||
hdr-inst := -rR -f $(srctree)/scripts/Makefile.headersinst obj
|
||||
|
||||
# If we do an all arch process set dst to asm-$(hdr-arch)
|
||||
hdr-dst = $(if $(KBUILD_HEADERS), dst=include/asm-$(hdr-arch), dst=include/asm)
|
||||
|
||||
@ -1175,7 +1175,7 @@ MRPROPER_FILES += .config .config.old .version .old_version $(version_h) \
|
||||
Module.symvers tags TAGS cscope* GPATH GTAGS GRTAGS GSYMS \
|
||||
signing_key.priv signing_key.x509 x509.genkey \
|
||||
extra_certificates signing_key.x509.keyid \
|
||||
signing_key.x509.signer include/linux/version.h
|
||||
signing_key.x509.signer
|
||||
|
||||
# clean - Delete most, but leave enough to build external modules
|
||||
#
|
||||
@ -1235,7 +1235,7 @@ rpm: include/config/kernel.release FORCE
|
||||
# ---------------------------------------------------------------------------
|
||||
|
||||
boards := $(wildcard $(srctree)/arch/$(SRCARCH)/configs/*_defconfig)
|
||||
boards := $(notdir $(boards))
|
||||
boards := $(sort $(notdir $(boards)))
|
||||
board-dirs := $(dir $(wildcard $(srctree)/arch/$(SRCARCH)/configs/*/*_defconfig))
|
||||
board-dirs := $(sort $(notdir $(board-dirs:/=)))
|
||||
|
||||
@ -1326,7 +1326,7 @@ help-board-dirs := $(addprefix help-,$(board-dirs))
|
||||
|
||||
help-boards: $(help-board-dirs)
|
||||
|
||||
boards-per-dir = $(notdir $(wildcard $(srctree)/arch/$(SRCARCH)/configs/$*/*_defconfig))
|
||||
boards-per-dir = $(sort $(notdir $(wildcard $(srctree)/arch/$(SRCARCH)/configs/$*/*_defconfig)))
|
||||
|
||||
$(help-board-dirs): help-%:
|
||||
@echo 'Architecture specific targets ($(SRCARCH) $*):'
|
||||
@ -1581,11 +1581,6 @@ ifneq ($(cmd_files),)
|
||||
include $(cmd_files)
|
||||
endif
|
||||
|
||||
# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.clean obj=dir
|
||||
# Usage:
|
||||
# $(Q)$(MAKE) $(clean)=dir
|
||||
clean := -f $(srctree)/scripts/Makefile.clean obj
|
||||
|
||||
endif # skip-makefile
|
||||
|
||||
PHONY += FORCE
|
||||
|
@ -177,6 +177,9 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \
|
||||
dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
|
||||
dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
|
||||
dtb-$(CONFIG_MACH_MESON6) += meson6-atv1200.dtb
|
||||
dtb-$(CONFIG_ARCH_MMP) += pxa168-aspenite.dtb \
|
||||
pxa910-dkb.dtb \
|
||||
mmp2-brownstone.dtb
|
||||
dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb
|
||||
dtb-$(CONFIG_ARCH_MXC) += \
|
||||
imx1-ads.dtb \
|
||||
|
@ -8,7 +8,7 @@
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "mmp2.dtsi"
|
||||
#include "mmp2.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell MMP2 Brownstone Development Board";
|
||||
|
@ -7,7 +7,8 @@
|
||||
* publishhed by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
#include "skeleton.dtsi"
|
||||
#include <dt-bindings/clock/marvell,mmp2.h>
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
@ -135,6 +136,8 @@
|
||||
compatible = "mrvl,mmp-uart";
|
||||
reg = <0xd4030000 0x1000>;
|
||||
interrupts = <27>;
|
||||
clocks = <&soc_clocks MMP2_CLK_UART0>;
|
||||
resets = <&soc_clocks MMP2_CLK_UART0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -142,6 +145,8 @@
|
||||
compatible = "mrvl,mmp-uart";
|
||||
reg = <0xd4017000 0x1000>;
|
||||
interrupts = <28>;
|
||||
clocks = <&soc_clocks MMP2_CLK_UART1>;
|
||||
resets = <&soc_clocks MMP2_CLK_UART1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -149,6 +154,8 @@
|
||||
compatible = "mrvl,mmp-uart";
|
||||
reg = <0xd4018000 0x1000>;
|
||||
interrupts = <24>;
|
||||
clocks = <&soc_clocks MMP2_CLK_UART2>;
|
||||
resets = <&soc_clocks MMP2_CLK_UART2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -156,6 +163,8 @@
|
||||
compatible = "mrvl,mmp-uart";
|
||||
reg = <0xd4016000 0x1000>;
|
||||
interrupts = <46>;
|
||||
clocks = <&soc_clocks MMP2_CLK_UART3>;
|
||||
resets = <&soc_clocks MMP2_CLK_UART3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -168,6 +177,8 @@
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <49>;
|
||||
interrupt-names = "gpio_mux";
|
||||
clocks = <&soc_clocks MMP2_CLK_GPIO>;
|
||||
resets = <&soc_clocks MMP2_CLK_GPIO>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
@ -201,6 +212,8 @@
|
||||
compatible = "mrvl,mmp-twsi";
|
||||
reg = <0xd4011000 0x1000>;
|
||||
interrupts = <7>;
|
||||
clocks = <&soc_clocks MMP2_CLK_TWSI0>;
|
||||
resets = <&soc_clocks MMP2_CLK_TWSI0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
mrvl,i2c-fast-mode;
|
||||
@ -211,6 +224,8 @@
|
||||
compatible = "mrvl,mmp-twsi";
|
||||
reg = <0xd4025000 0x1000>;
|
||||
interrupts = <58>;
|
||||
clocks = <&soc_clocks MMP2_CLK_TWSI1>;
|
||||
resets = <&soc_clocks MMP2_CLK_TWSI1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -220,8 +235,20 @@
|
||||
interrupts = <1 0>;
|
||||
interrupt-names = "rtc 1Hz", "rtc alarm";
|
||||
interrupt-parent = <&intcmux5>;
|
||||
clocks = <&soc_clocks MMP2_CLK_RTC>;
|
||||
resets = <&soc_clocks MMP2_CLK_RTC>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
soc_clocks: clocks{
|
||||
compatible = "marvell,mmp2-clock";
|
||||
reg = <0xd4050000 0x1000>,
|
||||
<0xd4282800 0x400>,
|
||||
<0xd4015000 0x1000>;
|
||||
reg-names = "mpmu", "apmu", "apbc";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
@ -8,7 +8,7 @@
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "pxa168.dtsi"
|
||||
#include "pxa168.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell PXA168 Aspenite Development Board";
|
||||
|
@ -7,7 +7,8 @@
|
||||
* publishhed by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
#include "skeleton.dtsi"
|
||||
#include <dt-bindings/clock/marvell,pxa168.h>
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
@ -59,6 +60,8 @@
|
||||
compatible = "mrvl,mmp-uart";
|
||||
reg = <0xd4017000 0x1000>;
|
||||
interrupts = <27>;
|
||||
clocks = <&soc_clocks PXA168_CLK_UART0>;
|
||||
resets = <&soc_clocks PXA168_CLK_UART0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -66,6 +69,8 @@
|
||||
compatible = "mrvl,mmp-uart";
|
||||
reg = <0xd4018000 0x1000>;
|
||||
interrupts = <28>;
|
||||
clocks = <&soc_clocks PXA168_CLK_UART1>;
|
||||
resets = <&soc_clocks PXA168_CLK_UART1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -73,6 +78,8 @@
|
||||
compatible = "mrvl,mmp-uart";
|
||||
reg = <0xd4026000 0x1000>;
|
||||
interrupts = <29>;
|
||||
clocks = <&soc_clocks PXA168_CLK_UART2>;
|
||||
resets = <&soc_clocks PXA168_CLK_UART2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -84,6 +91,8 @@
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <49>;
|
||||
clocks = <&soc_clocks PXA168_CLK_GPIO>;
|
||||
resets = <&soc_clocks PXA168_CLK_GPIO>;
|
||||
interrupt-names = "gpio_mux";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
@ -110,6 +119,8 @@
|
||||
compatible = "mrvl,mmp-twsi";
|
||||
reg = <0xd4011000 0x1000>;
|
||||
interrupts = <7>;
|
||||
clocks = <&soc_clocks PXA168_CLK_TWSI0>;
|
||||
resets = <&soc_clocks PXA168_CLK_TWSI0>;
|
||||
mrvl,i2c-fast-mode;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -118,6 +129,8 @@
|
||||
compatible = "mrvl,mmp-twsi";
|
||||
reg = <0xd4025000 0x1000>;
|
||||
interrupts = <58>;
|
||||
clocks = <&soc_clocks PXA168_CLK_TWSI1>;
|
||||
resets = <&soc_clocks PXA168_CLK_TWSI1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -126,8 +139,20 @@
|
||||
reg = <0xd4010000 0x1000>;
|
||||
interrupts = <5 6>;
|
||||
interrupt-names = "rtc 1Hz", "rtc alarm";
|
||||
clocks = <&soc_clocks PXA168_CLK_RTC>;
|
||||
resets = <&soc_clocks PXA168_CLK_RTC>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
soc_clocks: clocks{
|
||||
compatible = "marvell,pxa168-clock";
|
||||
reg = <0xd4050000 0x1000>,
|
||||
<0xd4282800 0x400>,
|
||||
<0xd4015000 0x1000>;
|
||||
reg-names = "mpmu", "apmu", "apbc";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
@ -8,7 +8,7 @@
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "pxa910.dtsi"
|
||||
#include "pxa910.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell PXA910 DKB Development Board";
|
||||
|
@ -7,7 +7,8 @@
|
||||
* publishhed by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
#include "skeleton.dtsi"
|
||||
#include <dt-bindings/clock/marvell,pxa910.h>
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
@ -71,6 +72,8 @@
|
||||
compatible = "mrvl,mmp-uart";
|
||||
reg = <0xd4017000 0x1000>;
|
||||
interrupts = <27>;
|
||||
clocks = <&soc_clocks PXA910_CLK_UART0>;
|
||||
resets = <&soc_clocks PXA910_CLK_UART0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -78,6 +81,8 @@
|
||||
compatible = "mrvl,mmp-uart";
|
||||
reg = <0xd4018000 0x1000>;
|
||||
interrupts = <28>;
|
||||
clocks = <&soc_clocks PXA910_CLK_UART1>;
|
||||
resets = <&soc_clocks PXA910_CLK_UART1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -85,6 +90,8 @@
|
||||
compatible = "mrvl,mmp-uart";
|
||||
reg = <0xd4036000 0x1000>;
|
||||
interrupts = <59>;
|
||||
clocks = <&soc_clocks PXA910_CLK_UART2>;
|
||||
resets = <&soc_clocks PXA910_CLK_UART2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -97,6 +104,8 @@
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <49>;
|
||||
interrupt-names = "gpio_mux";
|
||||
clocks = <&soc_clocks PXA910_CLK_GPIO>;
|
||||
resets = <&soc_clocks PXA910_CLK_GPIO>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
@ -124,6 +133,8 @@
|
||||
#size-cells = <0>;
|
||||
reg = <0xd4011000 0x1000>;
|
||||
interrupts = <7>;
|
||||
clocks = <&soc_clocks PXA910_CLK_TWSI0>;
|
||||
resets = <&soc_clocks PXA910_CLK_TWSI0>;
|
||||
mrvl,i2c-fast-mode;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -134,6 +145,8 @@
|
||||
#size-cells = <0>;
|
||||
reg = <0xd4037000 0x1000>;
|
||||
interrupts = <54>;
|
||||
clocks = <&soc_clocks PXA910_CLK_TWSI1>;
|
||||
resets = <&soc_clocks PXA910_CLK_TWSI1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -142,8 +155,21 @@
|
||||
reg = <0xd4010000 0x1000>;
|
||||
interrupts = <5 6>;
|
||||
interrupt-names = "rtc 1Hz", "rtc alarm";
|
||||
clocks = <&soc_clocks PXA910_CLK_RTC>;
|
||||
resets = <&soc_clocks PXA910_CLK_RTC>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
soc_clocks: clocks{
|
||||
compatible = "marvell,pxa910-clock";
|
||||
reg = <0xd4050000 0x1000>,
|
||||
<0xd4282800 0x400>,
|
||||
<0xd4015000 0x1000>,
|
||||
<0xd403b000 0x1000>;
|
||||
reg-names = "mpmu", "apmu", "apbc", "apbcp";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
@ -188,19 +188,11 @@
|
||||
"apb0_ir1", "apb0_keypad";
|
||||
};
|
||||
|
||||
apb1_mux: apb1_mux@01c20058 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-apb1-mux-clk";
|
||||
reg = <0x01c20058 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
|
||||
clock-output-names = "apb1_mux";
|
||||
};
|
||||
|
||||
apb1: apb1@01c20058 {
|
||||
apb1: clk@01c20058 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-apb1-clk";
|
||||
reg = <0x01c20058 0x4>;
|
||||
clocks = <&apb1_mux>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
|
||||
clock-output-names = "apb1";
|
||||
};
|
||||
|
||||
|
@ -176,19 +176,11 @@
|
||||
"apb0_ir", "apb0_keypad";
|
||||
};
|
||||
|
||||
apb1_mux: apb1_mux@01c20058 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-apb1-mux-clk";
|
||||
reg = <0x01c20058 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
|
||||
clock-output-names = "apb1_mux";
|
||||
};
|
||||
|
||||
apb1: apb1@01c20058 {
|
||||
apb1: clk@01c20058 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-apb1-clk";
|
||||
reg = <0x01c20058 0x4>;
|
||||
clocks = <&apb1_mux>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
|
||||
clock-output-names = "apb1";
|
||||
};
|
||||
|
||||
|
@ -161,19 +161,11 @@
|
||||
clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
|
||||
};
|
||||
|
||||
apb1_mux: apb1_mux@01c20058 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-apb1-mux-clk";
|
||||
reg = <0x01c20058 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
|
||||
clock-output-names = "apb1_mux";
|
||||
};
|
||||
|
||||
apb1: apb1@01c20058 {
|
||||
apb1: clk@01c20058 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-apb1-clk";
|
||||
reg = <0x01c20058 0x4>;
|
||||
clocks = <&apb1_mux>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
|
||||
clock-output-names = "apb1";
|
||||
};
|
||||
|
||||
|
@ -229,19 +229,11 @@
|
||||
"apb1_daudio1";
|
||||
};
|
||||
|
||||
apb2_mux: apb2_mux@01c20058 {
|
||||
apb2: clk@01c20058 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-apb1-mux-clk";
|
||||
compatible = "allwinner,sun4i-a10-apb1-clk";
|
||||
reg = <0x01c20058 0x4>;
|
||||
clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
|
||||
clock-output-names = "apb2_mux";
|
||||
};
|
||||
|
||||
apb2: apb2@01c20058 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun6i-a31-apb2-div-clk";
|
||||
reg = <0x01c20058 0x4>;
|
||||
clocks = <&apb2_mux>;
|
||||
clock-output-names = "apb2";
|
||||
};
|
||||
|
||||
|
@ -236,19 +236,11 @@
|
||||
"apb0_iis2", "apb0_keypad";
|
||||
};
|
||||
|
||||
apb1_mux: apb1_mux@01c20058 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-apb1-mux-clk";
|
||||
reg = <0x01c20058 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
|
||||
clock-output-names = "apb1_mux";
|
||||
};
|
||||
|
||||
apb1: apb1@01c20058 {
|
||||
apb1: clk@01c20058 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-apb1-clk";
|
||||
reg = <0x01c20058 0x4>;
|
||||
clocks = <&apb1_mux>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
|
||||
clock-output-names = "apb1";
|
||||
};
|
||||
|
||||
|
@ -189,19 +189,11 @@
|
||||
"apb1_daudio0", "apb1_daudio1";
|
||||
};
|
||||
|
||||
apb2_mux: apb2_mux_clk@01c20058 {
|
||||
apb2: clk@01c20058 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-apb1-mux-clk";
|
||||
compatible = "allwinner,sun4i-a10-apb1-clk";
|
||||
reg = <0x01c20058 0x4>;
|
||||
clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
|
||||
clock-output-names = "apb2_mux";
|
||||
};
|
||||
|
||||
apb2: apb2_clk@01c20058 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun6i-a31-apb2-div-clk";
|
||||
reg = <0x01c20058 0x4>;
|
||||
clocks = <&apb2_mux>;
|
||||
clock-output-names = "apb2";
|
||||
};
|
||||
|
||||
|
@ -33,7 +33,7 @@ CONFIG_ARM_APPENDED_DTB=y
|
||||
CONFIG_VFP=y
|
||||
CONFIG_NEON=y
|
||||
CONFIG_BINFMT_MISC=y
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
|
@ -43,7 +43,7 @@ CONFIG_KEXEC=y
|
||||
CONFIG_VFP=y
|
||||
CONFIG_NEON=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
|
@ -39,7 +39,7 @@ CONFIG_CPU_IDLE=y
|
||||
CONFIG_VFP=y
|
||||
CONFIG_NEON=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_PACKET_DIAG=y
|
||||
|
@ -29,7 +29,7 @@ CONFIG_ZBOOT_ROM_BSS=0x0
|
||||
CONFIG_ARM_APPENDED_DTB=y
|
||||
CONFIG_VFP=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
|
@ -49,7 +49,7 @@ CONFIG_CPU_FREQ_GOV_PERFORMANCE=m
|
||||
CONFIG_CPU_FREQ_GOV_POWERSAVE=m
|
||||
CONFIG_CPU_FREQ_GOV_ONDEMAND=m
|
||||
CONFIG_CPU_IDLE=y
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
|
@ -27,7 +27,7 @@ CONFIG_ARM_ATAG_DTB_COMPAT=y
|
||||
CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc mem=256M"
|
||||
CONFIG_VFP=y
|
||||
CONFIG_NEON=y
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
|
@ -39,7 +39,6 @@ CONFIG_BINFMT_AOUT=m
|
||||
CONFIG_BINFMT_MISC=m
|
||||
CONFIG_PM=y
|
||||
CONFIG_APM_EMULATION=y
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
|
@ -18,7 +18,7 @@ CONFIG_ARM_APPENDED_DTB=y
|
||||
CONFIG_ARM_ATAG_DTB_COMPAT=y
|
||||
CONFIG_NEON=y
|
||||
CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
|
@ -31,7 +31,6 @@ CONFIG_BINFMT_AOUT=m
|
||||
CONFIG_BINFMT_MISC=m
|
||||
CONFIG_PM=y
|
||||
CONFIG_APM_EMULATION=y
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
|
@ -54,7 +54,7 @@ CONFIG_ARM_IMX6Q_CPUFREQ=y
|
||||
CONFIG_VFP=y
|
||||
CONFIG_NEON=y
|
||||
CONFIG_BINFMT_MISC=m
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_PM_DEBUG=y
|
||||
CONFIG_PM_TEST_SUSPEND=y
|
||||
CONFIG_NET=y
|
||||
|
@ -30,7 +30,7 @@ CONFIG_HIGHMEM=y
|
||||
CONFIG_VFP=y
|
||||
CONFIG_NEON=y
|
||||
# CONFIG_SUSPEND is not set
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
|
@ -43,7 +43,7 @@ CONFIG_KEXEC=y
|
||||
CONFIG_VFP=y
|
||||
CONFIG_NEON=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
|
@ -37,7 +37,7 @@ CONFIG_AUTO_ZRELADDR=y
|
||||
CONFIG_VFP=y
|
||||
CONFIG_NEON=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
|
@ -28,7 +28,6 @@ CONFIG_KEXEC=y
|
||||
CONFIG_VFP=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
CONFIG_PM=y
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
|
@ -33,7 +33,7 @@ CONFIG_ARM_APPENDED_DTB=y
|
||||
CONFIG_VFP=y
|
||||
CONFIG_KEXEC=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
|
@ -63,7 +63,6 @@ CONFIG_FPE_NWFPE=y
|
||||
CONFIG_BINFMT_MISC=y
|
||||
CONFIG_PM=y
|
||||
# CONFIG_SUSPEND is not set
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
|
@ -18,7 +18,7 @@ CONFIG_PREEMPT=y
|
||||
CONFIG_AEABI=y
|
||||
CONFIG_KEXEC=y
|
||||
CONFIG_BINFMT_MISC=y
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
|
@ -32,7 +32,7 @@ CONFIG_VFP=y
|
||||
CONFIG_NEON=y
|
||||
CONFIG_KERNEL_MODE_NEON=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_PM_DEBUG=y
|
||||
CONFIG_PM_ADVANCED_DEBUG=y
|
||||
CONFIG_NET=y
|
||||
|
@ -39,7 +39,7 @@ CONFIG_KEXEC=y
|
||||
CONFIG_VFP=y
|
||||
CONFIG_NEON=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
|
@ -11,7 +11,7 @@ CONFIG_ARM_APPENDED_DTB=y
|
||||
CONFIG_ARM_ATAG_DTB_COMPAT=y
|
||||
CONFIG_VFP=y
|
||||
CONFIG_NEON=y
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
|
@ -46,7 +46,7 @@ CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
|
||||
CONFIG_CPU_IDLE=y
|
||||
CONFIG_VFP=y
|
||||
CONFIG_NEON=y
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
|
@ -25,7 +25,7 @@ CONFIG_CPU_IDLE=y
|
||||
CONFIG_ARM_U8500_CPUIDLE=y
|
||||
CONFIG_VFP=y
|
||||
CONFIG_NEON=y
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
|
@ -16,7 +16,7 @@ CONFIG_ARM_APPENDED_DTB=y
|
||||
CONFIG_ARM_ATAG_DTB_COMPAT=y
|
||||
CONFIG_VFP=y
|
||||
CONFIG_NEON=y
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
|
@ -120,12 +120,12 @@ static inline int arch_spin_value_unlocked(arch_spinlock_t lock)
|
||||
|
||||
static inline int arch_spin_is_locked(arch_spinlock_t *lock)
|
||||
{
|
||||
return !arch_spin_value_unlocked(ACCESS_ONCE(*lock));
|
||||
return !arch_spin_value_unlocked(READ_ONCE(*lock));
|
||||
}
|
||||
|
||||
static inline int arch_spin_is_contended(arch_spinlock_t *lock)
|
||||
{
|
||||
struct __raw_tickets tickets = ACCESS_ONCE(lock->tickets);
|
||||
struct __raw_tickets tickets = READ_ONCE(lock->tickets);
|
||||
return (tickets.next - tickets.owner) > 1;
|
||||
}
|
||||
#define arch_spin_is_contended arch_spin_is_contended
|
||||
|
@ -86,11 +86,12 @@ config MACH_GPLUGD
|
||||
|
||||
config MACH_MMP_DT
|
||||
bool "Support MMP (ARMv5) platforms from device tree"
|
||||
select CPU_PXA168
|
||||
select CPU_PXA910
|
||||
select USE_OF
|
||||
select PINCTRL
|
||||
select PINCTRL_SINGLE
|
||||
select COMMON_CLK
|
||||
select ARCH_HAS_RESET_CONTROLLER
|
||||
select CPU_MOHAWK
|
||||
help
|
||||
Include support for Marvell MMP2 based platforms using
|
||||
the device tree. Needn't select any other machine while
|
||||
@ -99,10 +100,12 @@ config MACH_MMP_DT
|
||||
config MACH_MMP2_DT
|
||||
bool "Support MMP2 (ARMv7) platforms from device tree"
|
||||
depends on !CPU_MOHAWK
|
||||
select CPU_MMP2
|
||||
select USE_OF
|
||||
select PINCTRL
|
||||
select PINCTRL_SINGLE
|
||||
select COMMON_CLK
|
||||
select ARCH_HAS_RESET_CONTROLLER
|
||||
select CPU_PJ4
|
||||
help
|
||||
Include support for Marvell MMP2 based platforms using
|
||||
the device tree.
|
||||
@ -111,21 +114,18 @@ endmenu
|
||||
|
||||
config CPU_PXA168
|
||||
bool
|
||||
select COMMON_CLK
|
||||
select CPU_MOHAWK
|
||||
help
|
||||
Select code specific to PXA168
|
||||
|
||||
config CPU_PXA910
|
||||
bool
|
||||
select COMMON_CLK
|
||||
select CPU_MOHAWK
|
||||
help
|
||||
Select code specific to PXA910
|
||||
|
||||
config CPU_MMP2
|
||||
bool
|
||||
select COMMON_CLK
|
||||
select CPU_PJ4
|
||||
help
|
||||
Select code specific to MMP2. MMP2 is ARMv7 compatible.
|
||||
|
@ -11,63 +11,42 @@
|
||||
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/hardware/cache-tauros2.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
extern void __init mmp_dt_init_timer(void);
|
||||
|
||||
static const struct of_dev_auxdata pxa168_auxdata_lookup[] __initconst = {
|
||||
OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.0", NULL),
|
||||
OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.1", NULL),
|
||||
OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4026000, "pxa2xx-uart.2", NULL),
|
||||
OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
|
||||
OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4025000, "pxa2xx-i2c.1", NULL),
|
||||
OF_DEV_AUXDATA("marvell,mmp-gpio", 0xd4019000, "mmp-gpio", NULL),
|
||||
OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
|
||||
{}
|
||||
};
|
||||
|
||||
static const struct of_dev_auxdata pxa910_auxdata_lookup[] __initconst = {
|
||||
OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.0", NULL),
|
||||
OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.1", NULL),
|
||||
OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4036000, "pxa2xx-uart.2", NULL),
|
||||
OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
|
||||
OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4037000, "pxa2xx-i2c.1", NULL),
|
||||
OF_DEV_AUXDATA("marvell,mmp-gpio", 0xd4019000, "mmp-gpio", NULL),
|
||||
OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
|
||||
{}
|
||||
};
|
||||
|
||||
static void __init pxa168_dt_init(void)
|
||||
{
|
||||
of_platform_populate(NULL, of_default_bus_match_table,
|
||||
pxa168_auxdata_lookup, NULL);
|
||||
}
|
||||
|
||||
static void __init pxa910_dt_init(void)
|
||||
{
|
||||
of_platform_populate(NULL, of_default_bus_match_table,
|
||||
pxa910_auxdata_lookup, NULL);
|
||||
}
|
||||
|
||||
static const char *mmp_dt_board_compat[] __initdata = {
|
||||
static const char *pxa168_dt_board_compat[] __initdata = {
|
||||
"mrvl,pxa168-aspenite",
|
||||
NULL,
|
||||
};
|
||||
|
||||
static const char *pxa910_dt_board_compat[] __initdata = {
|
||||
"mrvl,pxa910-dkb",
|
||||
NULL,
|
||||
};
|
||||
|
||||
static void __init mmp_init_time(void)
|
||||
{
|
||||
#ifdef CONFIG_CACHE_TAUROS2
|
||||
tauros2_init(0);
|
||||
#endif
|
||||
mmp_dt_init_timer();
|
||||
of_clk_init(NULL);
|
||||
}
|
||||
|
||||
DT_MACHINE_START(PXA168_DT, "Marvell PXA168 (Device Tree Support)")
|
||||
.map_io = mmp_map_io,
|
||||
.init_time = mmp_dt_init_timer,
|
||||
.init_machine = pxa168_dt_init,
|
||||
.dt_compat = mmp_dt_board_compat,
|
||||
.init_time = mmp_init_time,
|
||||
.dt_compat = pxa168_dt_board_compat,
|
||||
MACHINE_END
|
||||
|
||||
DT_MACHINE_START(PXA910_DT, "Marvell PXA910 (Device Tree Support)")
|
||||
.map_io = mmp_map_io,
|
||||
.init_time = mmp_dt_init_timer,
|
||||
.init_machine = pxa910_dt_init,
|
||||
.dt_compat = mmp_dt_board_compat,
|
||||
.init_time = mmp_init_time,
|
||||
.dt_compat = pxa910_dt_board_compat,
|
||||
MACHINE_END
|
||||
|
@ -12,29 +12,22 @@
|
||||
#include <linux/io.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/hardware/cache-tauros2.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
extern void __init mmp_dt_init_timer(void);
|
||||
|
||||
static const struct of_dev_auxdata mmp2_auxdata_lookup[] __initconst = {
|
||||
OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4030000, "pxa2xx-uart.0", NULL),
|
||||
OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.1", NULL),
|
||||
OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.2", NULL),
|
||||
OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4016000, "pxa2xx-uart.3", NULL),
|
||||
OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
|
||||
OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4025000, "pxa2xx-i2c.1", NULL),
|
||||
OF_DEV_AUXDATA("marvell,mmp-gpio", 0xd4019000, "mmp2-gpio", NULL),
|
||||
OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
|
||||
{}
|
||||
};
|
||||
|
||||
static void __init mmp2_dt_init(void)
|
||||
static void __init mmp_init_time(void)
|
||||
{
|
||||
of_platform_populate(NULL, of_default_bus_match_table,
|
||||
mmp2_auxdata_lookup, NULL);
|
||||
#ifdef CONFIG_CACHE_TAUROS2
|
||||
tauros2_init(0);
|
||||
#endif
|
||||
mmp_dt_init_timer();
|
||||
of_clk_init(NULL);
|
||||
}
|
||||
|
||||
static const char *mmp2_dt_board_compat[] __initdata = {
|
||||
@ -44,7 +37,6 @@ static const char *mmp2_dt_board_compat[] __initdata = {
|
||||
|
||||
DT_MACHINE_START(MMP2_DT, "Marvell MMP2 (Device Tree Support)")
|
||||
.map_io = mmp_map_io,
|
||||
.init_time = mmp_dt_init_timer,
|
||||
.init_machine = mmp2_dt_init,
|
||||
.init_time = mmp_init_time,
|
||||
.dt_compat = mmp2_dt_board_compat,
|
||||
MACHINE_END
|
||||
|
@ -15,7 +15,7 @@ config ARCH_OMAP3
|
||||
select ARM_CPU_SUSPEND if PM
|
||||
select OMAP_INTERCONNECT
|
||||
select PM_OPP if PM
|
||||
select PM_RUNTIME if CPU_IDLE
|
||||
select PM if CPU_IDLE
|
||||
select SOC_HAS_OMAP2_SDRC
|
||||
|
||||
config ARCH_OMAP4
|
||||
@ -32,7 +32,7 @@ config ARCH_OMAP4
|
||||
select PL310_ERRATA_588369 if CACHE_L2X0
|
||||
select PL310_ERRATA_727915 if CACHE_L2X0
|
||||
select PM_OPP if PM
|
||||
select PM_RUNTIME if CPU_IDLE
|
||||
select PM if CPU_IDLE
|
||||
select ARM_ERRATA_754322
|
||||
select ARM_ERRATA_775420
|
||||
|
||||
@ -103,7 +103,7 @@ config ARCH_OMAP2PLUS_TYPICAL
|
||||
select I2C_OMAP
|
||||
select MENELAUS if ARCH_OMAP2
|
||||
select NEON if CPU_V7
|
||||
select PM_RUNTIME
|
||||
select PM
|
||||
select REGULATOR
|
||||
select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4
|
||||
select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4
|
||||
|
@ -111,6 +111,7 @@ static struct clk dpll3_ck;
|
||||
|
||||
static const char *dpll3_ck_parent_names[] = {
|
||||
"sys_ck",
|
||||
"sys_ck",
|
||||
};
|
||||
|
||||
static const struct clk_ops dpll3_ck_ops = {
|
||||
@ -733,6 +734,10 @@ static const char *corex2_fck_parent_names[] = {
|
||||
DEFINE_STRUCT_CLK_HW_OMAP(corex2_fck, NULL);
|
||||
DEFINE_STRUCT_CLK(corex2_fck, corex2_fck_parent_names, core_ck_ops);
|
||||
|
||||
static const char *cpefuse_fck_parent_names[] = {
|
||||
"sys_ck",
|
||||
};
|
||||
|
||||
static struct clk cpefuse_fck;
|
||||
|
||||
static struct clk_hw_omap cpefuse_fck_hw = {
|
||||
@ -744,7 +749,7 @@ static struct clk_hw_omap cpefuse_fck_hw = {
|
||||
.clkdm_name = "core_l4_clkdm",
|
||||
};
|
||||
|
||||
DEFINE_STRUCT_CLK(cpefuse_fck, dpll3_ck_parent_names, aes2_ick_ops);
|
||||
DEFINE_STRUCT_CLK(cpefuse_fck, cpefuse_fck_parent_names, aes2_ick_ops);
|
||||
|
||||
static struct clk csi2_96m_fck;
|
||||
|
||||
@ -775,7 +780,7 @@ static struct clk_hw_omap d2d_26m_fck_hw = {
|
||||
.clkdm_name = "d2d_clkdm",
|
||||
};
|
||||
|
||||
DEFINE_STRUCT_CLK(d2d_26m_fck, dpll3_ck_parent_names, aes2_ick_ops);
|
||||
DEFINE_STRUCT_CLK(d2d_26m_fck, cpefuse_fck_parent_names, aes2_ick_ops);
|
||||
|
||||
static struct clk des1_ick;
|
||||
|
||||
@ -1046,7 +1051,7 @@ static struct clk_hw_omap dss2_alwon_fck_hw = {
|
||||
.clkdm_name = "dss_clkdm",
|
||||
};
|
||||
|
||||
DEFINE_STRUCT_CLK(dss2_alwon_fck, dpll3_ck_parent_names, aes2_ick_ops);
|
||||
DEFINE_STRUCT_CLK(dss2_alwon_fck, cpefuse_fck_parent_names, aes2_ick_ops);
|
||||
|
||||
static struct clk dss_96m_fck;
|
||||
|
||||
@ -1368,7 +1373,7 @@ DEFINE_STRUCT_CLK(gpio1_dbck, gpio1_dbck_parent_names, aes2_ick_ops);
|
||||
static struct clk wkup_l4_ick;
|
||||
|
||||
DEFINE_STRUCT_CLK_HW_OMAP(wkup_l4_ick, "wkup_clkdm");
|
||||
DEFINE_STRUCT_CLK(wkup_l4_ick, dpll3_ck_parent_names, core_l4_ick_ops);
|
||||
DEFINE_STRUCT_CLK(wkup_l4_ick, cpefuse_fck_parent_names, core_l4_ick_ops);
|
||||
|
||||
static struct clk gpio1_ick;
|
||||
|
||||
@ -1862,7 +1867,7 @@ static struct clk_hw_omap hecc_ck_hw = {
|
||||
.clkdm_name = "core_l3_clkdm",
|
||||
};
|
||||
|
||||
DEFINE_STRUCT_CLK(hecc_ck, dpll3_ck_parent_names, aes2_ick_ops);
|
||||
DEFINE_STRUCT_CLK(hecc_ck, cpefuse_fck_parent_names, aes2_ick_ops);
|
||||
|
||||
static struct clk hsotgusb_fck_am35xx;
|
||||
|
||||
@ -1875,7 +1880,7 @@ static struct clk_hw_omap hsotgusb_fck_am35xx_hw = {
|
||||
.clkdm_name = "core_l3_clkdm",
|
||||
};
|
||||
|
||||
DEFINE_STRUCT_CLK(hsotgusb_fck_am35xx, dpll3_ck_parent_names, aes2_ick_ops);
|
||||
DEFINE_STRUCT_CLK(hsotgusb_fck_am35xx, cpefuse_fck_parent_names, aes2_ick_ops);
|
||||
|
||||
static struct clk hsotgusb_ick_3430es1;
|
||||
|
||||
@ -2411,7 +2416,7 @@ static struct clk_hw_omap modem_fck_hw = {
|
||||
.clkdm_name = "d2d_clkdm",
|
||||
};
|
||||
|
||||
DEFINE_STRUCT_CLK(modem_fck, dpll3_ck_parent_names, aes2_ick_ops);
|
||||
DEFINE_STRUCT_CLK(modem_fck, cpefuse_fck_parent_names, aes2_ick_ops);
|
||||
|
||||
static struct clk mspro_fck;
|
||||
|
||||
@ -2710,7 +2715,7 @@ static struct clk_hw_omap sr1_fck_hw = {
|
||||
.clkdm_name = "wkup_clkdm",
|
||||
};
|
||||
|
||||
DEFINE_STRUCT_CLK(sr1_fck, dpll3_ck_parent_names, aes2_ick_ops);
|
||||
DEFINE_STRUCT_CLK(sr1_fck, cpefuse_fck_parent_names, aes2_ick_ops);
|
||||
|
||||
static struct clk sr2_fck;
|
||||
|
||||
@ -2724,7 +2729,7 @@ static struct clk_hw_omap sr2_fck_hw = {
|
||||
.clkdm_name = "wkup_clkdm",
|
||||
};
|
||||
|
||||
DEFINE_STRUCT_CLK(sr2_fck, dpll3_ck_parent_names, aes2_ick_ops);
|
||||
DEFINE_STRUCT_CLK(sr2_fck, cpefuse_fck_parent_names, aes2_ick_ops);
|
||||
|
||||
static struct clk sr_l4_ick;
|
||||
|
||||
|
@ -474,7 +474,7 @@ void omap3_noncore_dpll_disable(struct clk_hw *hw)
|
||||
*/
|
||||
long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *best_parent_rate,
|
||||
struct clk **best_parent_clk)
|
||||
struct clk_hw **best_parent_clk)
|
||||
{
|
||||
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
|
||||
struct dpll_data *dd;
|
||||
@ -488,10 +488,10 @@ long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, unsigned long rate,
|
||||
|
||||
if (__clk_get_rate(dd->clk_bypass) == rate &&
|
||||
(dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
|
||||
*best_parent_clk = dd->clk_bypass;
|
||||
*best_parent_clk = __clk_get_hw(dd->clk_bypass);
|
||||
} else {
|
||||
rate = omap2_dpll_round_rate(hw, rate, best_parent_rate);
|
||||
*best_parent_clk = dd->clk_ref;
|
||||
*best_parent_clk = __clk_get_hw(dd->clk_ref);
|
||||
}
|
||||
|
||||
*best_parent_rate = rate;
|
||||
|
@ -223,7 +223,7 @@ out:
|
||||
*/
|
||||
long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *best_parent_rate,
|
||||
struct clk **best_parent_clk)
|
||||
struct clk_hw **best_parent_clk)
|
||||
{
|
||||
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
|
||||
struct dpll_data *dd;
|
||||
@ -237,11 +237,11 @@ long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, unsigned long rate,
|
||||
|
||||
if (__clk_get_rate(dd->clk_bypass) == rate &&
|
||||
(dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
|
||||
*best_parent_clk = dd->clk_bypass;
|
||||
*best_parent_clk = __clk_get_hw(dd->clk_bypass);
|
||||
} else {
|
||||
rate = omap4_dpll_regm4xen_round_rate(hw, rate,
|
||||
best_parent_rate);
|
||||
*best_parent_clk = dd->clk_ref;
|
||||
*best_parent_clk = __clk_get_hw(dd->clk_ref);
|
||||
}
|
||||
|
||||
*best_parent_rate = rate;
|
||||
|
@ -1,6 +1,7 @@
|
||||
# CONFIG_LOCALVERSION_AUTO is not set
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
CONFIG_FHANDLE=y
|
||||
CONFIG_AUDIT=y
|
||||
CONFIG_NO_HZ_IDLE=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
@ -13,14 +14,12 @@ CONFIG_TASK_IO_ACCOUNTING=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_RESOURCE_COUNTERS=y
|
||||
CONFIG_MEMCG=y
|
||||
CONFIG_MEMCG_SWAP=y
|
||||
CONFIG_MEMCG_KMEM=y
|
||||
CONFIG_CGROUP_HUGETLB=y
|
||||
# CONFIG_UTS_NS is not set
|
||||
# CONFIG_IPC_NS is not set
|
||||
# CONFIG_PID_NS is not set
|
||||
# CONFIG_NET_NS is not set
|
||||
CONFIG_SCHED_AUTOGROUP=y
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
@ -92,7 +91,6 @@ CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
CONFIG_VIRTIO_CONSOLE=y
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
# CONFIG_HMC_DRV is not set
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_PL022=y
|
||||
CONFIG_GPIO_PL061=y
|
||||
@ -133,6 +131,8 @@ CONFIG_EXT3_FS=y
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_FANOTIFY=y
|
||||
CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
|
||||
CONFIG_QUOTA=y
|
||||
CONFIG_AUTOFS4_FS=y
|
||||
CONFIG_FUSE_FS=y
|
||||
CONFIG_CUSE=y
|
||||
CONFIG_VFAT_FS=y
|
||||
@ -152,14 +152,15 @@ CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_DEBUG_KERNEL=y
|
||||
CONFIG_LOCKUP_DETECTOR=y
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
# CONFIG_DEBUG_PREEMPT is not set
|
||||
# CONFIG_FTRACE is not set
|
||||
CONFIG_KEYS=y
|
||||
CONFIG_SECURITY=y
|
||||
CONFIG_CRYPTO_ANSI_CPRNG=y
|
||||
CONFIG_ARM64_CRYPTO=y
|
||||
CONFIG_CRYPTO_SHA1_ARM64_CE=y
|
||||
CONFIG_CRYPTO_SHA2_ARM64_CE=y
|
||||
CONFIG_CRYPTO_GHASH_ARM64_CE=y
|
||||
CONFIG_CRYPTO_AES_ARM64_CE=y
|
||||
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
|
||||
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
|
||||
CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
|
||||
|
@ -52,13 +52,14 @@ static inline void set_dma_ops(struct device *dev, struct dma_map_ops *ops)
|
||||
dev->archdata.dma_ops = ops;
|
||||
}
|
||||
|
||||
static inline int set_arch_dma_coherent_ops(struct device *dev)
|
||||
static inline void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
|
||||
struct iommu_ops *iommu, bool coherent)
|
||||
{
|
||||
dev->archdata.dma_coherent = true;
|
||||
set_dma_ops(dev, &coherent_swiotlb_dma_ops);
|
||||
return 0;
|
||||
dev->archdata.dma_coherent = coherent;
|
||||
if (coherent)
|
||||
set_dma_ops(dev, &coherent_swiotlb_dma_ops);
|
||||
}
|
||||
#define set_arch_dma_coherent_ops set_arch_dma_coherent_ops
|
||||
#define arch_setup_dma_ops arch_setup_dma_ops
|
||||
|
||||
/* do not use this function in a driver */
|
||||
static inline bool is_device_dma_coherent(struct device *dev)
|
||||
|
@ -298,7 +298,6 @@ void pmdp_splitting_flush(struct vm_area_struct *vma, unsigned long address,
|
||||
#define pfn_pmd(pfn,prot) (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
|
||||
#define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot)
|
||||
|
||||
#define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK))
|
||||
#define pud_write(pud) pte_write(pud_pte(pud))
|
||||
#define pud_pfn(pud) (((pud_val(pud) & PUD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
|
||||
|
||||
@ -401,7 +400,7 @@ static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
|
||||
return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(addr);
|
||||
}
|
||||
|
||||
#define pud_page(pud) pmd_page(pud_pmd(pud))
|
||||
#define pud_page(pud) pfn_to_page(__phys_to_pfn(pud_val(pud) & PHYS_MASK))
|
||||
|
||||
#endif /* CONFIG_ARM64_PGTABLE_LEVELS > 2 */
|
||||
|
||||
@ -437,6 +436,8 @@ static inline pud_t *pud_offset(pgd_t *pgd, unsigned long addr)
|
||||
return (pud_t *)pgd_page_vaddr(*pgd) + pud_index(addr);
|
||||
}
|
||||
|
||||
#define pgd_page(pgd) pfn_to_page(__phys_to_pfn(pgd_val(pgd) & PHYS_MASK))
|
||||
|
||||
#endif /* CONFIG_ARM64_PGTABLE_LEVELS > 3 */
|
||||
|
||||
#define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd))
|
||||
|
@ -99,12 +99,12 @@ static inline int arch_spin_value_unlocked(arch_spinlock_t lock)
|
||||
|
||||
static inline int arch_spin_is_locked(arch_spinlock_t *lock)
|
||||
{
|
||||
return !arch_spin_value_unlocked(ACCESS_ONCE(*lock));
|
||||
return !arch_spin_value_unlocked(READ_ONCE(*lock));
|
||||
}
|
||||
|
||||
static inline int arch_spin_is_contended(arch_spinlock_t *lock)
|
||||
{
|
||||
arch_spinlock_t lockval = ACCESS_ONCE(*lock);
|
||||
arch_spinlock_t lockval = READ_ONCE(*lock);
|
||||
return (lockval.next - lockval.owner) > 1;
|
||||
}
|
||||
#define arch_spin_is_contended arch_spin_is_contended
|
||||
|
@ -5,6 +5,7 @@
|
||||
#include <asm/debug-monitors.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/memory.h>
|
||||
#include <asm/mmu_context.h>
|
||||
#include <asm/smp_plat.h>
|
||||
#include <asm/suspend.h>
|
||||
#include <asm/tlbflush.h>
|
||||
@ -98,7 +99,18 @@ int __cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
|
||||
*/
|
||||
ret = __cpu_suspend_enter(arg, fn);
|
||||
if (ret == 0) {
|
||||
cpu_switch_mm(mm->pgd, mm);
|
||||
/*
|
||||
* We are resuming from reset with TTBR0_EL1 set to the
|
||||
* idmap to enable the MMU; restore the active_mm mappings in
|
||||
* TTBR0_EL1 unless the active_mm == &init_mm, in which case
|
||||
* the thread entered __cpu_suspend with TTBR0_EL1 set to
|
||||
* reserved TTBR0 page tables and should be restored as such.
|
||||
*/
|
||||
if (mm == &init_mm)
|
||||
cpu_set_reserved_ttbr0();
|
||||
else
|
||||
cpu_switch_mm(mm->pgd, mm);
|
||||
|
||||
flush_tlb_all();
|
||||
|
||||
/*
|
||||
|
@ -374,7 +374,7 @@ static long alchemy_calc_div(unsigned long rate, unsigned long prate,
|
||||
|
||||
static long alchemy_clk_fgcs_detr(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *best_parent_rate,
|
||||
struct clk **best_parent_clk,
|
||||
struct clk_hw **best_parent_clk,
|
||||
int scale, int maxdiv)
|
||||
{
|
||||
struct clk *pc, *bpc, *free;
|
||||
@ -453,7 +453,7 @@ static long alchemy_clk_fgcs_detr(struct clk_hw *hw, unsigned long rate,
|
||||
}
|
||||
|
||||
*best_parent_rate = bpr;
|
||||
*best_parent_clk = bpc;
|
||||
*best_parent_clk = __clk_get_hw(bpc);
|
||||
return br;
|
||||
}
|
||||
|
||||
@ -547,7 +547,7 @@ static unsigned long alchemy_clk_fgv1_recalc(struct clk_hw *hw,
|
||||
|
||||
static long alchemy_clk_fgv1_detr(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *best_parent_rate,
|
||||
struct clk **best_parent_clk)
|
||||
struct clk_hw **best_parent_clk)
|
||||
{
|
||||
return alchemy_clk_fgcs_detr(hw, rate, best_parent_rate,
|
||||
best_parent_clk, 2, 512);
|
||||
@ -679,7 +679,7 @@ static unsigned long alchemy_clk_fgv2_recalc(struct clk_hw *hw,
|
||||
|
||||
static long alchemy_clk_fgv2_detr(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *best_parent_rate,
|
||||
struct clk **best_parent_clk)
|
||||
struct clk_hw **best_parent_clk)
|
||||
{
|
||||
struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
|
||||
int scale, maxdiv;
|
||||
@ -898,7 +898,7 @@ static int alchemy_clk_csrc_setr(struct clk_hw *hw, unsigned long rate,
|
||||
|
||||
static long alchemy_clk_csrc_detr(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *best_parent_rate,
|
||||
struct clk **best_parent_clk)
|
||||
struct clk_hw **best_parent_clk)
|
||||
{
|
||||
struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
|
||||
int scale = c->dt[2] == 3 ? 1 : 2; /* au1300 check */
|
||||
|
@ -36,7 +36,7 @@ CONFIG_PCI=y
|
||||
CONFIG_PCI_REALLOC_ENABLE_AUTO=y
|
||||
CONFIG_PCCARD=y
|
||||
CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_PACKET_DIAG=y
|
||||
|
@ -37,7 +37,6 @@ CONFIG_MIPS32_N32=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_HIBERNATION=y
|
||||
CONFIG_PM_STD_PARTITION="/dev/hda3"
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_CPU_FREQ=y
|
||||
CONFIG_CPU_FREQ_DEBUG=y
|
||||
CONFIG_CPU_FREQ_STAT=m
|
||||
|
@ -58,7 +58,7 @@ CONFIG_BINFMT_MISC=m
|
||||
CONFIG_MIPS32_COMPAT=y
|
||||
CONFIG_MIPS32_O32=y
|
||||
CONFIG_MIPS32_N32=y
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
|
@ -61,7 +61,7 @@ CONFIG_BINFMT_MISC=y
|
||||
CONFIG_MIPS32_COMPAT=y
|
||||
CONFIG_MIPS32_O32=y
|
||||
CONFIG_MIPS32_N32=y
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_PM_DEBUG=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
|
@ -41,7 +41,7 @@ CONFIG_PCI=y
|
||||
CONFIG_PCI_MSI=y
|
||||
CONFIG_PCI_DEBUG=y
|
||||
CONFIG_BINFMT_MISC=m
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_PM_DEBUG=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
|
@ -30,7 +30,7 @@ retry:
|
||||
|
||||
return pte;
|
||||
#else
|
||||
return ACCESS_ONCE(*ptep);
|
||||
return READ_ONCE(*ptep);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
@ -33,11 +33,18 @@
|
||||
|
||||
#endif /*!CONFIG_PA20*/
|
||||
|
||||
/* LDCW, the only atomic read-write operation PA-RISC has. *sigh*. */
|
||||
/* LDCW, the only atomic read-write operation PA-RISC has. *sigh*.
|
||||
We don't explicitly expose that "*a" may be written as reload
|
||||
fails to find a register in class R1_REGS when "a" needs to be
|
||||
reloaded when generating 64-bit PIC code. Instead, we clobber
|
||||
memory to indicate to the compiler that the assembly code reads
|
||||
or writes to items other than those listed in the input and output
|
||||
operands. This may pessimize the code somewhat but __ldcw is
|
||||
usually used within code blocks surrounded by memory barriors. */
|
||||
#define __ldcw(a) ({ \
|
||||
unsigned __ret; \
|
||||
__asm__ __volatile__(__LDCW " 0(%2),%0" \
|
||||
: "=r" (__ret), "+m" (*(a)) : "r" (a)); \
|
||||
__asm__ __volatile__(__LDCW " 0(%1),%0" \
|
||||
: "=r" (__ret) : "r" (a) : "memory"); \
|
||||
__ret; \
|
||||
})
|
||||
|
||||
|
@ -36,7 +36,7 @@ CONFIG_KEXEC=y
|
||||
CONFIG_SCHED_SMT=y
|
||||
CONFIG_CMDLINE_BOOL=y
|
||||
CONFIG_CMDLINE=""
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_PM_DEBUG=y
|
||||
# CONFIG_SECCOMP is not set
|
||||
# CONFIG_PCI is not set
|
||||
|
@ -227,12 +227,10 @@ static void ipte_lock_simple(struct kvm_vcpu *vcpu)
|
||||
goto out;
|
||||
ic = &vcpu->kvm->arch.sca->ipte_control;
|
||||
do {
|
||||
old = *ic;
|
||||
barrier();
|
||||
old = READ_ONCE(*ic);
|
||||
while (old.k) {
|
||||
cond_resched();
|
||||
old = *ic;
|
||||
barrier();
|
||||
old = READ_ONCE(*ic);
|
||||
}
|
||||
new = old;
|
||||
new.k = 1;
|
||||
@ -251,8 +249,7 @@ static void ipte_unlock_simple(struct kvm_vcpu *vcpu)
|
||||
goto out;
|
||||
ic = &vcpu->kvm->arch.sca->ipte_control;
|
||||
do {
|
||||
old = *ic;
|
||||
barrier();
|
||||
old = READ_ONCE(*ic);
|
||||
new = old;
|
||||
new.k = 0;
|
||||
} while (cmpxchg(&ic->val, old.val, new.val) != old.val);
|
||||
@ -267,12 +264,10 @@ static void ipte_lock_siif(struct kvm_vcpu *vcpu)
|
||||
|
||||
ic = &vcpu->kvm->arch.sca->ipte_control;
|
||||
do {
|
||||
old = *ic;
|
||||
barrier();
|
||||
old = READ_ONCE(*ic);
|
||||
while (old.kg) {
|
||||
cond_resched();
|
||||
old = *ic;
|
||||
barrier();
|
||||
old = READ_ONCE(*ic);
|
||||
}
|
||||
new = old;
|
||||
new.k = 1;
|
||||
@ -286,8 +281,7 @@ static void ipte_unlock_siif(struct kvm_vcpu *vcpu)
|
||||
|
||||
ic = &vcpu->kvm->arch.sca->ipte_control;
|
||||
do {
|
||||
old = *ic;
|
||||
barrier();
|
||||
old = READ_ONCE(*ic);
|
||||
new = old;
|
||||
new.kh--;
|
||||
if (!new.kh)
|
||||
|
@ -223,7 +223,7 @@ config CPU_SHX3
|
||||
config ARCH_SHMOBILE
|
||||
bool
|
||||
select ARCH_SUSPEND_POSSIBLE
|
||||
select PM_RUNTIME
|
||||
select PM
|
||||
|
||||
config CPU_HAS_PMU
|
||||
depends on CPU_SH4 || CPU_SH4A
|
||||
|
@ -47,7 +47,7 @@ CONFIG_PREEMPT=y
|
||||
CONFIG_BINFMT_MISC=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_PM_DEBUG=y
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_CPU_IDLE=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
|
@ -82,7 +82,7 @@ CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
|
||||
CONFIG_BINFMT_MISC=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_PM_DEBUG=y
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_CPU_IDLE=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
|
@ -92,7 +92,7 @@ static __always_inline void arch_spin_lock(arch_spinlock_t *lock)
|
||||
unsigned count = SPIN_THRESHOLD;
|
||||
|
||||
do {
|
||||
if (ACCESS_ONCE(lock->tickets.head) == inc.tail)
|
||||
if (READ_ONCE(lock->tickets.head) == inc.tail)
|
||||
goto out;
|
||||
cpu_relax();
|
||||
} while (--count);
|
||||
@ -105,7 +105,7 @@ static __always_inline int arch_spin_trylock(arch_spinlock_t *lock)
|
||||
{
|
||||
arch_spinlock_t old, new;
|
||||
|
||||
old.tickets = ACCESS_ONCE(lock->tickets);
|
||||
old.tickets = READ_ONCE(lock->tickets);
|
||||
if (old.tickets.head != (old.tickets.tail & ~TICKET_SLOWPATH_FLAG))
|
||||
return 0;
|
||||
|
||||
@ -162,14 +162,14 @@ static __always_inline void arch_spin_unlock(arch_spinlock_t *lock)
|
||||
|
||||
static inline int arch_spin_is_locked(arch_spinlock_t *lock)
|
||||
{
|
||||
struct __raw_tickets tmp = ACCESS_ONCE(lock->tickets);
|
||||
struct __raw_tickets tmp = READ_ONCE(lock->tickets);
|
||||
|
||||
return tmp.tail != tmp.head;
|
||||
}
|
||||
|
||||
static inline int arch_spin_is_contended(arch_spinlock_t *lock)
|
||||
{
|
||||
struct __raw_tickets tmp = ACCESS_ONCE(lock->tickets);
|
||||
struct __raw_tickets tmp = READ_ONCE(lock->tickets);
|
||||
|
||||
return (__ticket_t)(tmp.tail - tmp.head) > TICKET_LOCK_INC;
|
||||
}
|
||||
|
@ -4448,7 +4448,7 @@ void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm)
|
||||
* zap all shadow pages.
|
||||
*/
|
||||
if (unlikely(kvm_current_mmio_generation(kvm) == 0)) {
|
||||
printk_ratelimited(KERN_INFO "kvm: zapping shadow pages for mmio generation wraparound\n");
|
||||
printk_ratelimited(KERN_DEBUG "kvm: zapping shadow pages for mmio generation wraparound\n");
|
||||
kvm_mmu_invalidate_zap_all_pages(kvm);
|
||||
}
|
||||
}
|
||||
|
@ -5840,53 +5840,10 @@ static __init int hardware_setup(void)
|
||||
memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
|
||||
memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
|
||||
|
||||
vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
|
||||
vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
|
||||
vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
|
||||
vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
|
||||
vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
|
||||
vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
|
||||
vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
|
||||
|
||||
memcpy(vmx_msr_bitmap_legacy_x2apic,
|
||||
vmx_msr_bitmap_legacy, PAGE_SIZE);
|
||||
memcpy(vmx_msr_bitmap_longmode_x2apic,
|
||||
vmx_msr_bitmap_longmode, PAGE_SIZE);
|
||||
|
||||
if (enable_apicv) {
|
||||
for (msr = 0x800; msr <= 0x8ff; msr++)
|
||||
vmx_disable_intercept_msr_read_x2apic(msr);
|
||||
|
||||
/* According SDM, in x2apic mode, the whole id reg is used.
|
||||
* But in KVM, it only use the highest eight bits. Need to
|
||||
* intercept it */
|
||||
vmx_enable_intercept_msr_read_x2apic(0x802);
|
||||
/* TMCCT */
|
||||
vmx_enable_intercept_msr_read_x2apic(0x839);
|
||||
/* TPR */
|
||||
vmx_disable_intercept_msr_write_x2apic(0x808);
|
||||
/* EOI */
|
||||
vmx_disable_intercept_msr_write_x2apic(0x80b);
|
||||
/* SELF-IPI */
|
||||
vmx_disable_intercept_msr_write_x2apic(0x83f);
|
||||
}
|
||||
|
||||
if (enable_ept) {
|
||||
kvm_mmu_set_mask_ptes(0ull,
|
||||
(enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
|
||||
(enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
|
||||
0ull, VMX_EPT_EXECUTABLE_MASK);
|
||||
ept_set_mmio_spte_mask();
|
||||
kvm_enable_tdp();
|
||||
} else
|
||||
kvm_disable_tdp();
|
||||
|
||||
update_ple_window_actual_max();
|
||||
|
||||
if (setup_vmcs_config(&vmcs_config) < 0) {
|
||||
r = -EIO;
|
||||
goto out7;
|
||||
}
|
||||
}
|
||||
|
||||
if (boot_cpu_has(X86_FEATURE_NX))
|
||||
kvm_enable_efer_bits(EFER_NX);
|
||||
@ -5945,6 +5902,49 @@ static __init int hardware_setup(void)
|
||||
if (nested)
|
||||
nested_vmx_setup_ctls_msrs();
|
||||
|
||||
vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
|
||||
vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
|
||||
vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
|
||||
vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
|
||||
vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
|
||||
vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
|
||||
vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
|
||||
|
||||
memcpy(vmx_msr_bitmap_legacy_x2apic,
|
||||
vmx_msr_bitmap_legacy, PAGE_SIZE);
|
||||
memcpy(vmx_msr_bitmap_longmode_x2apic,
|
||||
vmx_msr_bitmap_longmode, PAGE_SIZE);
|
||||
|
||||
if (enable_apicv) {
|
||||
for (msr = 0x800; msr <= 0x8ff; msr++)
|
||||
vmx_disable_intercept_msr_read_x2apic(msr);
|
||||
|
||||
/* According SDM, in x2apic mode, the whole id reg is used.
|
||||
* But in KVM, it only use the highest eight bits. Need to
|
||||
* intercept it */
|
||||
vmx_enable_intercept_msr_read_x2apic(0x802);
|
||||
/* TMCCT */
|
||||
vmx_enable_intercept_msr_read_x2apic(0x839);
|
||||
/* TPR */
|
||||
vmx_disable_intercept_msr_write_x2apic(0x808);
|
||||
/* EOI */
|
||||
vmx_disable_intercept_msr_write_x2apic(0x80b);
|
||||
/* SELF-IPI */
|
||||
vmx_disable_intercept_msr_write_x2apic(0x83f);
|
||||
}
|
||||
|
||||
if (enable_ept) {
|
||||
kvm_mmu_set_mask_ptes(0ull,
|
||||
(enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
|
||||
(enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
|
||||
0ull, VMX_EPT_EXECUTABLE_MASK);
|
||||
ept_set_mmio_spte_mask();
|
||||
kvm_enable_tdp();
|
||||
} else
|
||||
kvm_disable_tdp();
|
||||
|
||||
update_ple_window_actual_max();
|
||||
|
||||
return alloc_kvm_area();
|
||||
|
||||
out7:
|
||||
|
@ -15,7 +15,7 @@
|
||||
static inline pte_t gup_get_pte(pte_t *ptep)
|
||||
{
|
||||
#ifndef CONFIG_X86_PAE
|
||||
return ACCESS_ONCE(*ptep);
|
||||
return READ_ONCE(*ptep);
|
||||
#else
|
||||
/*
|
||||
* With get_user_pages_fast, we walk down the pagetables without taking
|
||||
|
@ -417,6 +417,6 @@ static void __exit agp_ali_cleanup(void)
|
||||
module_init(agp_ali_init);
|
||||
module_exit(agp_ali_cleanup);
|
||||
|
||||
MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
|
||||
MODULE_AUTHOR("Dave Jones");
|
||||
MODULE_LICENSE("GPL and additional rights");
|
||||
|
||||
|
@ -813,6 +813,6 @@ static void __exit agp_amd64_cleanup(void)
|
||||
module_init(agp_amd64_mod_init);
|
||||
module_exit(agp_amd64_cleanup);
|
||||
|
||||
MODULE_AUTHOR("Dave Jones <davej@redhat.com>, Andi Kleen");
|
||||
MODULE_AUTHOR("Dave Jones, Andi Kleen");
|
||||
module_param(agp_try_unsupported, bool, 0);
|
||||
MODULE_LICENSE("GPL");
|
||||
|
@ -579,6 +579,6 @@ static void __exit agp_ati_cleanup(void)
|
||||
module_init(agp_ati_init);
|
||||
module_exit(agp_ati_cleanup);
|
||||
|
||||
MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
|
||||
MODULE_AUTHOR("Dave Jones");
|
||||
MODULE_LICENSE("GPL and additional rights");
|
||||
|
||||
|
@ -356,7 +356,7 @@ static __init int agp_setup(char *s)
|
||||
__setup("agp=", agp_setup);
|
||||
#endif
|
||||
|
||||
MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
|
||||
MODULE_AUTHOR("Dave Jones, Jeff Hartmann");
|
||||
MODULE_DESCRIPTION("AGP GART driver");
|
||||
MODULE_LICENSE("GPL and additional rights");
|
||||
MODULE_ALIAS_MISCDEV(AGPGART_MINOR);
|
||||
|
@ -920,5 +920,5 @@ static void __exit agp_intel_cleanup(void)
|
||||
module_init(agp_intel_init);
|
||||
module_exit(agp_intel_cleanup);
|
||||
|
||||
MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
|
||||
MODULE_AUTHOR("Dave Jones, Various @Intel");
|
||||
MODULE_LICENSE("GPL and additional rights");
|
||||
|
@ -1438,5 +1438,5 @@ void intel_gmch_remove(void)
|
||||
}
|
||||
EXPORT_SYMBOL(intel_gmch_remove);
|
||||
|
||||
MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
|
||||
MODULE_AUTHOR("Dave Jones, Various @Intel");
|
||||
MODULE_LICENSE("GPL and additional rights");
|
||||
|
@ -1,7 +1,7 @@
|
||||
/*
|
||||
* Nvidia AGPGART routines.
|
||||
* Based upon a 2.4 agpgart diff by the folks from NVIDIA, and hacked up
|
||||
* to work in 2.5 by Dave Jones <davej@redhat.com>
|
||||
* to work in 2.5 by Dave Jones.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
|
@ -595,4 +595,4 @@ module_init(agp_via_init);
|
||||
module_exit(agp_via_cleanup);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
|
||||
MODULE_AUTHOR("Dave Jones");
|
||||
|
@ -199,18 +199,6 @@ struct bmc_device {
|
||||
int guid_set;
|
||||
char name[16];
|
||||
struct kref usecount;
|
||||
|
||||
/* bmc device attributes */
|
||||
struct device_attribute device_id_attr;
|
||||
struct device_attribute provides_dev_sdrs_attr;
|
||||
struct device_attribute revision_attr;
|
||||
struct device_attribute firmware_rev_attr;
|
||||
struct device_attribute version_attr;
|
||||
struct device_attribute add_dev_support_attr;
|
||||
struct device_attribute manufacturer_id_attr;
|
||||
struct device_attribute product_id_attr;
|
||||
struct device_attribute guid_attr;
|
||||
struct device_attribute aux_firmware_rev_attr;
|
||||
};
|
||||
#define to_bmc_device(x) container_of((x), struct bmc_device, pdev.dev)
|
||||
|
||||
@ -2252,7 +2240,7 @@ static ssize_t device_id_show(struct device *dev,
|
||||
|
||||
return snprintf(buf, 10, "%u\n", bmc->id.device_id);
|
||||
}
|
||||
DEVICE_ATTR(device_id, S_IRUGO, device_id_show, NULL);
|
||||
static DEVICE_ATTR(device_id, S_IRUGO, device_id_show, NULL);
|
||||
|
||||
static ssize_t provides_device_sdrs_show(struct device *dev,
|
||||
struct device_attribute *attr,
|
||||
@ -2263,7 +2251,8 @@ static ssize_t provides_device_sdrs_show(struct device *dev,
|
||||
return snprintf(buf, 10, "%u\n",
|
||||
(bmc->id.device_revision & 0x80) >> 7);
|
||||
}
|
||||
DEVICE_ATTR(provides_device_sdrs, S_IRUGO, provides_device_sdrs_show, NULL);
|
||||
static DEVICE_ATTR(provides_device_sdrs, S_IRUGO, provides_device_sdrs_show,
|
||||
NULL);
|
||||
|
||||
static ssize_t revision_show(struct device *dev, struct device_attribute *attr,
|
||||
char *buf)
|
||||
@ -2273,7 +2262,7 @@ static ssize_t revision_show(struct device *dev, struct device_attribute *attr,
|
||||
return snprintf(buf, 20, "%u\n",
|
||||
bmc->id.device_revision & 0x0F);
|
||||
}
|
||||
DEVICE_ATTR(revision, S_IRUGO, revision_show, NULL);
|
||||
static DEVICE_ATTR(revision, S_IRUGO, revision_show, NULL);
|
||||
|
||||
static ssize_t firmware_revision_show(struct device *dev,
|
||||
struct device_attribute *attr,
|
||||
@ -2284,7 +2273,7 @@ static ssize_t firmware_revision_show(struct device *dev,
|
||||
return snprintf(buf, 20, "%u.%x\n", bmc->id.firmware_revision_1,
|
||||
bmc->id.firmware_revision_2);
|
||||
}
|
||||
DEVICE_ATTR(firmware_revision, S_IRUGO, firmware_revision_show, NULL);
|
||||
static DEVICE_ATTR(firmware_revision, S_IRUGO, firmware_revision_show, NULL);
|
||||
|
||||
static ssize_t ipmi_version_show(struct device *dev,
|
||||
struct device_attribute *attr,
|
||||
@ -2296,7 +2285,7 @@ static ssize_t ipmi_version_show(struct device *dev,
|
||||
ipmi_version_major(&bmc->id),
|
||||
ipmi_version_minor(&bmc->id));
|
||||
}
|
||||
DEVICE_ATTR(ipmi_version, S_IRUGO, ipmi_version_show, NULL);
|
||||
static DEVICE_ATTR(ipmi_version, S_IRUGO, ipmi_version_show, NULL);
|
||||
|
||||
static ssize_t add_dev_support_show(struct device *dev,
|
||||
struct device_attribute *attr,
|
||||
@ -2307,7 +2296,8 @@ static ssize_t add_dev_support_show(struct device *dev,
|
||||
return snprintf(buf, 10, "0x%02x\n",
|
||||
bmc->id.additional_device_support);
|
||||
}
|
||||
DEVICE_ATTR(additional_device_support, S_IRUGO, add_dev_support_show, NULL);
|
||||
static DEVICE_ATTR(additional_device_support, S_IRUGO, add_dev_support_show,
|
||||
NULL);
|
||||
|
||||
static ssize_t manufacturer_id_show(struct device *dev,
|
||||
struct device_attribute *attr,
|
||||
@ -2317,7 +2307,7 @@ static ssize_t manufacturer_id_show(struct device *dev,
|
||||
|
||||
return snprintf(buf, 20, "0x%6.6x\n", bmc->id.manufacturer_id);
|
||||
}
|
||||
DEVICE_ATTR(manufacturer_id, S_IRUGO, manufacturer_id_show, NULL);
|
||||
static DEVICE_ATTR(manufacturer_id, S_IRUGO, manufacturer_id_show, NULL);
|
||||
|
||||
static ssize_t product_id_show(struct device *dev,
|
||||
struct device_attribute *attr,
|
||||
@ -2327,7 +2317,7 @@ static ssize_t product_id_show(struct device *dev,
|
||||
|
||||
return snprintf(buf, 10, "0x%4.4x\n", bmc->id.product_id);
|
||||
}
|
||||
DEVICE_ATTR(product_id, S_IRUGO, product_id_show, NULL);
|
||||
static DEVICE_ATTR(product_id, S_IRUGO, product_id_show, NULL);
|
||||
|
||||
static ssize_t aux_firmware_rev_show(struct device *dev,
|
||||
struct device_attribute *attr,
|
||||
@ -2341,7 +2331,7 @@ static ssize_t aux_firmware_rev_show(struct device *dev,
|
||||
bmc->id.aux_firmware_revision[1],
|
||||
bmc->id.aux_firmware_revision[0]);
|
||||
}
|
||||
DEVICE_ATTR(aux_firmware_revision, S_IRUGO, aux_firmware_rev_show, NULL);
|
||||
static DEVICE_ATTR(aux_firmware_revision, S_IRUGO, aux_firmware_rev_show, NULL);
|
||||
|
||||
static ssize_t guid_show(struct device *dev, struct device_attribute *attr,
|
||||
char *buf)
|
||||
@ -2352,7 +2342,7 @@ static ssize_t guid_show(struct device *dev, struct device_attribute *attr,
|
||||
(long long) bmc->guid[0],
|
||||
(long long) bmc->guid[8]);
|
||||
}
|
||||
DEVICE_ATTR(guid, S_IRUGO, guid_show, NULL);
|
||||
static DEVICE_ATTR(guid, S_IRUGO, guid_show, NULL);
|
||||
|
||||
static struct attribute *bmc_dev_attrs[] = {
|
||||
&dev_attr_device_id.attr,
|
||||
@ -2392,10 +2382,10 @@ cleanup_bmc_device(struct kref *ref)
|
||||
|
||||
if (bmc->id.aux_firmware_revision_set)
|
||||
device_remove_file(&bmc->pdev.dev,
|
||||
&bmc->aux_firmware_rev_attr);
|
||||
&dev_attr_aux_firmware_revision);
|
||||
if (bmc->guid_set)
|
||||
device_remove_file(&bmc->pdev.dev,
|
||||
&bmc->guid_attr);
|
||||
&dev_attr_guid);
|
||||
|
||||
platform_device_unregister(&bmc->pdev);
|
||||
}
|
||||
@ -2422,16 +2412,14 @@ static int create_bmc_files(struct bmc_device *bmc)
|
||||
int err;
|
||||
|
||||
if (bmc->id.aux_firmware_revision_set) {
|
||||
bmc->aux_firmware_rev_attr.attr.name = "aux_firmware_revision";
|
||||
err = device_create_file(&bmc->pdev.dev,
|
||||
&bmc->aux_firmware_rev_attr);
|
||||
&dev_attr_aux_firmware_revision);
|
||||
if (err)
|
||||
goto out;
|
||||
}
|
||||
if (bmc->guid_set) {
|
||||
bmc->guid_attr.attr.name = "guid";
|
||||
err = device_create_file(&bmc->pdev.dev,
|
||||
&bmc->guid_attr);
|
||||
&dev_attr_guid);
|
||||
if (err)
|
||||
goto out_aux_firm;
|
||||
}
|
||||
@ -2441,7 +2429,7 @@ static int create_bmc_files(struct bmc_device *bmc)
|
||||
out_aux_firm:
|
||||
if (bmc->id.aux_firmware_revision_set)
|
||||
device_remove_file(&bmc->pdev.dev,
|
||||
&bmc->aux_firmware_rev_attr);
|
||||
&dev_attr_aux_firmware_revision);
|
||||
out:
|
||||
return err;
|
||||
}
|
||||
|
@ -52,6 +52,7 @@
|
||||
#include <linux/dmi.h>
|
||||
#include <linux/kthread.h>
|
||||
#include <linux/acpi.h>
|
||||
#include <linux/ctype.h>
|
||||
|
||||
#define PFX "ipmi_ssif: "
|
||||
#define DEVICE_NAME "ipmi_ssif"
|
||||
|
@ -57,7 +57,7 @@ static unsigned long clk_programmable_recalc_rate(struct clk_hw *hw,
|
||||
static long clk_programmable_determine_rate(struct clk_hw *hw,
|
||||
unsigned long rate,
|
||||
unsigned long *best_parent_rate,
|
||||
struct clk **best_parent_clk)
|
||||
struct clk_hw **best_parent_hw)
|
||||
{
|
||||
struct clk *parent = NULL;
|
||||
long best_rate = -EINVAL;
|
||||
@ -84,7 +84,7 @@ static long clk_programmable_determine_rate(struct clk_hw *hw,
|
||||
if (best_rate < 0 || (rate - tmp_rate) < (rate - best_rate)) {
|
||||
best_rate = tmp_rate;
|
||||
*best_parent_rate = parent_rate;
|
||||
*best_parent_clk = parent;
|
||||
*best_parent_hw = __clk_get_hw(parent);
|
||||
}
|
||||
|
||||
if (!best_rate)
|
||||
|
@ -1032,7 +1032,7 @@ static long kona_peri_clk_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
}
|
||||
|
||||
static long kona_peri_clk_determine_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *best_parent_rate, struct clk **best_parent)
|
||||
unsigned long *best_parent_rate, struct clk_hw **best_parent)
|
||||
{
|
||||
struct kona_clk *bcm_clk = to_kona_clk(hw);
|
||||
struct clk *clk = hw->clk;
|
||||
@ -1075,7 +1075,7 @@ static long kona_peri_clk_determine_rate(struct clk_hw *hw, unsigned long rate,
|
||||
if (delta < best_delta) {
|
||||
best_delta = delta;
|
||||
best_rate = other_rate;
|
||||
*best_parent = parent;
|
||||
*best_parent = __clk_get_hw(parent);
|
||||
*best_parent_rate = parent_rate;
|
||||
}
|
||||
}
|
||||
|
@ -57,7 +57,7 @@ static unsigned long clk_composite_recalc_rate(struct clk_hw *hw,
|
||||
|
||||
static long clk_composite_determine_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *best_parent_rate,
|
||||
struct clk **best_parent_p)
|
||||
struct clk_hw **best_parent_p)
|
||||
{
|
||||
struct clk_composite *composite = to_clk_composite(hw);
|
||||
const struct clk_ops *rate_ops = composite->rate_ops;
|
||||
@ -80,8 +80,9 @@ static long clk_composite_determine_rate(struct clk_hw *hw, unsigned long rate,
|
||||
*best_parent_p = NULL;
|
||||
|
||||
if (__clk_get_flags(hw->clk) & CLK_SET_RATE_NO_REPARENT) {
|
||||
*best_parent_p = clk_get_parent(mux_hw->clk);
|
||||
*best_parent_rate = __clk_get_rate(*best_parent_p);
|
||||
parent = clk_get_parent(mux_hw->clk);
|
||||
*best_parent_p = __clk_get_hw(parent);
|
||||
*best_parent_rate = __clk_get_rate(parent);
|
||||
|
||||
return rate_ops->round_rate(rate_hw, rate,
|
||||
best_parent_rate);
|
||||
@ -103,7 +104,7 @@ static long clk_composite_determine_rate(struct clk_hw *hw, unsigned long rate,
|
||||
|
||||
if (!rate_diff || !*best_parent_p
|
||||
|| best_rate_diff > rate_diff) {
|
||||
*best_parent_p = parent;
|
||||
*best_parent_p = __clk_get_hw(parent);
|
||||
*best_parent_rate = parent_rate;
|
||||
best_rate_diff = rate_diff;
|
||||
best_rate = tmp_rate;
|
||||
|
@ -77,7 +77,7 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
|
||||
|
||||
else {
|
||||
if (mux->flags & CLK_MUX_INDEX_BIT)
|
||||
index = (1 << ffs(index));
|
||||
index = 1 << index;
|
||||
|
||||
if (mux->flags & CLK_MUX_INDEX_ONE)
|
||||
index++;
|
||||
|
@ -218,7 +218,7 @@ static int s2mps11_clk_probe(struct platform_device *pdev)
|
||||
default:
|
||||
dev_err(&pdev->dev, "Invalid device type\n");
|
||||
return -EINVAL;
|
||||
};
|
||||
}
|
||||
|
||||
/* Store clocks of_node in first element of s2mps11_clks array */
|
||||
s2mps11_clks->clk_np = s2mps11_clk_parse_dt(pdev, clks_init);
|
||||
|
@ -240,7 +240,6 @@ static const struct file_operations clk_dump_fops = {
|
||||
.release = single_release,
|
||||
};
|
||||
|
||||
/* caller must hold prepare_lock */
|
||||
static int clk_debug_create_one(struct clk *clk, struct dentry *pdentry)
|
||||
{
|
||||
struct dentry *d;
|
||||
@ -354,13 +353,13 @@ out:
|
||||
mutex_unlock(&clk_debug_lock);
|
||||
}
|
||||
|
||||
struct dentry *clk_debugfs_add_file(struct clk *clk, char *name, umode_t mode,
|
||||
struct dentry *clk_debugfs_add_file(struct clk_hw *hw, char *name, umode_t mode,
|
||||
void *data, const struct file_operations *fops)
|
||||
{
|
||||
struct dentry *d = NULL;
|
||||
|
||||
if (clk->dentry)
|
||||
d = debugfs_create_file(name, mode, clk->dentry, data, fops);
|
||||
if (hw->clk->dentry)
|
||||
d = debugfs_create_file(name, mode, hw->clk->dentry, data, fops);
|
||||
|
||||
return d;
|
||||
}
|
||||
@ -574,11 +573,6 @@ unsigned int __clk_get_enable_count(struct clk *clk)
|
||||
return !clk ? 0 : clk->enable_count;
|
||||
}
|
||||
|
||||
unsigned int __clk_get_prepare_count(struct clk *clk)
|
||||
{
|
||||
return !clk ? 0 : clk->prepare_count;
|
||||
}
|
||||
|
||||
unsigned long __clk_get_rate(struct clk *clk)
|
||||
{
|
||||
unsigned long ret;
|
||||
@ -601,7 +595,7 @@ out:
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(__clk_get_rate);
|
||||
|
||||
unsigned long __clk_get_accuracy(struct clk *clk)
|
||||
static unsigned long __clk_get_accuracy(struct clk *clk)
|
||||
{
|
||||
if (!clk)
|
||||
return 0;
|
||||
@ -707,7 +701,7 @@ struct clk *__clk_lookup(const char *name)
|
||||
*/
|
||||
long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *best_parent_rate,
|
||||
struct clk **best_parent_p)
|
||||
struct clk_hw **best_parent_p)
|
||||
{
|
||||
struct clk *clk = hw->clk, *parent, *best_parent = NULL;
|
||||
int i, num_parents;
|
||||
@ -743,7 +737,7 @@ long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate,
|
||||
|
||||
out:
|
||||
if (best_parent)
|
||||
*best_parent_p = best_parent;
|
||||
*best_parent_p = best_parent->hw;
|
||||
*best_parent_rate = best;
|
||||
|
||||
return best;
|
||||
@ -951,6 +945,7 @@ unsigned long __clk_round_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
unsigned long parent_rate = 0;
|
||||
struct clk *parent;
|
||||
struct clk_hw *parent_hw;
|
||||
|
||||
if (!clk)
|
||||
return 0;
|
||||
@ -959,10 +954,11 @@ unsigned long __clk_round_rate(struct clk *clk, unsigned long rate)
|
||||
if (parent)
|
||||
parent_rate = parent->rate;
|
||||
|
||||
if (clk->ops->determine_rate)
|
||||
if (clk->ops->determine_rate) {
|
||||
parent_hw = parent ? parent->hw : NULL;
|
||||
return clk->ops->determine_rate(clk->hw, rate, &parent_rate,
|
||||
&parent);
|
||||
else if (clk->ops->round_rate)
|
||||
&parent_hw);
|
||||
} else if (clk->ops->round_rate)
|
||||
return clk->ops->round_rate(clk->hw, rate, &parent_rate);
|
||||
else if (clk->flags & CLK_SET_RATE_PARENT)
|
||||
return __clk_round_rate(clk->parent, rate);
|
||||
@ -1350,6 +1346,7 @@ static struct clk *clk_calc_new_rates(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
struct clk *top = clk;
|
||||
struct clk *old_parent, *parent;
|
||||
struct clk_hw *parent_hw;
|
||||
unsigned long best_parent_rate = 0;
|
||||
unsigned long new_rate;
|
||||
int p_index = 0;
|
||||
@ -1365,9 +1362,11 @@ static struct clk *clk_calc_new_rates(struct clk *clk, unsigned long rate)
|
||||
|
||||
/* find the closest rate and parent clk/rate */
|
||||
if (clk->ops->determine_rate) {
|
||||
parent_hw = parent ? parent->hw : NULL;
|
||||
new_rate = clk->ops->determine_rate(clk->hw, rate,
|
||||
&best_parent_rate,
|
||||
&parent);
|
||||
&parent_hw);
|
||||
parent = parent_hw->clk;
|
||||
} else if (clk->ops->round_rate) {
|
||||
new_rate = clk->ops->round_rate(clk->hw, rate,
|
||||
&best_parent_rate);
|
||||
@ -1614,7 +1613,7 @@ static struct clk *__clk_init_parent(struct clk *clk)
|
||||
|
||||
if (clk->num_parents == 1) {
|
||||
if (IS_ERR_OR_NULL(clk->parent))
|
||||
ret = clk->parent = __clk_lookup(clk->parent_names[0]);
|
||||
clk->parent = __clk_lookup(clk->parent_names[0]);
|
||||
ret = clk->parent;
|
||||
goto out;
|
||||
}
|
||||
@ -1944,7 +1943,6 @@ int __clk_init(struct device *dev, struct clk *clk)
|
||||
else
|
||||
clk->rate = 0;
|
||||
|
||||
clk_debug_register(clk);
|
||||
/*
|
||||
* walk the list of orphan clocks and reparent any that are children of
|
||||
* this clock
|
||||
@ -1979,6 +1977,9 @@ int __clk_init(struct device *dev, struct clk *clk)
|
||||
out:
|
||||
clk_prepare_unlock();
|
||||
|
||||
if (!ret)
|
||||
clk_debug_register(clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -2273,14 +2274,17 @@ int __clk_get(struct clk *clk)
|
||||
|
||||
void __clk_put(struct clk *clk)
|
||||
{
|
||||
struct module *owner;
|
||||
|
||||
if (!clk || WARN_ON_ONCE(IS_ERR(clk)))
|
||||
return;
|
||||
|
||||
clk_prepare_lock();
|
||||
owner = clk->owner;
|
||||
kref_put(&clk->ref, __clk_release);
|
||||
clk_prepare_unlock();
|
||||
|
||||
module_put(clk->owner);
|
||||
module_put(owner);
|
||||
}
|
||||
|
||||
/*** clk rate change notifiers ***/
|
||||
|
@ -38,44 +38,44 @@
|
||||
#include "clk.h"
|
||||
|
||||
/* clock parent list */
|
||||
static const char *timer0_mux_p[] __initdata = { "osc32k", "timerclk01", };
|
||||
static const char *timer1_mux_p[] __initdata = { "osc32k", "timerclk01", };
|
||||
static const char *timer2_mux_p[] __initdata = { "osc32k", "timerclk23", };
|
||||
static const char *timer3_mux_p[] __initdata = { "osc32k", "timerclk23", };
|
||||
static const char *timer4_mux_p[] __initdata = { "osc32k", "timerclk45", };
|
||||
static const char *timer5_mux_p[] __initdata = { "osc32k", "timerclk45", };
|
||||
static const char *timer6_mux_p[] __initdata = { "osc32k", "timerclk67", };
|
||||
static const char *timer7_mux_p[] __initdata = { "osc32k", "timerclk67", };
|
||||
static const char *timer8_mux_p[] __initdata = { "osc32k", "timerclk89", };
|
||||
static const char *timer9_mux_p[] __initdata = { "osc32k", "timerclk89", };
|
||||
static const char *uart0_mux_p[] __initdata = { "osc26m", "pclk", };
|
||||
static const char *uart1_mux_p[] __initdata = { "osc26m", "pclk", };
|
||||
static const char *uart2_mux_p[] __initdata = { "osc26m", "pclk", };
|
||||
static const char *uart3_mux_p[] __initdata = { "osc26m", "pclk", };
|
||||
static const char *uart4_mux_p[] __initdata = { "osc26m", "pclk", };
|
||||
static const char *spi0_mux_p[] __initdata = { "osc26m", "rclk_cfgaxi", };
|
||||
static const char *spi1_mux_p[] __initdata = { "osc26m", "rclk_cfgaxi", };
|
||||
static const char *spi2_mux_p[] __initdata = { "osc26m", "rclk_cfgaxi", };
|
||||
static const char *timer0_mux_p[] __initconst = { "osc32k", "timerclk01", };
|
||||
static const char *timer1_mux_p[] __initconst = { "osc32k", "timerclk01", };
|
||||
static const char *timer2_mux_p[] __initconst = { "osc32k", "timerclk23", };
|
||||
static const char *timer3_mux_p[] __initconst = { "osc32k", "timerclk23", };
|
||||
static const char *timer4_mux_p[] __initconst = { "osc32k", "timerclk45", };
|
||||
static const char *timer5_mux_p[] __initconst = { "osc32k", "timerclk45", };
|
||||
static const char *timer6_mux_p[] __initconst = { "osc32k", "timerclk67", };
|
||||
static const char *timer7_mux_p[] __initconst = { "osc32k", "timerclk67", };
|
||||
static const char *timer8_mux_p[] __initconst = { "osc32k", "timerclk89", };
|
||||
static const char *timer9_mux_p[] __initconst = { "osc32k", "timerclk89", };
|
||||
static const char *uart0_mux_p[] __initconst = { "osc26m", "pclk", };
|
||||
static const char *uart1_mux_p[] __initconst = { "osc26m", "pclk", };
|
||||
static const char *uart2_mux_p[] __initconst = { "osc26m", "pclk", };
|
||||
static const char *uart3_mux_p[] __initconst = { "osc26m", "pclk", };
|
||||
static const char *uart4_mux_p[] __initconst = { "osc26m", "pclk", };
|
||||
static const char *spi0_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", };
|
||||
static const char *spi1_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", };
|
||||
static const char *spi2_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", };
|
||||
/* share axi parent */
|
||||
static const char *saxi_mux_p[] __initdata = { "armpll3", "armpll2", };
|
||||
static const char *pwm0_mux_p[] __initdata = { "osc32k", "osc26m", };
|
||||
static const char *pwm1_mux_p[] __initdata = { "osc32k", "osc26m", };
|
||||
static const char *sd_mux_p[] __initdata = { "armpll2", "armpll3", };
|
||||
static const char *mmc1_mux_p[] __initdata = { "armpll2", "armpll3", };
|
||||
static const char *mmc1_mux2_p[] __initdata = { "osc26m", "mmc1_div", };
|
||||
static const char *g2d_mux_p[] __initdata = { "armpll2", "armpll3", };
|
||||
static const char *venc_mux_p[] __initdata = { "armpll2", "armpll3", };
|
||||
static const char *vdec_mux_p[] __initdata = { "armpll2", "armpll3", };
|
||||
static const char *vpp_mux_p[] __initdata = { "armpll2", "armpll3", };
|
||||
static const char *edc0_mux_p[] __initdata = { "armpll2", "armpll3", };
|
||||
static const char *ldi0_mux_p[] __initdata = { "armpll2", "armpll4",
|
||||
static const char *saxi_mux_p[] __initconst = { "armpll3", "armpll2", };
|
||||
static const char *pwm0_mux_p[] __initconst = { "osc32k", "osc26m", };
|
||||
static const char *pwm1_mux_p[] __initconst = { "osc32k", "osc26m", };
|
||||
static const char *sd_mux_p[] __initconst = { "armpll2", "armpll3", };
|
||||
static const char *mmc1_mux_p[] __initconst = { "armpll2", "armpll3", };
|
||||
static const char *mmc1_mux2_p[] __initconst = { "osc26m", "mmc1_div", };
|
||||
static const char *g2d_mux_p[] __initconst = { "armpll2", "armpll3", };
|
||||
static const char *venc_mux_p[] __initconst = { "armpll2", "armpll3", };
|
||||
static const char *vdec_mux_p[] __initconst = { "armpll2", "armpll3", };
|
||||
static const char *vpp_mux_p[] __initconst = { "armpll2", "armpll3", };
|
||||
static const char *edc0_mux_p[] __initconst = { "armpll2", "armpll3", };
|
||||
static const char *ldi0_mux_p[] __initconst = { "armpll2", "armpll4",
|
||||
"armpll3", "armpll5", };
|
||||
static const char *edc1_mux_p[] __initdata = { "armpll2", "armpll3", };
|
||||
static const char *ldi1_mux_p[] __initdata = { "armpll2", "armpll4",
|
||||
static const char *edc1_mux_p[] __initconst = { "armpll2", "armpll3", };
|
||||
static const char *ldi1_mux_p[] __initconst = { "armpll2", "armpll4",
|
||||
"armpll3", "armpll5", };
|
||||
static const char *rclk_hsic_p[] __initdata = { "armpll3", "armpll2", };
|
||||
static const char *mmc2_mux_p[] __initdata = { "armpll2", "armpll3", };
|
||||
static const char *mmc3_mux_p[] __initdata = { "armpll2", "armpll3", };
|
||||
static const char *rclk_hsic_p[] __initconst = { "armpll3", "armpll2", };
|
||||
static const char *mmc2_mux_p[] __initconst = { "armpll2", "armpll3", };
|
||||
static const char *mmc3_mux_p[] __initconst = { "armpll2", "armpll3", };
|
||||
|
||||
|
||||
/* fixed rate clocks */
|
||||
@ -296,7 +296,7 @@ static unsigned long mmc_clk_recalc_rate(struct clk_hw *hw,
|
||||
|
||||
static long mmc_clk_determine_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *best_parent_rate,
|
||||
struct clk **best_parent_p)
|
||||
struct clk_hw **best_parent_p)
|
||||
{
|
||||
struct clk_mmc *mclk = to_mmc(hw);
|
||||
unsigned long best = 0;
|
||||
|
@ -2,7 +2,12 @@
|
||||
# Makefile for mmp specific clk
|
||||
#
|
||||
|
||||
obj-y += clk-apbc.o clk-apmu.o clk-frac.o
|
||||
obj-y += clk-apbc.o clk-apmu.o clk-frac.o clk-mix.o clk-gate.o clk.o
|
||||
|
||||
obj-$(CONFIG_RESET_CONTROLLER) += reset.o
|
||||
|
||||
obj-$(CONFIG_MACH_MMP_DT) += clk-of-pxa168.o clk-of-pxa910.o
|
||||
obj-$(CONFIG_MACH_MMP2_DT) += clk-of-mmp2.o
|
||||
|
||||
obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o
|
||||
obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o
|
||||
|
@ -22,19 +22,12 @@
|
||||
* numerator/denominator = Fin / (Fout * factor)
|
||||
*/
|
||||
|
||||
#define to_clk_factor(hw) container_of(hw, struct clk_factor, hw)
|
||||
struct clk_factor {
|
||||
struct clk_hw hw;
|
||||
void __iomem *base;
|
||||
struct clk_factor_masks *masks;
|
||||
struct clk_factor_tbl *ftbl;
|
||||
unsigned int ftbl_cnt;
|
||||
};
|
||||
#define to_clk_factor(hw) container_of(hw, struct mmp_clk_factor, hw)
|
||||
|
||||
static long clk_factor_round_rate(struct clk_hw *hw, unsigned long drate,
|
||||
unsigned long *prate)
|
||||
{
|
||||
struct clk_factor *factor = to_clk_factor(hw);
|
||||
struct mmp_clk_factor *factor = to_clk_factor(hw);
|
||||
unsigned long rate = 0, prev_rate;
|
||||
int i;
|
||||
|
||||
@ -58,8 +51,8 @@ static long clk_factor_round_rate(struct clk_hw *hw, unsigned long drate,
|
||||
static unsigned long clk_factor_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_factor *factor = to_clk_factor(hw);
|
||||
struct clk_factor_masks *masks = factor->masks;
|
||||
struct mmp_clk_factor *factor = to_clk_factor(hw);
|
||||
struct mmp_clk_factor_masks *masks = factor->masks;
|
||||
unsigned int val, num, den;
|
||||
|
||||
val = readl_relaxed(factor->base);
|
||||
@ -81,11 +74,12 @@ static unsigned long clk_factor_recalc_rate(struct clk_hw *hw,
|
||||
static int clk_factor_set_rate(struct clk_hw *hw, unsigned long drate,
|
||||
unsigned long prate)
|
||||
{
|
||||
struct clk_factor *factor = to_clk_factor(hw);
|
||||
struct clk_factor_masks *masks = factor->masks;
|
||||
struct mmp_clk_factor *factor = to_clk_factor(hw);
|
||||
struct mmp_clk_factor_masks *masks = factor->masks;
|
||||
int i;
|
||||
unsigned long val;
|
||||
unsigned long prev_rate, rate = 0;
|
||||
unsigned long flags = 0;
|
||||
|
||||
for (i = 0; i < factor->ftbl_cnt; i++) {
|
||||
prev_rate = rate;
|
||||
@ -97,6 +91,9 @@ static int clk_factor_set_rate(struct clk_hw *hw, unsigned long drate,
|
||||
if (i > 0)
|
||||
i--;
|
||||
|
||||
if (factor->lock)
|
||||
spin_lock_irqsave(factor->lock, flags);
|
||||
|
||||
val = readl_relaxed(factor->base);
|
||||
|
||||
val &= ~(masks->num_mask << masks->num_shift);
|
||||
@ -107,21 +104,65 @@ static int clk_factor_set_rate(struct clk_hw *hw, unsigned long drate,
|
||||
|
||||
writel_relaxed(val, factor->base);
|
||||
|
||||
if (factor->lock)
|
||||
spin_unlock_irqrestore(factor->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void clk_factor_init(struct clk_hw *hw)
|
||||
{
|
||||
struct mmp_clk_factor *factor = to_clk_factor(hw);
|
||||
struct mmp_clk_factor_masks *masks = factor->masks;
|
||||
u32 val, num, den;
|
||||
int i;
|
||||
unsigned long flags = 0;
|
||||
|
||||
if (factor->lock)
|
||||
spin_lock_irqsave(factor->lock, flags);
|
||||
|
||||
val = readl(factor->base);
|
||||
|
||||
/* calculate numerator */
|
||||
num = (val >> masks->num_shift) & masks->num_mask;
|
||||
|
||||
/* calculate denominator */
|
||||
den = (val >> masks->den_shift) & masks->den_mask;
|
||||
|
||||
for (i = 0; i < factor->ftbl_cnt; i++)
|
||||
if (den == factor->ftbl[i].den && num == factor->ftbl[i].num)
|
||||
break;
|
||||
|
||||
if (i >= factor->ftbl_cnt) {
|
||||
val &= ~(masks->num_mask << masks->num_shift);
|
||||
val |= (factor->ftbl[0].num & masks->num_mask) <<
|
||||
masks->num_shift;
|
||||
|
||||
val &= ~(masks->den_mask << masks->den_shift);
|
||||
val |= (factor->ftbl[0].den & masks->den_mask) <<
|
||||
masks->den_shift;
|
||||
|
||||
writel(val, factor->base);
|
||||
}
|
||||
|
||||
if (factor->lock)
|
||||
spin_unlock_irqrestore(factor->lock, flags);
|
||||
}
|
||||
|
||||
static struct clk_ops clk_factor_ops = {
|
||||
.recalc_rate = clk_factor_recalc_rate,
|
||||
.round_rate = clk_factor_round_rate,
|
||||
.set_rate = clk_factor_set_rate,
|
||||
.init = clk_factor_init,
|
||||
};
|
||||
|
||||
struct clk *mmp_clk_register_factor(const char *name, const char *parent_name,
|
||||
unsigned long flags, void __iomem *base,
|
||||
struct clk_factor_masks *masks, struct clk_factor_tbl *ftbl,
|
||||
unsigned int ftbl_cnt)
|
||||
struct mmp_clk_factor_masks *masks,
|
||||
struct mmp_clk_factor_tbl *ftbl,
|
||||
unsigned int ftbl_cnt, spinlock_t *lock)
|
||||
{
|
||||
struct clk_factor *factor;
|
||||
struct mmp_clk_factor *factor;
|
||||
struct clk_init_data init;
|
||||
struct clk *clk;
|
||||
|
||||
@ -142,6 +183,7 @@ struct clk *mmp_clk_register_factor(const char *name, const char *parent_name,
|
||||
factor->ftbl = ftbl;
|
||||
factor->ftbl_cnt = ftbl_cnt;
|
||||
factor->hw.init = &init;
|
||||
factor->lock = lock;
|
||||
|
||||
init.name = name;
|
||||
init.ops = &clk_factor_ops;
|
||||
|
133
drivers/clk/mmp/clk-gate.c
Normal file
133
drivers/clk/mmp/clk-gate.c
Normal file
@ -0,0 +1,133 @@
|
||||
/*
|
||||
* mmp gate clock operation source file
|
||||
*
|
||||
* Copyright (C) 2014 Marvell
|
||||
* Chao Xie <chao.xie@marvell.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
#include "clk.h"
|
||||
|
||||
/*
|
||||
* Some clocks will have mutiple bits to enable the clocks, and
|
||||
* the bits to disable the clock is not same as enabling bits.
|
||||
*/
|
||||
|
||||
#define to_clk_mmp_gate(hw) container_of(hw, struct mmp_clk_gate, hw)
|
||||
|
||||
static int mmp_clk_gate_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct mmp_clk_gate *gate = to_clk_mmp_gate(hw);
|
||||
struct clk *clk = hw->clk;
|
||||
unsigned long flags = 0;
|
||||
unsigned long rate;
|
||||
u32 tmp;
|
||||
|
||||
if (gate->lock)
|
||||
spin_lock_irqsave(gate->lock, flags);
|
||||
|
||||
tmp = readl(gate->reg);
|
||||
tmp &= ~gate->mask;
|
||||
tmp |= gate->val_enable;
|
||||
writel(tmp, gate->reg);
|
||||
|
||||
if (gate->lock)
|
||||
spin_unlock_irqrestore(gate->lock, flags);
|
||||
|
||||
if (gate->flags & MMP_CLK_GATE_NEED_DELAY) {
|
||||
rate = __clk_get_rate(clk);
|
||||
/* Need delay 2 cycles. */
|
||||
udelay(2000000/rate);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mmp_clk_gate_disable(struct clk_hw *hw)
|
||||
{
|
||||
struct mmp_clk_gate *gate = to_clk_mmp_gate(hw);
|
||||
unsigned long flags = 0;
|
||||
u32 tmp;
|
||||
|
||||
if (gate->lock)
|
||||
spin_lock_irqsave(gate->lock, flags);
|
||||
|
||||
tmp = readl(gate->reg);
|
||||
tmp &= ~gate->mask;
|
||||
tmp |= gate->val_disable;
|
||||
writel(tmp, gate->reg);
|
||||
|
||||
if (gate->lock)
|
||||
spin_unlock_irqrestore(gate->lock, flags);
|
||||
}
|
||||
|
||||
static int mmp_clk_gate_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct mmp_clk_gate *gate = to_clk_mmp_gate(hw);
|
||||
unsigned long flags = 0;
|
||||
u32 tmp;
|
||||
|
||||
if (gate->lock)
|
||||
spin_lock_irqsave(gate->lock, flags);
|
||||
|
||||
tmp = readl(gate->reg);
|
||||
|
||||
if (gate->lock)
|
||||
spin_unlock_irqrestore(gate->lock, flags);
|
||||
|
||||
return (tmp & gate->mask) == gate->val_enable;
|
||||
}
|
||||
|
||||
const struct clk_ops mmp_clk_gate_ops = {
|
||||
.enable = mmp_clk_gate_enable,
|
||||
.disable = mmp_clk_gate_disable,
|
||||
.is_enabled = mmp_clk_gate_is_enabled,
|
||||
};
|
||||
|
||||
struct clk *mmp_clk_register_gate(struct device *dev, const char *name,
|
||||
const char *parent_name, unsigned long flags,
|
||||
void __iomem *reg, u32 mask, u32 val_enable, u32 val_disable,
|
||||
unsigned int gate_flags, spinlock_t *lock)
|
||||
{
|
||||
struct mmp_clk_gate *gate;
|
||||
struct clk *clk;
|
||||
struct clk_init_data init;
|
||||
|
||||
/* allocate the gate */
|
||||
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
|
||||
if (!gate) {
|
||||
pr_err("%s:%s could not allocate gate clk\n", __func__, name);
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
|
||||
init.name = name;
|
||||
init.ops = &mmp_clk_gate_ops;
|
||||
init.flags = flags | CLK_IS_BASIC;
|
||||
init.parent_names = (parent_name ? &parent_name : NULL);
|
||||
init.num_parents = (parent_name ? 1 : 0);
|
||||
|
||||
/* struct clk_gate assignments */
|
||||
gate->reg = reg;
|
||||
gate->mask = mask;
|
||||
gate->val_enable = val_enable;
|
||||
gate->val_disable = val_disable;
|
||||
gate->flags = gate_flags;
|
||||
gate->lock = lock;
|
||||
gate->hw.init = &init;
|
||||
|
||||
clk = clk_register(dev, &gate->hw);
|
||||
|
||||
if (IS_ERR(clk))
|
||||
kfree(gate);
|
||||
|
||||
return clk;
|
||||
}
|
513
drivers/clk/mmp/clk-mix.c
Normal file
513
drivers/clk/mmp/clk-mix.c
Normal file
@ -0,0 +1,513 @@
|
||||
/*
|
||||
* mmp mix(div and mux) clock operation source file
|
||||
*
|
||||
* Copyright (C) 2014 Marvell
|
||||
* Chao Xie <chao.xie@marvell.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/err.h>
|
||||
|
||||
#include "clk.h"
|
||||
|
||||
/*
|
||||
* The mix clock is a clock combined mux and div type clock.
|
||||
* Because the div field and mux field need to be set at same
|
||||
* time, we can not divide it into 2 types of clock
|
||||
*/
|
||||
|
||||
#define to_clk_mix(hw) container_of(hw, struct mmp_clk_mix, hw)
|
||||
|
||||
static unsigned int _get_maxdiv(struct mmp_clk_mix *mix)
|
||||
{
|
||||
unsigned int div_mask = (1 << mix->reg_info.width_div) - 1;
|
||||
unsigned int maxdiv = 0;
|
||||
struct clk_div_table *clkt;
|
||||
|
||||
if (mix->div_flags & CLK_DIVIDER_ONE_BASED)
|
||||
return div_mask;
|
||||
if (mix->div_flags & CLK_DIVIDER_POWER_OF_TWO)
|
||||
return 1 << div_mask;
|
||||
if (mix->div_table) {
|
||||
for (clkt = mix->div_table; clkt->div; clkt++)
|
||||
if (clkt->div > maxdiv)
|
||||
maxdiv = clkt->div;
|
||||
return maxdiv;
|
||||
}
|
||||
return div_mask + 1;
|
||||
}
|
||||
|
||||
static unsigned int _get_div(struct mmp_clk_mix *mix, unsigned int val)
|
||||
{
|
||||
struct clk_div_table *clkt;
|
||||
|
||||
if (mix->div_flags & CLK_DIVIDER_ONE_BASED)
|
||||
return val;
|
||||
if (mix->div_flags & CLK_DIVIDER_POWER_OF_TWO)
|
||||
return 1 << val;
|
||||
if (mix->div_table) {
|
||||
for (clkt = mix->div_table; clkt->div; clkt++)
|
||||
if (clkt->val == val)
|
||||
return clkt->div;
|
||||
if (clkt->div == 0)
|
||||
return 0;
|
||||
}
|
||||
return val + 1;
|
||||
}
|
||||
|
||||
static unsigned int _get_mux(struct mmp_clk_mix *mix, unsigned int val)
|
||||
{
|
||||
int num_parents = __clk_get_num_parents(mix->hw.clk);
|
||||
int i;
|
||||
|
||||
if (mix->mux_flags & CLK_MUX_INDEX_BIT)
|
||||
return ffs(val) - 1;
|
||||
if (mix->mux_flags & CLK_MUX_INDEX_ONE)
|
||||
return val - 1;
|
||||
if (mix->mux_table) {
|
||||
for (i = 0; i < num_parents; i++)
|
||||
if (mix->mux_table[i] == val)
|
||||
return i;
|
||||
if (i == num_parents)
|
||||
return 0;
|
||||
}
|
||||
|
||||
return val;
|
||||
}
|
||||
static unsigned int _get_div_val(struct mmp_clk_mix *mix, unsigned int div)
|
||||
{
|
||||
struct clk_div_table *clkt;
|
||||
|
||||
if (mix->div_flags & CLK_DIVIDER_ONE_BASED)
|
||||
return div;
|
||||
if (mix->div_flags & CLK_DIVIDER_POWER_OF_TWO)
|
||||
return __ffs(div);
|
||||
if (mix->div_table) {
|
||||
for (clkt = mix->div_table; clkt->div; clkt++)
|
||||
if (clkt->div == div)
|
||||
return clkt->val;
|
||||
if (clkt->div == 0)
|
||||
return 0;
|
||||
}
|
||||
|
||||
return div - 1;
|
||||
}
|
||||
|
||||
static unsigned int _get_mux_val(struct mmp_clk_mix *mix, unsigned int mux)
|
||||
{
|
||||
if (mix->mux_table)
|
||||
return mix->mux_table[mux];
|
||||
|
||||
return mux;
|
||||
}
|
||||
|
||||
static void _filter_clk_table(struct mmp_clk_mix *mix,
|
||||
struct mmp_clk_mix_clk_table *table,
|
||||
unsigned int table_size)
|
||||
{
|
||||
int i;
|
||||
struct mmp_clk_mix_clk_table *item;
|
||||
struct clk *parent, *clk;
|
||||
unsigned long parent_rate;
|
||||
|
||||
clk = mix->hw.clk;
|
||||
|
||||
for (i = 0; i < table_size; i++) {
|
||||
item = &table[i];
|
||||
parent = clk_get_parent_by_index(clk, item->parent_index);
|
||||
parent_rate = __clk_get_rate(parent);
|
||||
if (parent_rate % item->rate) {
|
||||
item->valid = 0;
|
||||
} else {
|
||||
item->divisor = parent_rate / item->rate;
|
||||
item->valid = 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int _set_rate(struct mmp_clk_mix *mix, u32 mux_val, u32 div_val,
|
||||
unsigned int change_mux, unsigned int change_div)
|
||||
{
|
||||
struct mmp_clk_mix_reg_info *ri = &mix->reg_info;
|
||||
u8 width, shift;
|
||||
u32 mux_div, fc_req;
|
||||
int ret, timeout = 50;
|
||||
unsigned long flags = 0;
|
||||
|
||||
if (!change_mux && !change_div)
|
||||
return -EINVAL;
|
||||
|
||||
if (mix->lock)
|
||||
spin_lock_irqsave(mix->lock, flags);
|
||||
|
||||
if (mix->type == MMP_CLK_MIX_TYPE_V1
|
||||
|| mix->type == MMP_CLK_MIX_TYPE_V2)
|
||||
mux_div = readl(ri->reg_clk_ctrl);
|
||||
else
|
||||
mux_div = readl(ri->reg_clk_sel);
|
||||
|
||||
if (change_div) {
|
||||
width = ri->width_div;
|
||||
shift = ri->shift_div;
|
||||
mux_div &= ~MMP_CLK_BITS_MASK(width, shift);
|
||||
mux_div |= MMP_CLK_BITS_SET_VAL(div_val, width, shift);
|
||||
}
|
||||
|
||||
if (change_mux) {
|
||||
width = ri->width_mux;
|
||||
shift = ri->shift_mux;
|
||||
mux_div &= ~MMP_CLK_BITS_MASK(width, shift);
|
||||
mux_div |= MMP_CLK_BITS_SET_VAL(mux_val, width, shift);
|
||||
}
|
||||
|
||||
if (mix->type == MMP_CLK_MIX_TYPE_V1) {
|
||||
writel(mux_div, ri->reg_clk_ctrl);
|
||||
} else if (mix->type == MMP_CLK_MIX_TYPE_V2) {
|
||||
mux_div |= (1 << ri->bit_fc);
|
||||
writel(mux_div, ri->reg_clk_ctrl);
|
||||
|
||||
do {
|
||||
fc_req = readl(ri->reg_clk_ctrl);
|
||||
timeout--;
|
||||
if (!(fc_req & (1 << ri->bit_fc)))
|
||||
break;
|
||||
} while (timeout);
|
||||
|
||||
if (timeout == 0) {
|
||||
pr_err("%s:%s cannot do frequency change\n",
|
||||
__func__, __clk_get_name(mix->hw.clk));
|
||||
ret = -EBUSY;
|
||||
goto error;
|
||||
}
|
||||
} else {
|
||||
fc_req = readl(ri->reg_clk_ctrl);
|
||||
fc_req |= 1 << ri->bit_fc;
|
||||
writel(fc_req, ri->reg_clk_ctrl);
|
||||
writel(mux_div, ri->reg_clk_sel);
|
||||
fc_req &= ~(1 << ri->bit_fc);
|
||||
}
|
||||
|
||||
ret = 0;
|
||||
error:
|
||||
if (mix->lock)
|
||||
spin_unlock_irqrestore(mix->lock, flags);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static long mmp_clk_mix_determine_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *best_parent_rate,
|
||||
struct clk_hw **best_parent_clk)
|
||||
{
|
||||
struct mmp_clk_mix *mix = to_clk_mix(hw);
|
||||
struct mmp_clk_mix_clk_table *item;
|
||||
struct clk *parent, *parent_best, *mix_clk;
|
||||
unsigned long parent_rate, mix_rate, mix_rate_best, parent_rate_best;
|
||||
unsigned long gap, gap_best;
|
||||
u32 div_val_max;
|
||||
unsigned int div;
|
||||
int i, j;
|
||||
|
||||
mix_clk = hw->clk;
|
||||
|
||||
parent = NULL;
|
||||
mix_rate_best = 0;
|
||||
parent_rate_best = 0;
|
||||
gap_best = rate;
|
||||
parent_best = NULL;
|
||||
|
||||
if (mix->table) {
|
||||
for (i = 0; i < mix->table_size; i++) {
|
||||
item = &mix->table[i];
|
||||
if (item->valid == 0)
|
||||
continue;
|
||||
parent = clk_get_parent_by_index(mix_clk,
|
||||
item->parent_index);
|
||||
parent_rate = __clk_get_rate(parent);
|
||||
mix_rate = parent_rate / item->divisor;
|
||||
gap = abs(mix_rate - rate);
|
||||
if (parent_best == NULL || gap < gap_best) {
|
||||
parent_best = parent;
|
||||
parent_rate_best = parent_rate;
|
||||
mix_rate_best = mix_rate;
|
||||
gap_best = gap;
|
||||
if (gap_best == 0)
|
||||
goto found;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
for (i = 0; i < __clk_get_num_parents(mix_clk); i++) {
|
||||
parent = clk_get_parent_by_index(mix_clk, i);
|
||||
parent_rate = __clk_get_rate(parent);
|
||||
div_val_max = _get_maxdiv(mix);
|
||||
for (j = 0; j < div_val_max; j++) {
|
||||
div = _get_div(mix, j);
|
||||
mix_rate = parent_rate / div;
|
||||
gap = abs(mix_rate - rate);
|
||||
if (parent_best == NULL || gap < gap_best) {
|
||||
parent_best = parent;
|
||||
parent_rate_best = parent_rate;
|
||||
mix_rate_best = mix_rate;
|
||||
gap_best = gap;
|
||||
if (gap_best == 0)
|
||||
goto found;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
found:
|
||||
*best_parent_rate = parent_rate_best;
|
||||
*best_parent_clk = __clk_get_hw(parent_best);
|
||||
|
||||
return mix_rate_best;
|
||||
}
|
||||
|
||||
static int mmp_clk_mix_set_rate_and_parent(struct clk_hw *hw,
|
||||
unsigned long rate,
|
||||
unsigned long parent_rate,
|
||||
u8 index)
|
||||
{
|
||||
struct mmp_clk_mix *mix = to_clk_mix(hw);
|
||||
unsigned int div;
|
||||
u32 div_val, mux_val;
|
||||
|
||||
div = parent_rate / rate;
|
||||
div_val = _get_div_val(mix, div);
|
||||
mux_val = _get_mux_val(mix, index);
|
||||
|
||||
return _set_rate(mix, mux_val, div_val, 1, 1);
|
||||
}
|
||||
|
||||
static u8 mmp_clk_mix_get_parent(struct clk_hw *hw)
|
||||
{
|
||||
struct mmp_clk_mix *mix = to_clk_mix(hw);
|
||||
struct mmp_clk_mix_reg_info *ri = &mix->reg_info;
|
||||
unsigned long flags = 0;
|
||||
u32 mux_div = 0;
|
||||
u8 width, shift;
|
||||
u32 mux_val;
|
||||
|
||||
if (mix->lock)
|
||||
spin_lock_irqsave(mix->lock, flags);
|
||||
|
||||
if (mix->type == MMP_CLK_MIX_TYPE_V1
|
||||
|| mix->type == MMP_CLK_MIX_TYPE_V2)
|
||||
mux_div = readl(ri->reg_clk_ctrl);
|
||||
else
|
||||
mux_div = readl(ri->reg_clk_sel);
|
||||
|
||||
if (mix->lock)
|
||||
spin_unlock_irqrestore(mix->lock, flags);
|
||||
|
||||
width = mix->reg_info.width_mux;
|
||||
shift = mix->reg_info.shift_mux;
|
||||
|
||||
mux_val = MMP_CLK_BITS_GET_VAL(mux_div, width, shift);
|
||||
|
||||
return _get_mux(mix, mux_val);
|
||||
}
|
||||
|
||||
static unsigned long mmp_clk_mix_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct mmp_clk_mix *mix = to_clk_mix(hw);
|
||||
struct mmp_clk_mix_reg_info *ri = &mix->reg_info;
|
||||
unsigned long flags = 0;
|
||||
u32 mux_div = 0;
|
||||
u8 width, shift;
|
||||
unsigned int div;
|
||||
|
||||
if (mix->lock)
|
||||
spin_lock_irqsave(mix->lock, flags);
|
||||
|
||||
if (mix->type == MMP_CLK_MIX_TYPE_V1
|
||||
|| mix->type == MMP_CLK_MIX_TYPE_V2)
|
||||
mux_div = readl(ri->reg_clk_ctrl);
|
||||
else
|
||||
mux_div = readl(ri->reg_clk_sel);
|
||||
|
||||
if (mix->lock)
|
||||
spin_unlock_irqrestore(mix->lock, flags);
|
||||
|
||||
width = mix->reg_info.width_div;
|
||||
shift = mix->reg_info.shift_div;
|
||||
|
||||
div = _get_div(mix, MMP_CLK_BITS_GET_VAL(mux_div, width, shift));
|
||||
|
||||
return parent_rate / div;
|
||||
}
|
||||
|
||||
static int mmp_clk_set_parent(struct clk_hw *hw, u8 index)
|
||||
{
|
||||
struct mmp_clk_mix *mix = to_clk_mix(hw);
|
||||
struct mmp_clk_mix_clk_table *item;
|
||||
int i;
|
||||
u32 div_val, mux_val;
|
||||
|
||||
if (mix->table) {
|
||||
for (i = 0; i < mix->table_size; i++) {
|
||||
item = &mix->table[i];
|
||||
if (item->valid == 0)
|
||||
continue;
|
||||
if (item->parent_index == index)
|
||||
break;
|
||||
}
|
||||
if (i < mix->table_size) {
|
||||
div_val = _get_div_val(mix, item->divisor);
|
||||
mux_val = _get_mux_val(mix, item->parent_index);
|
||||
} else
|
||||
return -EINVAL;
|
||||
} else {
|
||||
mux_val = _get_mux_val(mix, index);
|
||||
div_val = 0;
|
||||
}
|
||||
|
||||
return _set_rate(mix, mux_val, div_val, 1, div_val ? 1 : 0);
|
||||
}
|
||||
|
||||
static int mmp_clk_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long best_parent_rate)
|
||||
{
|
||||
struct mmp_clk_mix *mix = to_clk_mix(hw);
|
||||
struct mmp_clk_mix_clk_table *item;
|
||||
unsigned long parent_rate;
|
||||
unsigned int best_divisor;
|
||||
struct clk *mix_clk, *parent;
|
||||
int i;
|
||||
|
||||
best_divisor = best_parent_rate / rate;
|
||||
|
||||
mix_clk = hw->clk;
|
||||
if (mix->table) {
|
||||
for (i = 0; i < mix->table_size; i++) {
|
||||
item = &mix->table[i];
|
||||
if (item->valid == 0)
|
||||
continue;
|
||||
parent = clk_get_parent_by_index(mix_clk,
|
||||
item->parent_index);
|
||||
parent_rate = __clk_get_rate(parent);
|
||||
if (parent_rate == best_parent_rate
|
||||
&& item->divisor == best_divisor)
|
||||
break;
|
||||
}
|
||||
if (i < mix->table_size)
|
||||
return _set_rate(mix,
|
||||
_get_mux_val(mix, item->parent_index),
|
||||
_get_div_val(mix, item->divisor),
|
||||
1, 1);
|
||||
else
|
||||
return -EINVAL;
|
||||
} else {
|
||||
for (i = 0; i < __clk_get_num_parents(mix_clk); i++) {
|
||||
parent = clk_get_parent_by_index(mix_clk, i);
|
||||
parent_rate = __clk_get_rate(parent);
|
||||
if (parent_rate == best_parent_rate)
|
||||
break;
|
||||
}
|
||||
if (i < __clk_get_num_parents(mix_clk))
|
||||
return _set_rate(mix, _get_mux_val(mix, i),
|
||||
_get_div_val(mix, best_divisor), 1, 1);
|
||||
else
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
static void mmp_clk_mix_init(struct clk_hw *hw)
|
||||
{
|
||||
struct mmp_clk_mix *mix = to_clk_mix(hw);
|
||||
|
||||
if (mix->table)
|
||||
_filter_clk_table(mix, mix->table, mix->table_size);
|
||||
}
|
||||
|
||||
const struct clk_ops mmp_clk_mix_ops = {
|
||||
.determine_rate = mmp_clk_mix_determine_rate,
|
||||
.set_rate_and_parent = mmp_clk_mix_set_rate_and_parent,
|
||||
.set_rate = mmp_clk_set_rate,
|
||||
.set_parent = mmp_clk_set_parent,
|
||||
.get_parent = mmp_clk_mix_get_parent,
|
||||
.recalc_rate = mmp_clk_mix_recalc_rate,
|
||||
.init = mmp_clk_mix_init,
|
||||
};
|
||||
|
||||
struct clk *mmp_clk_register_mix(struct device *dev,
|
||||
const char *name,
|
||||
const char **parent_names,
|
||||
u8 num_parents,
|
||||
unsigned long flags,
|
||||
struct mmp_clk_mix_config *config,
|
||||
spinlock_t *lock)
|
||||
{
|
||||
struct mmp_clk_mix *mix;
|
||||
struct clk *clk;
|
||||
struct clk_init_data init;
|
||||
size_t table_bytes;
|
||||
|
||||
mix = kzalloc(sizeof(*mix), GFP_KERNEL);
|
||||
if (!mix) {
|
||||
pr_err("%s:%s: could not allocate mmp mix clk\n",
|
||||
__func__, name);
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
|
||||
init.name = name;
|
||||
init.flags = flags | CLK_GET_RATE_NOCACHE;
|
||||
init.parent_names = parent_names;
|
||||
init.num_parents = num_parents;
|
||||
init.ops = &mmp_clk_mix_ops;
|
||||
|
||||
memcpy(&mix->reg_info, &config->reg_info, sizeof(config->reg_info));
|
||||
if (config->table) {
|
||||
table_bytes = sizeof(*config->table) * config->table_size;
|
||||
mix->table = kzalloc(table_bytes, GFP_KERNEL);
|
||||
if (!mix->table) {
|
||||
pr_err("%s:%s: could not allocate mmp mix table\n",
|
||||
__func__, name);
|
||||
kfree(mix);
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
memcpy(mix->table, config->table, table_bytes);
|
||||
mix->table_size = config->table_size;
|
||||
}
|
||||
|
||||
if (config->mux_table) {
|
||||
table_bytes = sizeof(u32) * num_parents;
|
||||
mix->mux_table = kzalloc(table_bytes, GFP_KERNEL);
|
||||
if (!mix->mux_table) {
|
||||
pr_err("%s:%s: could not allocate mmp mix mux-table\n",
|
||||
__func__, name);
|
||||
kfree(mix->table);
|
||||
kfree(mix);
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
memcpy(mix->mux_table, config->mux_table, table_bytes);
|
||||
}
|
||||
|
||||
mix->div_flags = config->div_flags;
|
||||
mix->mux_flags = config->mux_flags;
|
||||
mix->lock = lock;
|
||||
mix->hw.init = &init;
|
||||
|
||||
if (config->reg_info.bit_fc >= 32)
|
||||
mix->type = MMP_CLK_MIX_TYPE_V1;
|
||||
else if (config->reg_info.reg_clk_sel)
|
||||
mix->type = MMP_CLK_MIX_TYPE_V3;
|
||||
else
|
||||
mix->type = MMP_CLK_MIX_TYPE_V2;
|
||||
clk = clk_register(dev, &mix->hw);
|
||||
|
||||
if (IS_ERR(clk)) {
|
||||
kfree(mix->mux_table);
|
||||
kfree(mix->table);
|
||||
kfree(mix);
|
||||
}
|
||||
|
||||
return clk;
|
||||
}
|
@ -54,7 +54,7 @@
|
||||
|
||||
static DEFINE_SPINLOCK(clk_lock);
|
||||
|
||||
static struct clk_factor_masks uart_factor_masks = {
|
||||
static struct mmp_clk_factor_masks uart_factor_masks = {
|
||||
.factor = 2,
|
||||
.num_mask = 0x1fff,
|
||||
.den_mask = 0x1fff,
|
||||
@ -62,7 +62,7 @@ static struct clk_factor_masks uart_factor_masks = {
|
||||
.den_shift = 0,
|
||||
};
|
||||
|
||||
static struct clk_factor_tbl uart_factor_tbl[] = {
|
||||
static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
|
||||
{.num = 14634, .den = 2165}, /*14.745MHZ */
|
||||
{.num = 3521, .den = 689}, /*19.23MHZ */
|
||||
{.num = 9679, .den = 5728}, /*58.9824MHZ */
|
||||
@ -191,7 +191,7 @@ void __init mmp2_clk_init(void)
|
||||
clk = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
|
||||
mpmu_base + MPMU_UART_PLL,
|
||||
&uart_factor_masks, uart_factor_tbl,
|
||||
ARRAY_SIZE(uart_factor_tbl));
|
||||
ARRAY_SIZE(uart_factor_tbl), &clk_lock);
|
||||
clk_set_rate(clk, 14745600);
|
||||
clk_register_clkdev(clk, "uart_pll", NULL);
|
||||
|
||||
|
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Reference in New Issue
Block a user