forked from Minki/linux
clk: imx6: Fix procedure to switch the parent of LDB_DI_CLK
Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk
tree, the glitchy parent mux of ldb_di[x]_clk can cause a glitch to
enter the ldb_di_ipu_div divider. If the divider gets locked up, no
ldb_di[x]_clk is generated, and the LVDS display will hang when the
ipu_di_clk is sourced from ldb_di_clk.
To fix the problem, both the new and current parent of the ldb_di_clk
should be disabled before the switch. This patch ensures that correct
steps are followed when ldb_di_clk parent is switched in the beginning
of boot. The glitchy muxes are then registered as read-only. The clock
parent can be selected using the assigned-clocks and
assigned-clock-parents properties of the ccm device tree node:
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_MMDC_CH1_AXI>,
<&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
};
The issue is explained in detail in EB821 ("LDB Clock Switch Procedure &
i.MX6 Asynchronous Clock Switching Guidelines") [1].
[1] http://www.nxp.com/files/32bit/doc/eng_bulletin/EB821.pdf
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Akshay Bhat <akshay.bhat@timesys.com>
Tested-by Joshua Clayton <stillcompiling@gmail.com>
Tested-by: Charles Kang <Charles.Kang@advantech.com.tw>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Fabio Estevam
Shawn Guo
parent
03d576f202
commit
5d283b0838
@ -156,9 +156,90 @@ static struct clk ** const uart_clks[] __initconst = {
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NULL
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};
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#define CCM_CCDR 0x04
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static int ldb_di_sel_by_clock_id(int clock_id)
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{
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switch (clock_id) {
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case IMX6QDL_CLK_PLL5_VIDEO_DIV:
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if (clk_on_imx6q() &&
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imx_get_soc_revision() == IMX_CHIP_REVISION_1_0)
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return -ENOENT;
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return 0;
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case IMX6QDL_CLK_PLL2_PFD0_352M:
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return 1;
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case IMX6QDL_CLK_PLL2_PFD2_396M:
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return 2;
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case IMX6QDL_CLK_MMDC_CH1_AXI:
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return 3;
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case IMX6QDL_CLK_PLL3_USB_OTG:
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return 4;
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default:
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return -ENOENT;
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}
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}
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#define CCDR_MMDC_CH1_MASK BIT(16)
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static void of_assigned_ldb_sels(struct device_node *node,
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unsigned int *ldb_di0_sel,
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unsigned int *ldb_di1_sel)
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{
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struct of_phandle_args clkspec;
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int index, rc, num_parents;
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int parent, child, sel;
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num_parents = of_count_phandle_with_args(node, "assigned-clock-parents",
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"#clock-cells");
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for (index = 0; index < num_parents; index++) {
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rc = of_parse_phandle_with_args(node, "assigned-clock-parents",
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"#clock-cells", index, &clkspec);
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if (rc < 0) {
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/* skip empty (null) phandles */
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if (rc == -ENOENT)
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continue;
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else
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return;
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}
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if (clkspec.np != node || clkspec.args[0] >= IMX6QDL_CLK_END) {
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pr_err("ccm: parent clock %d not in ccm\n", index);
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return;
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}
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parent = clkspec.args[0];
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rc = of_parse_phandle_with_args(node, "assigned-clocks",
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"#clock-cells", index, &clkspec);
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if (rc < 0)
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return;
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if (clkspec.np != node || clkspec.args[0] >= IMX6QDL_CLK_END) {
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pr_err("ccm: child clock %d not in ccm\n", index);
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return;
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}
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child = clkspec.args[0];
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if (child != IMX6QDL_CLK_LDB_DI0_SEL &&
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child != IMX6QDL_CLK_LDB_DI1_SEL)
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continue;
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sel = ldb_di_sel_by_clock_id(parent);
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if (sel < 0) {
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pr_err("ccm: invalid ldb_di%d parent clock: %d\n",
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child == IMX6QDL_CLK_LDB_DI1_SEL, parent);
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continue;
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}
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if (child == IMX6QDL_CLK_LDB_DI0_SEL)
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*ldb_di0_sel = sel;
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if (child == IMX6QDL_CLK_LDB_DI1_SEL)
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*ldb_di1_sel = sel;
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}
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}
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#define CCM_CCDR 0x04
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#define CCM_CCSR 0x0c
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#define CCM_CS2CDR 0x2c
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#define CCDR_MMDC_CH1_MASK BIT(16)
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#define CCSR_PLL3_SW_CLK_SEL BIT(0)
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#define CS2CDR_LDB_DI0_CLK_SEL_SHIFT 9
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#define CS2CDR_LDB_DI1_CLK_SEL_SHIFT 12
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static void __init imx6q_mmdc_ch1_mask_handshake(void __iomem *ccm_base)
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{
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@ -169,10 +250,173 @@ static void __init imx6q_mmdc_ch1_mask_handshake(void __iomem *ccm_base)
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writel_relaxed(reg, ccm_base + CCM_CCDR);
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}
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/*
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* The only way to disable the MMDC_CH1 clock is to move it to pll3_sw_clk
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* via periph2_clk2_sel and then to disable pll3_sw_clk by selecting the
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* bypass clock source, since there is no CG bit for mmdc_ch1.
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*/
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static void mmdc_ch1_disable(void __iomem *ccm_base)
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{
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unsigned int reg;
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clk_set_parent(clk[IMX6QDL_CLK_PERIPH2_CLK2_SEL],
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clk[IMX6QDL_CLK_PLL3_USB_OTG]);
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/*
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* Handshake with mmdc_ch1 module must be masked when changing
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* periph2_clk_sel.
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*/
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clk_set_parent(clk[IMX6QDL_CLK_PERIPH2], clk[IMX6QDL_CLK_PERIPH2_CLK2]);
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/* Disable pll3_sw_clk by selecting the bypass clock source */
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reg = readl_relaxed(ccm_base + CCM_CCSR);
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reg |= CCSR_PLL3_SW_CLK_SEL;
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writel_relaxed(reg, ccm_base + CCM_CCSR);
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}
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static void mmdc_ch1_reenable(void __iomem *ccm_base)
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{
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unsigned int reg;
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/* Enable pll3_sw_clk by disabling the bypass */
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reg = readl_relaxed(ccm_base + CCM_CCSR);
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reg &= ~CCSR_PLL3_SW_CLK_SEL;
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writel_relaxed(reg, ccm_base + CCM_CCSR);
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clk_set_parent(clk[IMX6QDL_CLK_PERIPH2], clk[IMX6QDL_CLK_PERIPH2_PRE]);
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}
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/*
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* We have to follow a strict procedure when changing the LDB clock source,
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* otherwise we risk introducing a glitch that can lock up the LDB divider.
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* Things to keep in mind:
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*
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* 1. The current and new parent clock inputs to the mux must be disabled.
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* 2. The default clock input for ldb_di0/1_clk_sel is mmdc_ch1_axi, which
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* has no CG bit.
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* 3. pll2_pfd2_396m can not be gated if it is used as memory clock.
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* 4. In the RTL implementation of the LDB_DI_CLK_SEL muxes the top four
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* options are in one mux and the PLL3 option along with three unused
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* inputs is in a second mux. There is a third mux with two inputs used
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* to decide between the first and second 4-port mux:
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*
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* pll5_video_div 0 --|\
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* pll2_pfd0_352m 1 --| |_
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* pll2_pfd2_396m 2 --| | `-|\
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* mmdc_ch1_axi 3 --|/ | |
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* | |--
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* pll3_usb_otg 4 --|\ | |
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* 5 --| |_,-|/
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* 6 --| |
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* 7 --|/
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*
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* The ldb_di0/1_clk_sel[1:0] bits control both 4-port muxes at the same time.
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* The ldb_di0/1_clk_sel[2] bit controls the 2-port mux. The code below
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* switches the parent to the bottom mux first and then manipulates the top
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* mux to ensure that no glitch will enter the divider.
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*/
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static void init_ldb_clks(struct device_node *np, void __iomem *ccm_base)
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{
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unsigned int reg;
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unsigned int sel[2][4];
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int i;
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reg = readl_relaxed(ccm_base + CCM_CS2CDR);
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sel[0][0] = (reg >> CS2CDR_LDB_DI0_CLK_SEL_SHIFT) & 7;
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sel[1][0] = (reg >> CS2CDR_LDB_DI1_CLK_SEL_SHIFT) & 7;
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sel[0][3] = sel[0][2] = sel[0][1] = sel[0][0];
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sel[1][3] = sel[1][2] = sel[1][1] = sel[1][0];
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of_assigned_ldb_sels(np, &sel[0][3], &sel[1][3]);
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for (i = 0; i < 2; i++) {
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/* Warn if a glitch might have been introduced already */
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if (sel[i][0] != 3) {
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pr_warn("ccm: ldb_di%d_sel already changed from reset value: %d\n",
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i, sel[i][0]);
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}
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if (sel[i][0] == sel[i][3])
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continue;
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/* Only switch to or from pll2_pfd2_396m if it is disabled */
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if ((sel[i][0] == 2 || sel[i][3] == 2) &&
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(clk_get_parent(clk[IMX6QDL_CLK_PERIPH_PRE]) ==
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clk[IMX6QDL_CLK_PLL2_PFD2_396M])) {
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pr_err("ccm: ldb_di%d_sel: couldn't disable pll2_pfd2_396m\n",
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i);
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sel[i][3] = sel[i][2] = sel[i][1] = sel[i][0];
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continue;
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}
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/* First switch to the bottom mux */
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sel[i][1] = sel[i][0] | 4;
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/* Then configure the top mux before switching back to it */
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sel[i][2] = sel[i][3] | 4;
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pr_debug("ccm: switching ldb_di%d_sel: %d->%d->%d->%d\n", i,
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sel[i][0], sel[i][1], sel[i][2], sel[i][3]);
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}
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if (sel[0][0] == sel[0][3] && sel[1][0] == sel[1][3])
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return;
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mmdc_ch1_disable(ccm_base);
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for (i = 1; i < 4; i++) {
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reg = readl_relaxed(ccm_base + CCM_CS2CDR);
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reg &= ~((7 << CS2CDR_LDB_DI0_CLK_SEL_SHIFT) |
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(7 << CS2CDR_LDB_DI1_CLK_SEL_SHIFT));
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reg |= ((sel[0][i] << CS2CDR_LDB_DI0_CLK_SEL_SHIFT) |
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(sel[1][i] << CS2CDR_LDB_DI1_CLK_SEL_SHIFT));
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writel_relaxed(reg, ccm_base + CCM_CS2CDR);
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}
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mmdc_ch1_reenable(ccm_base);
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}
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#define CCM_ANALOG_PLL_VIDEO 0xa0
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#define CCM_ANALOG_PFD_480 0xf0
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#define CCM_ANALOG_PFD_528 0x100
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#define PLL_ENABLE BIT(13)
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#define PFD0_CLKGATE BIT(7)
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#define PFD1_CLKGATE BIT(15)
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#define PFD2_CLKGATE BIT(23)
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#define PFD3_CLKGATE BIT(31)
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static void disable_anatop_clocks(void __iomem *anatop_base)
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{
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unsigned int reg;
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/* Make sure PLL2 PFDs 0-2 are gated */
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reg = readl_relaxed(anatop_base + CCM_ANALOG_PFD_528);
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/* Cannot gate PFD2 if pll2_pfd2_396m is the parent of MMDC clock */
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if (clk_get_parent(clk[IMX6QDL_CLK_PERIPH_PRE]) ==
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clk[IMX6QDL_CLK_PLL2_PFD2_396M])
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reg |= PFD0_CLKGATE | PFD1_CLKGATE;
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else
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reg |= PFD0_CLKGATE | PFD1_CLKGATE | PFD2_CLKGATE;
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writel_relaxed(reg, anatop_base + CCM_ANALOG_PFD_528);
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/* Make sure PLL3 PFDs 0-3 are gated */
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reg = readl_relaxed(anatop_base + CCM_ANALOG_PFD_480);
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reg |= PFD0_CLKGATE | PFD1_CLKGATE | PFD2_CLKGATE | PFD3_CLKGATE;
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writel_relaxed(reg, anatop_base + CCM_ANALOG_PFD_480);
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/* Make sure PLL5 is disabled */
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reg = readl_relaxed(anatop_base + CCM_ANALOG_PLL_VIDEO);
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reg &= ~PLL_ENABLE;
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writel_relaxed(reg, anatop_base + CCM_ANALOG_PLL_VIDEO);
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}
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static void __init imx6q_clocks_init(struct device_node *ccm_node)
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{
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struct device_node *np;
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void __iomem *base;
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void __iomem *anatop_base, *base;
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int i;
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int ret;
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@ -185,7 +429,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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clk[IMX6QDL_CLK_ANACLK2] = imx_obtain_fixed_clock("anaclk2", 0);
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np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
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base = of_iomap(np, 0);
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anatop_base = base = of_iomap(np, 0);
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WARN_ON(!base);
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/* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */
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@ -310,8 +554,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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base = of_iomap(np, 0);
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WARN_ON(!base);
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imx6q_mmdc_ch1_mask_handshake(base);
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/* name reg shift width parent_names num_parents */
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clk[IMX6QDL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
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clk[IMX6QDL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
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@ -345,6 +587,18 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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clk[IMX6QDL_CLK_GPU3D_SHADER_SEL] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
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clk[IMX6QDL_CLK_IPU1_SEL] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
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clk[IMX6QDL_CLK_IPU2_SEL] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
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disable_anatop_clocks(anatop_base);
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imx6q_mmdc_ch1_mask_handshake(base);
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/*
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* The LDB_DI0/1_SEL muxes are registered read-only due to a hardware
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* bug. Set the muxes to the requested values before registering the
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* ldb_di_sel clocks.
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*/
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init_ldb_clks(np, base);
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clk[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_ldb("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels));
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clk[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_ldb("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels));
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clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
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