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drm/i915/guc: Remove GUC_CTL_DEVICE_INFO parameter

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It looks that GuC does not actively use GUC_CTL_DEVICE_INFO parameter
where we are passing GT type and Core family values.
Let's stop/remove setup of this parameter and remove related
definitions.

v2: (this time without squashed HAX)
  - New title and description
  - Remove also GUC_CORE_FAMILY_* definitions (Michel)
v3:
  - The removed define GUC_CTL_DEVICE_INFO has been restored (Michel)
  - Updated description (Sagar)
v4: rebase

Signed-off-by: Piotr Piórkowski <piotr.piorkowski@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Cc: John A Spotswood <john.a.spotswood@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michel Thierry <michel.thierry@intel.com>
Acked-by: Michel Thierry <michel.thierry@intel.com>
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20180413085245.57206-1-piotr.piorkowski@intel.com
This commit is contained in:
Piorkowski, Piotr 2018-04-13 10:52:45 +02:00 committed by Chris Wilson
parent fadec6eefe
commit 5bbed0b38d
2 changed files with 0 additions and 29 deletions
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24
drivers/gpu/drm/i915/intel_guc.c
View File

@ -203,26 +203,6 @@ void intel_guc_fini(struct intel_guc *guc)
guc_shared_data_destroy(guc); guc_shared_data_destroy(guc);
} }
static u32 get_gt_type(struct drm_i915_private *dev_priv)
{
/* XXX: GT type based on PCI device ID? field seems unused by fw */
return 0;
}
static u32 get_core_family(struct drm_i915_private *dev_priv)
{
u32 gen = INTEL_GEN(dev_priv);
switch (gen) {
case 9:
return GUC_CORE_FAMILY_GEN9;
default:
MISSING_CASE(gen);
return GUC_CORE_FAMILY_UNKNOWN;
}
}
static u32 get_log_control_flags(void) static u32 get_log_control_flags(void)
{ {
u32 level = i915_modparams.guc_log_level; u32 level = i915_modparams.guc_log_level;
@ -255,10 +235,6 @@ void intel_guc_init_params(struct intel_guc *guc)
memset(params, 0, sizeof(params)); memset(params, 0, sizeof(params));
params[GUC_CTL_DEVICE_INFO] |=
(get_gt_type(dev_priv) << GUC_CTL_GT_TYPE_SHIFT) |
(get_core_family(dev_priv) << GUC_CTL_CORE_FAMILY_SHIFT);
/* /*
* GuC ARAT increment is 10 ns. GuC default scheduler quantum is one * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
* second. This ARAR is calculated by: * second. This ARAR is calculated by:

5
drivers/gpu/drm/i915/intel_guc_fwif.h
View File

@ -23,9 +23,6 @@
#ifndef _INTEL_GUC_FWIF_H #ifndef _INTEL_GUC_FWIF_H
#define _INTEL_GUC_FWIF_H #define _INTEL_GUC_FWIF_H
#define GUC_CORE_FAMILY_GEN9 12
#define GUC_CORE_FAMILY_UNKNOWN 0x7fffffff
#define GUC_CLIENT_PRIORITY_KMD_HIGH 0 #define GUC_CLIENT_PRIORITY_KMD_HIGH 0
#define GUC_CLIENT_PRIORITY_HIGH 1 #define GUC_CLIENT_PRIORITY_HIGH 1
#define GUC_CLIENT_PRIORITY_KMD_NORMAL 2 #define GUC_CLIENT_PRIORITY_KMD_NORMAL 2
@ -82,8 +79,6 @@
#define GUC_CTL_ARAT_LOW 2 #define GUC_CTL_ARAT_LOW 2
#define GUC_CTL_DEVICE_INFO 3 #define GUC_CTL_DEVICE_INFO 3
#define GUC_CTL_GT_TYPE_SHIFT 0
#define GUC_CTL_CORE_FAMILY_SHIFT 7
#define GUC_CTL_LOG_PARAMS 4 #define GUC_CTL_LOG_PARAMS 4
#define GUC_LOG_VALID (1 << 0) #define GUC_LOG_VALID (1 << 0)