Merge tag 'amd-drm-next-5.11-2020-11-05' of git://people.freedesktop.org/~agd5f/linux into drm-next
amd-drm-next-5.11-2020-11-05: amdgpu: - Add initial support for Vangogh - Add support for Green Sardine - Add initial support for Dimgrey Cavefish - Scatter/Gather display support for Renoir - Updates for Sienna Cichlid - Updates for Navy Flounder - SMU7 power improvements - Modifier support for gfx9+ - CI BACO fixes - Arcturus SMU fixes - Lots of code cleanups - DC fixes - Kernel doc fixes - Add more GPU HW client information to page fault error logging - MPO clock tuning for RV - FP fixes for DCN3 on ARM and PPC radeon: - Expose voltage via hwmon on Sumo APUs amdkfd: - Fix unique id handling - Misc fixes From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201105222749.201798-1-alexander.deucher@amd.com
This commit is contained in:
Dave Airlie
@@ -667,7 +667,7 @@ struct drm_amdgpu_cs_chunk_data {
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};
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};
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/**
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/*
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* Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU
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*
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*/
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@@ -724,6 +724,8 @@ struct drm_amdgpu_cs_chunk_data {
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#define AMDGPU_INFO_FW_TA 0x13
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/* Subquery id: Query DMCUB firmware version */
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#define AMDGPU_INFO_FW_DMCUB 0x14
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/* Subquery id: Query TOC firmware version */
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#define AMDGPU_INFO_FW_TOC 0x15
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/* number of bytes moved for TTM migration */
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#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
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@@ -946,6 +948,7 @@ struct drm_amdgpu_info_firmware {
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#define AMDGPU_VRAM_TYPE_DDR3 7
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#define AMDGPU_VRAM_TYPE_DDR4 8
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#define AMDGPU_VRAM_TYPE_GDDR6 9
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#define AMDGPU_VRAM_TYPE_DDR5 10
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struct drm_amdgpu_info_device {
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/** PCI Device ID */
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@@ -1083,6 +1086,7 @@ struct drm_amdgpu_info_vce_clock_table {
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#define AMDGPU_FAMILY_AI 141 /* Vega10 */
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#define AMDGPU_FAMILY_RV 142 /* Raven */
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#define AMDGPU_FAMILY_NV 143 /* Navi10 */
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#define AMDGPU_FAMILY_VGH 144 /* Van Gogh */
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#if defined(__cplusplus)
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}
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@@ -1095,6 +1095,121 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
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*/
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#define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0)
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/*
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* AMD modifiers
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*
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* Memory layout:
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*
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* without DCC:
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* - main surface
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*
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* with DCC & without DCC_RETILE:
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* - main surface in plane 0
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* - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set)
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*
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* with DCC & DCC_RETILE:
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* - main surface in plane 0
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* - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned)
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* - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned)
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*
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* For multi-plane formats the above surfaces get merged into one plane for
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* each format plane, based on the required alignment only.
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*/
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#define AMD_FMT_MOD fourcc_mod_code(AMD, 0)
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#define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD)
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/* Reserve 0 for GFX8 and older */
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#define AMD_FMT_MOD_TILE_VER_GFX9 1
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#define AMD_FMT_MOD_TILE_VER_GFX10 2
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#define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3
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/*
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* 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical
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* version.
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*/
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#define AMD_FMT_MOD_TILE_GFX9_64K_S 9
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/*
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* 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has
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* GFX9 as canonical version.
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*/
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#define AMD_FMT_MOD_TILE_GFX9_64K_D 10
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#define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25
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#define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26
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#define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27
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#define AMD_FMT_MOD_DCC_BLOCK_64B 0
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#define AMD_FMT_MOD_DCC_BLOCK_128B 1
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#define AMD_FMT_MOD_DCC_BLOCK_256B 2
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#define AMD_FMT_MOD_TILE_VERSION_SHIFT 0
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#define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF
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#define AMD_FMT_MOD_TILE_SHIFT 8
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#define AMD_FMT_MOD_TILE_MASK 0x1F
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/* Whether DCC compression is enabled. */
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#define AMD_FMT_MOD_DCC_SHIFT 13
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#define AMD_FMT_MOD_DCC_MASK 0x1
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/*
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* Whether to include two DCC surfaces, one which is rb & pipe aligned, and
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* one which is not-aligned.
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*/
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#define AMD_FMT_MOD_DCC_RETILE_SHIFT 14
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#define AMD_FMT_MOD_DCC_RETILE_MASK 0x1
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/* Only set if DCC_RETILE = false */
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#define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15
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#define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1
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#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16
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#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1
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#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17
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#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1
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#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18
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#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x1
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/*
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* DCC supports embedding some clear colors directly in the DCC surface.
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* However, on older GPUs the rendering HW ignores the embedded clear color
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* and prefers the driver provided color. This necessitates doing a fastclear
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* eliminate operation before a process transfers control.
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*
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* If this bit is set that means the fastclear eliminate is not needed for these
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* embeddable colors.
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*/
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#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 19
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#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1
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/*
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* The below fields are for accounting for per GPU differences. These are only
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* relevant for GFX9 and later and if the tile field is *_X/_T.
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*
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* PIPE_XOR_BITS = always needed
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* BANK_XOR_BITS = only for TILE_VER_GFX9
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* PACKERS = only for TILE_VER_GFX10_RBPLUS
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* RB = only for TILE_VER_GFX9 & DCC
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* PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN)
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*/
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#define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 20
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#define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7
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#define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 23
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#define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7
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#define AMD_FMT_MOD_PACKERS_SHIFT 26 /* aliases with BANK_XOR_BITS */
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#define AMD_FMT_MOD_PACKERS_MASK 0x7
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#define AMD_FMT_MOD_RB_SHIFT 29
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#define AMD_FMT_MOD_RB_MASK 0x7
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#define AMD_FMT_MOD_PIPE_SHIFT 32
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#define AMD_FMT_MOD_PIPE_MASK 0x7
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#define AMD_FMT_MOD_SET(field, value) \
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((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT)
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#define AMD_FMT_MOD_GET(field, value) \
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(((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK)
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#define AMD_FMT_MOD_CLEAR(field) \
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(~((uint64_t)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT))
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#if defined(__cplusplus)
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}
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#endif
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