forked from Minki/linux
clk: oxnas: Refactor to make use of devm_clk_hw_register()
Make usage of static tables identified by the OF match table to feed devm_clk_hw_register() and use of_clk_add_hw_provider(). This structure is cleaner and simplifies adding new SoC support while having common probe and gate ops code. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20161005150752.22618-5-narmstrong@baylibre.com
This commit is contained in:
Neil Armstrong
Michael Turquette
parent
1a2cfd0070
commit
5a9e54a81b
@ -20,18 +20,29 @@
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/stringify.h>
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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#include <dt-bindings/clock/oxsemi,ox810se.h>
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/* Standard regmap gate clocks */
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struct clk_oxnas_gate {
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struct clk_hw hw;
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signed char bit;
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unsigned int bit;
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struct regmap *regmap;
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};
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struct oxnas_stdclk_data {
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struct clk_hw_onecell_data *onecell_data;
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struct clk_oxnas_gate **gates;
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unsigned int ngates;
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struct clk_oxnas_pll **plls;
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unsigned int nplls;
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};
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/* Regmap offsets */
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#define CLK_STAT_REGOFFSET 0x24
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#define CLK_SET_REGOFFSET 0x2c
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@ -77,7 +88,7 @@ static const struct clk_ops oxnas_clk_gate_ops = {
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.is_enabled = oxnas_clk_gate_is_enabled,
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};
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static const char *const oxnas_clk_parents[] = {
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static const char *const osc_parents[] = {
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"oscillator",
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};
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@ -85,63 +96,81 @@ static const char *const eth_parents[] = {
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"gmacclk",
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};
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#define DECLARE_STD_CLKP(__clk, __parent) \
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static const struct clk_init_data clk_##__clk##_init = { \
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.name = __stringify(__clk), \
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.ops = &oxnas_clk_gate_ops, \
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.parent_names = __parent, \
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.num_parents = ARRAY_SIZE(__parent), \
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#define OXNAS_GATE(_name, _bit, _parents) \
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struct clk_oxnas_gate _name = { \
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.bit = (_bit), \
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.hw.init = &(struct clk_init_data) { \
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.name = #_name, \
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.ops = &oxnas_clk_gate_ops, \
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.parent_names = _parents, \
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.num_parents = ARRAY_SIZE(_parents), \
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.flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \
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}, \
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}
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#define DECLARE_STD_CLK(__clk) DECLARE_STD_CLKP(__clk, oxnas_clk_parents)
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static OXNAS_GATE(ox810se_leon, 0, osc_parents);
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static OXNAS_GATE(ox810se_dma_sgdma, 1, osc_parents);
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static OXNAS_GATE(ox810se_cipher, 2, osc_parents);
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static OXNAS_GATE(ox810se_sata, 4, osc_parents);
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static OXNAS_GATE(ox810se_audio, 5, osc_parents);
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static OXNAS_GATE(ox810se_usbmph, 6, osc_parents);
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static OXNAS_GATE(ox810se_etha, 7, eth_parents);
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static OXNAS_GATE(ox810se_pciea, 8, osc_parents);
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static OXNAS_GATE(ox810se_nand, 9, osc_parents);
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/* Hardware Bit - Clock association */
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struct clk_oxnas_init_data {
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unsigned long bit;
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const struct clk_init_data *clk_init;
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static struct clk_oxnas_gate *ox810se_gates[] = {
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&ox810se_leon,
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&ox810se_dma_sgdma,
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&ox810se_cipher,
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&ox810se_sata,
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&ox810se_audio,
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&ox810se_usbmph,
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&ox810se_etha,
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&ox810se_pciea,
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&ox810se_nand,
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};
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/* Clk init data declaration */
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DECLARE_STD_CLK(leon);
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DECLARE_STD_CLK(dma_sgdma);
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DECLARE_STD_CLK(cipher);
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DECLARE_STD_CLK(sata);
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DECLARE_STD_CLK(audio);
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DECLARE_STD_CLK(usbmph);
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DECLARE_STD_CLKP(etha, eth_parents);
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DECLARE_STD_CLK(pciea);
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DECLARE_STD_CLK(nand);
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/* Table index is clock indice */
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static const struct clk_oxnas_init_data clk_oxnas_init[] = {
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[0] = {0, &clk_leon_init},
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[1] = {1, &clk_dma_sgdma_init},
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[2] = {2, &clk_cipher_init},
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/* Skip & Do not touch to DDR clock */
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[3] = {4, &clk_sata_init},
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[4] = {5, &clk_audio_init},
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[5] = {6, &clk_usbmph_init},
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[6] = {7, &clk_etha_init},
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[7] = {8, &clk_pciea_init},
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[8] = {9, &clk_nand_init},
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static struct clk_hw_onecell_data ox810se_hw_onecell_data = {
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.hws = {
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[CLK_810_LEON] = &ox810se_leon.hw,
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[CLK_810_DMA_SGDMA] = &ox810se_dma_sgdma.hw,
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[CLK_810_CIPHER] = &ox810se_cipher.hw,
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[CLK_810_SATA] = &ox810se_sata.hw,
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[CLK_810_AUDIO] = &ox810se_audio.hw,
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[CLK_810_USBMPH] = &ox810se_usbmph.hw,
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[CLK_810_ETHA] = &ox810se_etha.hw,
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[CLK_810_PCIEA] = &ox810se_pciea.hw,
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[CLK_810_NAND] = &ox810se_nand.hw,
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},
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.num = ARRAY_SIZE(ox810se_gates),
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};
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struct clk_oxnas_data {
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struct clk_oxnas_gate clk_oxnas[ARRAY_SIZE(clk_oxnas_init)];
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struct clk_onecell_data onecell_data[ARRAY_SIZE(clk_oxnas_init)];
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struct clk *clks[ARRAY_SIZE(clk_oxnas_init)];
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static struct oxnas_stdclk_data ox810se_stdclk_data = {
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.onecell_data = &ox810se_hw_onecell_data,
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.gates = ox810se_gates,
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.ngates = ARRAY_SIZE(ox810se_gates),
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};
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static const struct of_device_id oxnas_stdclk_dt_ids[] = {
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{ .compatible = "oxsemi,ox810se-stdclk", &ox810se_stdclk_data },
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{ }
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};
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static int oxnas_stdclk_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct clk_oxnas_data *clk_oxnas;
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const struct oxnas_stdclk_data *data;
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const struct of_device_id *id;
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struct regmap *regmap;
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int ret;
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int i;
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clk_oxnas = devm_kzalloc(&pdev->dev, sizeof(*clk_oxnas), GFP_KERNEL);
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if (!clk_oxnas)
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return -ENOMEM;
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id = of_match_device(oxnas_stdclk_dt_ids, &pdev->dev);
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if (!id)
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return -ENODEV;
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data = id->data;
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regmap = syscon_node_to_regmap(of_get_parent(np));
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if (IS_ERR(regmap)) {
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@ -149,32 +178,23 @@ static int oxnas_stdclk_probe(struct platform_device *pdev)
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return PTR_ERR(regmap);
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}
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for (i = 0; i < ARRAY_SIZE(clk_oxnas_init); i++) {
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struct clk_oxnas_gate *_clk;
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for (i = 0 ; i < data->ngates ; ++i)
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data->gates[i]->regmap = regmap;
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_clk = &clk_oxnas->clk_oxnas[i];
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_clk->bit = clk_oxnas_init[i].bit;
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_clk->hw.init = clk_oxnas_init[i].clk_init;
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_clk->regmap = regmap;
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for (i = 0; i < data->onecell_data->num; i++) {
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if (!data->onecell_data->hws[i])
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continue;
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clk_oxnas->clks[i] =
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devm_clk_register(&pdev->dev, &_clk->hw);
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if (WARN_ON(IS_ERR(clk_oxnas->clks[i])))
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return PTR_ERR(clk_oxnas->clks[i]);
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ret = devm_clk_hw_register(&pdev->dev,
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data->onecell_data->hws[i]);
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if (ret)
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return ret;
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}
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clk_oxnas->onecell_data->clks = clk_oxnas->clks;
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clk_oxnas->onecell_data->clk_num = ARRAY_SIZE(clk_oxnas_init);
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return of_clk_add_provider(np, of_clk_src_onecell_get,
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clk_oxnas->onecell_data);
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return of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
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data->onecell_data);
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}
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static const struct of_device_id oxnas_stdclk_dt_ids[] = {
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{ .compatible = "oxsemi,ox810se-stdclk" },
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{ }
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};
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static struct platform_driver oxnas_stdclk_driver = {
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.probe = oxnas_stdclk_probe,
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.driver = {
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