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ARM: dts: exynos5420: add input clocks to audss clock controller

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Specify the remaining input clocks (pll_ref, pll_in, and sclk_pcm_in)
for the AudioSS clock controller.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
This commit is contained in:
Andrew Bresticker 2013-09-25 14:12:52 -07:00 committed by Tomasz Figa
parent 3538a2cf0e
commit 59d711e9dd
1 changed files with 2 additions and 2 deletions
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4
arch/arm/boot/dts/exynos5420.dtsi
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@ -76,8 +76,8 @@
compatible = "samsung,exynos5420-audss-clock";
reg = <0x03810000 0x0C>;
#clock-cells = <1>;
clocks = <&clock 148>;
clock-names = "sclk_audio";
clocks = <&clock 1>, <&clock 5>, <&clock 148>, <&clock 149>;
clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
};
codec@11000000 {