forked from Minki/linux
serial: Add driver for LPC32xx High Speed UARTs
This patch adds a driver for the 3 High Speed UARTs of the LPC32xx SoC that support up to 921600bps. These UARTs are different from the 4 "Standard" UARTs of the LPC32xx. Signed-off-by: Roland Stigge <stigge@antcom.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Roland Stigge
Greg Kroah-Hartman
parent
e4305f0c50
commit
596f93f50e
@ -0,0 +1,14 @@
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* NXP LPC32xx SoC High Speed UART
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Required properties:
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- compatible: Should be "nxp,lpc3220-hsuart"
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- reg: Should contain registers location and length
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- interrupts: Should contain interrupt
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Example:
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uart1: serial@40014000 {
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compatible = "nxp,lpc3220-hsuart";
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reg = <0x40014000 0x1000>;
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interrupts = <26 0>;
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};
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@ -704,6 +704,25 @@ config SERIAL_PNX8XXX_CONSOLE
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If you have a MIPS-based Philips SoC such as PNX8550 or PNX8330
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and you want to use serial console, say Y. Otherwise, say N.
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config SERIAL_HS_LPC32XX
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tristate "LPC32XX high speed serial port support"
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depends on ARCH_LPC32XX && OF
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select SERIAL_CORE
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help
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Support for the LPC32XX high speed serial ports (up to 900kbps).
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Those are UARTs completely different from the Standard UARTs on the
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LPC32XX SoC.
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Choose M or Y here to build this driver.
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config SERIAL_HS_LPC32XX_CONSOLE
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bool "Enable LPC32XX high speed UART serial console"
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depends on SERIAL_HS_LPC32XX
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select SERIAL_CORE_CONSOLE
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help
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If you would like to be able to use one of the high speed serial
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ports on the LPC32XX as the console, you can do so by answering
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Y to this option.
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config SERIAL_CORE
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tristate
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@ -34,6 +34,7 @@ obj-$(CONFIG_SERIAL_MUX) += mux.o
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obj-$(CONFIG_SERIAL_68328) += 68328serial.o
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obj-$(CONFIG_SERIAL_MCF) += mcf.o
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obj-$(CONFIG_SERIAL_PMACZILOG) += pmac_zilog.o
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obj-$(CONFIG_SERIAL_HS_LPC32XX) += lpc32xx_hs.o
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obj-$(CONFIG_SERIAL_DZ) += dz.o
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obj-$(CONFIG_SERIAL_ZS) += zs.o
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obj-$(CONFIG_SERIAL_SH_SCI) += sh-sci.o
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823
drivers/tty/serial/lpc32xx_hs.c
Normal file
823
drivers/tty/serial/lpc32xx_hs.c
Normal file
@ -0,0 +1,823 @@
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/*
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* High Speed Serial Ports on NXP LPC32xx SoC
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*
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* Authors: Kevin Wells <kevin.wells@nxp.com>
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* Roland Stigge <stigge@antcom.de>
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*
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* Copyright (C) 2010 NXP Semiconductors
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* Copyright (C) 2012 Roland Stigge
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/module.h>
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#include <linux/ioport.h>
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#include <linux/init.h>
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#include <linux/console.h>
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#include <linux/sysrq.h>
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#include <linux/tty.h>
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#include <linux/tty_flip.h>
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#include <linux/serial_core.h>
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#include <linux/serial.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/nmi.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/gpio.h>
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#include <linux/of.h>
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#include <mach/platform.h>
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#include <mach/hardware.h>
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/*
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* High Speed UART register offsets
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*/
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#define LPC32XX_HSUART_FIFO(x) ((x) + 0x00)
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#define LPC32XX_HSUART_LEVEL(x) ((x) + 0x04)
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#define LPC32XX_HSUART_IIR(x) ((x) + 0x08)
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#define LPC32XX_HSUART_CTRL(x) ((x) + 0x0C)
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#define LPC32XX_HSUART_RATE(x) ((x) + 0x10)
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#define LPC32XX_HSU_BREAK_DATA (1 << 10)
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#define LPC32XX_HSU_ERROR_DATA (1 << 9)
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#define LPC32XX_HSU_RX_EMPTY (1 << 8)
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#define LPC32XX_HSU_TX_LEV(n) (((n) >> 8) & 0xFF)
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#define LPC32XX_HSU_RX_LEV(n) ((n) & 0xFF)
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#define LPC32XX_HSU_TX_INT_SET (1 << 6)
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#define LPC32XX_HSU_RX_OE_INT (1 << 5)
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#define LPC32XX_HSU_BRK_INT (1 << 4)
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#define LPC32XX_HSU_FE_INT (1 << 3)
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#define LPC32XX_HSU_RX_TIMEOUT_INT (1 << 2)
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#define LPC32XX_HSU_RX_TRIG_INT (1 << 1)
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#define LPC32XX_HSU_TX_INT (1 << 0)
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#define LPC32XX_HSU_HRTS_INV (1 << 21)
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#define LPC32XX_HSU_HRTS_TRIG_8B (0x0 << 19)
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#define LPC32XX_HSU_HRTS_TRIG_16B (0x1 << 19)
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#define LPC32XX_HSU_HRTS_TRIG_32B (0x2 << 19)
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#define LPC32XX_HSU_HRTS_TRIG_48B (0x3 << 19)
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#define LPC32XX_HSU_HRTS_EN (1 << 18)
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#define LPC32XX_HSU_TMO_DISABLED (0x0 << 16)
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#define LPC32XX_HSU_TMO_INACT_4B (0x1 << 16)
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#define LPC32XX_HSU_TMO_INACT_8B (0x2 << 16)
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#define LPC32XX_HSU_TMO_INACT_16B (0x3 << 16)
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#define LPC32XX_HSU_HCTS_INV (1 << 15)
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#define LPC32XX_HSU_HCTS_EN (1 << 14)
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#define LPC32XX_HSU_OFFSET(n) ((n) << 9)
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#define LPC32XX_HSU_BREAK (1 << 8)
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#define LPC32XX_HSU_ERR_INT_EN (1 << 7)
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#define LPC32XX_HSU_RX_INT_EN (1 << 6)
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#define LPC32XX_HSU_TX_INT_EN (1 << 5)
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#define LPC32XX_HSU_RX_TL1B (0x0 << 2)
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#define LPC32XX_HSU_RX_TL4B (0x1 << 2)
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#define LPC32XX_HSU_RX_TL8B (0x2 << 2)
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#define LPC32XX_HSU_RX_TL16B (0x3 << 2)
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#define LPC32XX_HSU_RX_TL32B (0x4 << 2)
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#define LPC32XX_HSU_RX_TL48B (0x5 << 2)
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#define LPC32XX_HSU_TX_TLEMPTY (0x0 << 0)
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#define LPC32XX_HSU_TX_TL0B (0x0 << 0)
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#define LPC32XX_HSU_TX_TL4B (0x1 << 0)
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#define LPC32XX_HSU_TX_TL8B (0x2 << 0)
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#define LPC32XX_HSU_TX_TL16B (0x3 << 0)
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#define MODNAME "lpc32xx_hsuart"
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struct lpc32xx_hsuart_port {
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struct uart_port port;
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};
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#define FIFO_READ_LIMIT 128
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#define MAX_PORTS 3
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#define LPC32XX_TTY_NAME "ttyTX"
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static struct lpc32xx_hsuart_port lpc32xx_hs_ports[MAX_PORTS];
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#ifdef CONFIG_SERIAL_HS_LPC32XX_CONSOLE
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static void wait_for_xmit_empty(struct uart_port *port)
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{
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unsigned int timeout = 10000;
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do {
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if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(
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port->membase))) == 0)
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break;
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if (--timeout == 0)
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break;
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udelay(1);
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} while (1);
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}
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static void wait_for_xmit_ready(struct uart_port *port)
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{
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unsigned int timeout = 10000;
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while (1) {
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if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(
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port->membase))) < 32)
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break;
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if (--timeout == 0)
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break;
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udelay(1);
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}
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}
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static void lpc32xx_hsuart_console_putchar(struct uart_port *port, int ch)
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{
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wait_for_xmit_ready(port);
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writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase));
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}
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static void lpc32xx_hsuart_console_write(struct console *co, const char *s,
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unsigned int count)
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{
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struct lpc32xx_hsuart_port *up = &lpc32xx_hs_ports[co->index];
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unsigned long flags;
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int locked = 1;
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touch_nmi_watchdog();
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local_irq_save(flags);
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if (up->port.sysrq)
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locked = 0;
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else if (oops_in_progress)
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locked = spin_trylock(&up->port.lock);
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else
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spin_lock(&up->port.lock);
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uart_console_write(&up->port, s, count, lpc32xx_hsuart_console_putchar);
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wait_for_xmit_empty(&up->port);
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if (locked)
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spin_unlock(&up->port.lock);
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local_irq_restore(flags);
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}
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static int __init lpc32xx_hsuart_console_setup(struct console *co,
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char *options)
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{
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struct uart_port *port;
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int baud = 115200;
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int bits = 8;
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int parity = 'n';
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int flow = 'n';
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if (co->index >= MAX_PORTS)
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co->index = 0;
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port = &lpc32xx_hs_ports[co->index].port;
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if (!port->membase)
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return -ENODEV;
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if (options)
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uart_parse_options(options, &baud, &parity, &bits, &flow);
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return uart_set_options(port, co, baud, parity, bits, flow);
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}
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static struct uart_driver lpc32xx_hsuart_reg;
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static struct console lpc32xx_hsuart_console = {
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.name = LPC32XX_TTY_NAME,
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.write = lpc32xx_hsuart_console_write,
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.device = uart_console_device,
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.setup = lpc32xx_hsuart_console_setup,
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.flags = CON_PRINTBUFFER,
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.index = -1,
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.data = &lpc32xx_hsuart_reg,
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};
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static int __init lpc32xx_hsuart_console_init(void)
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{
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register_console(&lpc32xx_hsuart_console);
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return 0;
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}
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console_initcall(lpc32xx_hsuart_console_init);
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#define LPC32XX_HSUART_CONSOLE (&lpc32xx_hsuart_console)
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#else
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#define LPC32XX_HSUART_CONSOLE NULL
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#endif
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static struct uart_driver lpc32xx_hs_reg = {
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.owner = THIS_MODULE,
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.driver_name = MODNAME,
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.dev_name = LPC32XX_TTY_NAME,
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.nr = MAX_PORTS,
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.cons = LPC32XX_HSUART_CONSOLE,
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};
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static int uarts_registered;
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static unsigned int __serial_get_clock_div(unsigned long uartclk,
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unsigned long rate)
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{
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u32 div, goodrate, hsu_rate, l_hsu_rate, comprate;
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u32 rate_diff;
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/* Find the closest divider to get the desired clock rate */
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div = uartclk / rate;
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goodrate = hsu_rate = (div / 14) - 1;
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if (hsu_rate != 0)
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hsu_rate--;
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/* Tweak divider */
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l_hsu_rate = hsu_rate + 3;
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rate_diff = 0xFFFFFFFF;
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while (hsu_rate < l_hsu_rate) {
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comprate = uartclk / ((hsu_rate + 1) * 14);
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if (abs(comprate - rate) < rate_diff) {
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goodrate = hsu_rate;
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rate_diff = abs(comprate - rate);
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}
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hsu_rate++;
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}
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if (hsu_rate > 0xFF)
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hsu_rate = 0xFF;
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return goodrate;
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}
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static void __serial_uart_flush(struct uart_port *port)
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{
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u32 tmp;
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int cnt = 0;
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while ((readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) &&
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(cnt++ < FIFO_READ_LIMIT))
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tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
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}
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static void __serial_lpc32xx_rx(struct uart_port *port)
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{
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unsigned int tmp, flag;
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struct tty_struct *tty = tty_port_tty_get(&port->state->port);
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if (!tty) {
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/* Discard data: no tty available */
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while (!(readl(LPC32XX_HSUART_FIFO(port->membase)) &
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LPC32XX_HSU_RX_EMPTY))
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;
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return;
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}
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/* Read data from FIFO and push into terminal */
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tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
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while (!(tmp & LPC32XX_HSU_RX_EMPTY)) {
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flag = TTY_NORMAL;
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port->icount.rx++;
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if (tmp & LPC32XX_HSU_ERROR_DATA) {
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/* Framing error */
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writel(LPC32XX_HSU_FE_INT,
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LPC32XX_HSUART_IIR(port->membase));
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port->icount.frame++;
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flag = TTY_FRAME;
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tty_insert_flip_char(tty, 0, TTY_FRAME);
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}
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tty_insert_flip_char(tty, (tmp & 0xFF), flag);
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tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
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}
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tty_flip_buffer_push(tty);
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tty_kref_put(tty);
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}
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static void __serial_lpc32xx_tx(struct uart_port *port)
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{
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struct circ_buf *xmit = &port->state->xmit;
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unsigned int tmp;
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if (port->x_char) {
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writel((u32)port->x_char, LPC32XX_HSUART_FIFO(port->membase));
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port->icount.tx++;
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port->x_char = 0;
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return;
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}
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if (uart_circ_empty(xmit) || uart_tx_stopped(port))
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goto exit_tx;
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/* Transfer data */
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while (LPC32XX_HSU_TX_LEV(readl(
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LPC32XX_HSUART_LEVEL(port->membase))) < 64) {
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writel((u32) xmit->buf[xmit->tail],
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LPC32XX_HSUART_FIFO(port->membase));
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
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port->icount.tx++;
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if (uart_circ_empty(xmit))
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break;
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}
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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uart_write_wakeup(port);
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exit_tx:
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if (uart_circ_empty(xmit)) {
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tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
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tmp &= ~LPC32XX_HSU_TX_INT_EN;
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writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
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}
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}
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static irqreturn_t serial_lpc32xx_interrupt(int irq, void *dev_id)
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{
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struct uart_port *port = dev_id;
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struct tty_struct *tty = tty_port_tty_get(&port->state->port);
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u32 status;
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spin_lock(&port->lock);
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/* Read UART status and clear latched interrupts */
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status = readl(LPC32XX_HSUART_IIR(port->membase));
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if (status & LPC32XX_HSU_BRK_INT) {
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/* Break received */
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writel(LPC32XX_HSU_BRK_INT, LPC32XX_HSUART_IIR(port->membase));
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port->icount.brk++;
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uart_handle_break(port);
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}
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/* Framing error */
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if (status & LPC32XX_HSU_FE_INT)
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writel(LPC32XX_HSU_FE_INT, LPC32XX_HSUART_IIR(port->membase));
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if (status & LPC32XX_HSU_RX_OE_INT) {
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/* Receive FIFO overrun */
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writel(LPC32XX_HSU_RX_OE_INT,
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LPC32XX_HSUART_IIR(port->membase));
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port->icount.overrun++;
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if (tty) {
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tty_insert_flip_char(tty, 0, TTY_OVERRUN);
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tty_schedule_flip(tty);
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}
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}
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/* Data received? */
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if (status & (LPC32XX_HSU_RX_TIMEOUT_INT | LPC32XX_HSU_RX_TRIG_INT)) {
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__serial_lpc32xx_rx(port);
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if (tty)
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tty_flip_buffer_push(tty);
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}
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/* Transmit data request? */
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if ((status & LPC32XX_HSU_TX_INT) && (!uart_tx_stopped(port))) {
|
||||
writel(LPC32XX_HSU_TX_INT, LPC32XX_HSUART_IIR(port->membase));
|
||||
__serial_lpc32xx_tx(port);
|
||||
}
|
||||
|
||||
spin_unlock(&port->lock);
|
||||
tty_kref_put(tty);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
/* port->lock is not held. */
|
||||
static unsigned int serial_lpc32xx_tx_empty(struct uart_port *port)
|
||||
{
|
||||
unsigned int ret = 0;
|
||||
|
||||
if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(port->membase))) == 0)
|
||||
ret = TIOCSER_TEMT;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* port->lock held by caller. */
|
||||
static void serial_lpc32xx_set_mctrl(struct uart_port *port,
|
||||
unsigned int mctrl)
|
||||
{
|
||||
/* No signals are supported on HS UARTs */
|
||||
}
|
||||
|
||||
/* port->lock is held by caller and interrupts are disabled. */
|
||||
static unsigned int serial_lpc32xx_get_mctrl(struct uart_port *port)
|
||||
{
|
||||
/* No signals are supported on HS UARTs */
|
||||
return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
|
||||
}
|
||||
|
||||
/* port->lock held by caller. */
|
||||
static void serial_lpc32xx_stop_tx(struct uart_port *port)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
|
||||
tmp &= ~LPC32XX_HSU_TX_INT_EN;
|
||||
writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
|
||||
}
|
||||
|
||||
/* port->lock held by caller. */
|
||||
static void serial_lpc32xx_start_tx(struct uart_port *port)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
__serial_lpc32xx_tx(port);
|
||||
tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
|
||||
tmp |= LPC32XX_HSU_TX_INT_EN;
|
||||
writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
|
||||
}
|
||||
|
||||
/* port->lock held by caller. */
|
||||
static void serial_lpc32xx_stop_rx(struct uart_port *port)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
|
||||
tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
|
||||
writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
|
||||
|
||||
writel((LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT |
|
||||
LPC32XX_HSU_FE_INT), LPC32XX_HSUART_IIR(port->membase));
|
||||
}
|
||||
|
||||
/* port->lock held by caller. */
|
||||
static void serial_lpc32xx_enable_ms(struct uart_port *port)
|
||||
{
|
||||
/* Modem status is not supported */
|
||||
}
|
||||
|
||||
/* port->lock is not held. */
|
||||
static void serial_lpc32xx_break_ctl(struct uart_port *port,
|
||||
int break_state)
|
||||
{
|
||||
unsigned long flags;
|
||||
u32 tmp;
|
||||
|
||||
spin_lock_irqsave(&port->lock, flags);
|
||||
tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
|
||||
if (break_state != 0)
|
||||
tmp |= LPC32XX_HSU_BREAK;
|
||||
else
|
||||
tmp &= ~LPC32XX_HSU_BREAK;
|
||||
writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
|
||||
spin_unlock_irqrestore(&port->lock, flags);
|
||||
}
|
||||
|
||||
/* LPC3250 Errata HSUART.1: Hang workaround via loopback mode on inactivity */
|
||||
static void lpc32xx_loopback_set(resource_size_t mapbase, int state)
|
||||
{
|
||||
int bit;
|
||||
u32 tmp;
|
||||
|
||||
switch (mapbase) {
|
||||
case LPC32XX_HS_UART1_BASE:
|
||||
bit = 0;
|
||||
break;
|
||||
case LPC32XX_HS_UART2_BASE:
|
||||
bit = 1;
|
||||
break;
|
||||
case LPC32XX_HS_UART7_BASE:
|
||||
bit = 6;
|
||||
break;
|
||||
default:
|
||||
WARN(1, "lpc32xx_hs: Warning: Unknown port at %08x\n", mapbase);
|
||||
return;
|
||||
}
|
||||
|
||||
tmp = readl(LPC32XX_UARTCTL_CLOOP);
|
||||
if (state)
|
||||
tmp |= (1 << bit);
|
||||
else
|
||||
tmp &= ~(1 << bit);
|
||||
writel(tmp, LPC32XX_UARTCTL_CLOOP);
|
||||
}
|
||||
|
||||
/* port->lock is not held. */
|
||||
static int serial_lpc32xx_startup(struct uart_port *port)
|
||||
{
|
||||
int retval;
|
||||
unsigned long flags;
|
||||
u32 tmp;
|
||||
|
||||
spin_lock_irqsave(&port->lock, flags);
|
||||
|
||||
__serial_uart_flush(port);
|
||||
|
||||
writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
|
||||
LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
|
||||
LPC32XX_HSUART_IIR(port->membase));
|
||||
|
||||
writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
|
||||
|
||||
/*
|
||||
* Set receiver timeout, HSU offset of 20, no break, no interrupts,
|
||||
* and default FIFO trigger levels
|
||||
*/
|
||||
tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
|
||||
LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
|
||||
writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
|
||||
|
||||
lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */
|
||||
|
||||
spin_unlock_irqrestore(&port->lock, flags);
|
||||
|
||||
retval = request_irq(port->irq, serial_lpc32xx_interrupt,
|
||||
0, MODNAME, port);
|
||||
if (!retval)
|
||||
writel((tmp | LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN),
|
||||
LPC32XX_HSUART_CTRL(port->membase));
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
/* port->lock is not held. */
|
||||
static void serial_lpc32xx_shutdown(struct uart_port *port)
|
||||
{
|
||||
u32 tmp;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&port->lock, flags);
|
||||
|
||||
tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
|
||||
LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
|
||||
writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
|
||||
|
||||
lpc32xx_loopback_set(port->mapbase, 1); /* go to loopback mode */
|
||||
|
||||
spin_unlock_irqrestore(&port->lock, flags);
|
||||
|
||||
free_irq(port->irq, port);
|
||||
}
|
||||
|
||||
/* port->lock is not held. */
|
||||
static void serial_lpc32xx_set_termios(struct uart_port *port,
|
||||
struct ktermios *termios,
|
||||
struct ktermios *old)
|
||||
{
|
||||
unsigned long flags;
|
||||
unsigned int baud, quot;
|
||||
u32 tmp;
|
||||
|
||||
/* Always 8-bit, no parity, 1 stop bit */
|
||||
termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
|
||||
termios->c_cflag |= CS8;
|
||||
|
||||
termios->c_cflag &= ~(HUPCL | CMSPAR | CLOCAL | CRTSCTS);
|
||||
|
||||
baud = uart_get_baud_rate(port, termios, old, 0,
|
||||
port->uartclk / 14);
|
||||
|
||||
quot = __serial_get_clock_div(port->uartclk, baud);
|
||||
|
||||
spin_lock_irqsave(&port->lock, flags);
|
||||
|
||||
/* Ignore characters? */
|
||||
tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
|
||||
if ((termios->c_cflag & CREAD) == 0)
|
||||
tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
|
||||
else
|
||||
tmp |= LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN;
|
||||
writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
|
||||
|
||||
writel(quot, LPC32XX_HSUART_RATE(port->membase));
|
||||
|
||||
uart_update_timeout(port, termios->c_cflag, baud);
|
||||
|
||||
spin_unlock_irqrestore(&port->lock, flags);
|
||||
|
||||
/* Don't rewrite B0 */
|
||||
if (tty_termios_baud_rate(termios))
|
||||
tty_termios_encode_baud_rate(termios, baud, baud);
|
||||
}
|
||||
|
||||
static const char *serial_lpc32xx_type(struct uart_port *port)
|
||||
{
|
||||
return MODNAME;
|
||||
}
|
||||
|
||||
static void serial_lpc32xx_release_port(struct uart_port *port)
|
||||
{
|
||||
if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
|
||||
if (port->flags & UPF_IOREMAP) {
|
||||
iounmap(port->membase);
|
||||
port->membase = NULL;
|
||||
}
|
||||
|
||||
release_mem_region(port->mapbase, SZ_4K);
|
||||
}
|
||||
}
|
||||
|
||||
static int serial_lpc32xx_request_port(struct uart_port *port)
|
||||
{
|
||||
int ret = -ENODEV;
|
||||
|
||||
if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
|
||||
ret = 0;
|
||||
|
||||
if (!request_mem_region(port->mapbase, SZ_4K, MODNAME))
|
||||
ret = -EBUSY;
|
||||
else if (port->flags & UPF_IOREMAP) {
|
||||
port->membase = ioremap(port->mapbase, SZ_4K);
|
||||
if (!port->membase) {
|
||||
release_mem_region(port->mapbase, SZ_4K);
|
||||
ret = -ENOMEM;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void serial_lpc32xx_config_port(struct uart_port *port, int uflags)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = serial_lpc32xx_request_port(port);
|
||||
if (ret < 0)
|
||||
return;
|
||||
port->type = PORT_UART00;
|
||||
port->fifosize = 64;
|
||||
|
||||
__serial_uart_flush(port);
|
||||
|
||||
writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
|
||||
LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
|
||||
LPC32XX_HSUART_IIR(port->membase));
|
||||
|
||||
writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
|
||||
|
||||
/* Set receiver timeout, HSU offset of 20, no break, no interrupts,
|
||||
and default FIFO trigger levels */
|
||||
writel(LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
|
||||
LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B,
|
||||
LPC32XX_HSUART_CTRL(port->membase));
|
||||
}
|
||||
|
||||
static int serial_lpc32xx_verify_port(struct uart_port *port,
|
||||
struct serial_struct *ser)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
if (ser->type != PORT_UART00)
|
||||
ret = -EINVAL;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct uart_ops serial_lpc32xx_pops = {
|
||||
.tx_empty = serial_lpc32xx_tx_empty,
|
||||
.set_mctrl = serial_lpc32xx_set_mctrl,
|
||||
.get_mctrl = serial_lpc32xx_get_mctrl,
|
||||
.stop_tx = serial_lpc32xx_stop_tx,
|
||||
.start_tx = serial_lpc32xx_start_tx,
|
||||
.stop_rx = serial_lpc32xx_stop_rx,
|
||||
.enable_ms = serial_lpc32xx_enable_ms,
|
||||
.break_ctl = serial_lpc32xx_break_ctl,
|
||||
.startup = serial_lpc32xx_startup,
|
||||
.shutdown = serial_lpc32xx_shutdown,
|
||||
.set_termios = serial_lpc32xx_set_termios,
|
||||
.type = serial_lpc32xx_type,
|
||||
.release_port = serial_lpc32xx_release_port,
|
||||
.request_port = serial_lpc32xx_request_port,
|
||||
.config_port = serial_lpc32xx_config_port,
|
||||
.verify_port = serial_lpc32xx_verify_port,
|
||||
};
|
||||
|
||||
/*
|
||||
* Register a set of serial devices attached to a platform device
|
||||
*/
|
||||
static int __devinit serial_hs_lpc32xx_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct lpc32xx_hsuart_port *p = &lpc32xx_hs_ports[uarts_registered];
|
||||
int ret = 0;
|
||||
struct resource *res;
|
||||
|
||||
if (uarts_registered >= MAX_PORTS) {
|
||||
dev_err(&pdev->dev,
|
||||
"Error: Number of possible ports exceeded (%d)!\n",
|
||||
uarts_registered + 1);
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
memset(p, 0, sizeof(*p));
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res) {
|
||||
dev_err(&pdev->dev,
|
||||
"Error getting mem resource for HS UART port %d\n",
|
||||
uarts_registered);
|
||||
return -ENXIO;
|
||||
}
|
||||
p->port.mapbase = res->start;
|
||||
p->port.membase = NULL;
|
||||
|
||||
p->port.irq = platform_get_irq(pdev, 0);
|
||||
if (p->port.irq < 0) {
|
||||
dev_err(&pdev->dev, "Error getting irq for HS UART port %d\n",
|
||||
uarts_registered);
|
||||
return p->port.irq;
|
||||
}
|
||||
|
||||
p->port.iotype = UPIO_MEM32;
|
||||
p->port.uartclk = LPC32XX_MAIN_OSC_FREQ;
|
||||
p->port.regshift = 2;
|
||||
p->port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | UPF_IOREMAP;
|
||||
p->port.dev = &pdev->dev;
|
||||
p->port.ops = &serial_lpc32xx_pops;
|
||||
p->port.line = uarts_registered++;
|
||||
spin_lock_init(&p->port.lock);
|
||||
|
||||
/* send port to loopback mode by default */
|
||||
lpc32xx_loopback_set(p->port.mapbase, 1);
|
||||
|
||||
ret = uart_add_one_port(&lpc32xx_hs_reg, &p->port);
|
||||
|
||||
platform_set_drvdata(pdev, p);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* Remove serial ports registered against a platform device.
|
||||
*/
|
||||
static int __devexit serial_hs_lpc32xx_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
|
||||
|
||||
uart_remove_one_port(&lpc32xx_hs_reg, &p->port);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int serial_hs_lpc32xx_suspend(struct platform_device *pdev,
|
||||
pm_message_t state)
|
||||
{
|
||||
struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
|
||||
|
||||
uart_suspend_port(&lpc32xx_hs_reg, &p->port);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int serial_hs_lpc32xx_resume(struct platform_device *pdev)
|
||||
{
|
||||
struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
|
||||
|
||||
uart_resume_port(&lpc32xx_hs_reg, &p->port);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
#define serial_hs_lpc32xx_suspend NULL
|
||||
#define serial_hs_lpc32xx_resume NULL
|
||||
#endif
|
||||
|
||||
static const struct of_device_id serial_hs_lpc32xx_dt_ids[] = {
|
||||
{ .compatible = "nxp,lpc3220-hsuart" },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(of, serial_hs_lpc32xx_dt_ids);
|
||||
|
||||
static struct platform_driver serial_hs_lpc32xx_driver = {
|
||||
.probe = serial_hs_lpc32xx_probe,
|
||||
.remove = __devexit_p(serial_hs_lpc32xx_remove),
|
||||
.suspend = serial_hs_lpc32xx_suspend,
|
||||
.resume = serial_hs_lpc32xx_resume,
|
||||
.driver = {
|
||||
.name = MODNAME,
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = serial_hs_lpc32xx_dt_ids,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init lpc32xx_hsuart_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = uart_register_driver(&lpc32xx_hs_reg);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = platform_driver_register(&serial_hs_lpc32xx_driver);
|
||||
if (ret)
|
||||
uart_unregister_driver(&lpc32xx_hs_reg);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void __exit lpc32xx_hsuart_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&serial_hs_lpc32xx_driver);
|
||||
uart_unregister_driver(&lpc32xx_hs_reg);
|
||||
}
|
||||
|
||||
module_init(lpc32xx_hsuart_init);
|
||||
module_exit(lpc32xx_hsuart_exit);
|
||||
|
||||
MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
|
||||
MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
|
||||
MODULE_DESCRIPTION("NXP LPC32XX High Speed UART driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue
Block a user