forked from Minki/linux
scsi: ufs-mediatek: Support performance mode for inline encryption engine
Some MediaTek UFS platforms support high-performance mode that inline encryption engine can be boosted while UFS is not clock-gated. The high-performance mode will be enabled if all below conditions are well-declaired in device tree, - Proper platform-specific compatible string which enables the host capability "UFS_MTK_CAP_BOOST_CRYPT_ENGINE". - "dvfsrc-vcore" node is available in this platform. - Required minimum vcore voltage for high-performance mode. - Clock mux and clock parents of inline encryption engine for both "low-power mode" and "high-performance mode". Link: https://lore.kernel.org/r/20200914050052.3974-2-stanley.chu@mediatek.com Signed-off-by: Stanley Chu <stanley.chu@mediatek.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Stanley Chu
Martin K. Petersen
parent
3d1a99e2b5
commit
590b0d2372
@ -10,6 +10,7 @@
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#include <linux/bitfield.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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@ -44,6 +45,28 @@ static struct ufs_dev_fix ufs_mtk_dev_fixups[] = {
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END_FIX
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};
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static const struct ufs_mtk_host_cfg ufs_mtk_mt8192_cfg = {
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.caps = UFS_MTK_CAP_BOOST_CRYPT_ENGINE,
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};
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static const struct of_device_id ufs_mtk_of_match[] = {
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{
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.compatible = "mediatek,mt8183-ufshci",
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},
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{
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.compatible = "mediatek,mt8192-ufshci",
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.data = &ufs_mtk_mt8192_cfg
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},
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{},
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};
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static bool ufs_mtk_is_boost_crypt_enabled(struct ufs_hba *hba)
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{
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struct ufs_mtk_host *host = ufshcd_get_variant(hba);
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return (host->caps & UFS_MTK_CAP_BOOST_CRYPT_ENGINE);
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}
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static void ufs_mtk_cfg_unipro_cg(struct ufs_hba *hba, bool enable)
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{
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u32 tmp;
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@ -294,6 +317,144 @@ static void ufs_mtk_mphy_power_on(struct ufs_hba *hba, bool on)
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host->mphy_powered_on = on;
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}
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static int ufs_mtk_get_host_clk(struct device *dev, const char *name,
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struct clk **clk_out)
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{
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struct clk *clk;
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int err = 0;
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clk = devm_clk_get(dev, name);
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if (IS_ERR(clk))
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err = PTR_ERR(clk);
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else
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*clk_out = clk;
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return err;
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}
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static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bool boost)
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{
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struct ufs_mtk_host *host = ufshcd_get_variant(hba);
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struct ufs_mtk_crypt_cfg *cfg;
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struct regulator *reg;
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int volt, ret;
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if (!ufs_mtk_is_boost_crypt_enabled(hba))
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return;
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cfg = host->crypt;
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volt = cfg->vcore_volt;
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reg = cfg->reg_vcore;
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ret = clk_prepare_enable(cfg->clk_crypt_mux);
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if (ret) {
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dev_info(hba->dev, "clk_prepare_enable(): %d\n",
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ret);
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return;
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}
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if (boost) {
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ret = regulator_set_voltage(reg, volt, INT_MAX);
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if (ret) {
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dev_info(hba->dev,
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"failed to set vcore to %d\n", volt);
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goto out;
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}
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ret = clk_set_parent(cfg->clk_crypt_mux,
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cfg->clk_crypt_perf);
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if (ret) {
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dev_info(hba->dev,
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"failed to set clk_crypt_perf\n");
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regulator_set_voltage(reg, 0, INT_MAX);
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goto out;
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}
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} else {
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ret = clk_set_parent(cfg->clk_crypt_mux,
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cfg->clk_crypt_lp);
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if (ret) {
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dev_info(hba->dev,
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"failed to set clk_crypt_lp\n");
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goto out;
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}
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ret = regulator_set_voltage(reg, 0, INT_MAX);
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if (ret) {
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dev_info(hba->dev,
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"failed to set vcore to MIN\n");
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}
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}
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out:
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clk_disable_unprepare(cfg->clk_crypt_mux);
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}
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static int ufs_mtk_init_host_clk(struct ufs_hba *hba, const char *name,
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struct clk **clk)
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{
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int ret;
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ret = ufs_mtk_get_host_clk(hba->dev, name, clk);
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if (ret) {
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dev_info(hba->dev, "%s: failed to get %s: %d", __func__,
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name, ret);
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}
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return ret;
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}
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static void ufs_mtk_init_host_caps(struct ufs_hba *hba)
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{
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struct ufs_mtk_host *host = ufshcd_get_variant(hba);
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struct ufs_mtk_crypt_cfg *cfg;
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struct device *dev = hba->dev;
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struct regulator *reg;
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u32 volt;
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host->caps = host->cfg->caps;
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if (!ufs_mtk_is_boost_crypt_enabled(hba))
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return;
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host->crypt = devm_kzalloc(dev, sizeof(*(host->crypt)),
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GFP_KERNEL);
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if (!host->crypt)
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goto disable_caps;
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reg = devm_regulator_get_optional(dev, "dvfsrc-vcore");
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if (IS_ERR(reg)) {
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dev_info(dev, "failed to get dvfsrc-vcore: %ld",
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PTR_ERR(reg));
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goto disable_caps;
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}
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if (of_property_read_u32(dev->of_node, "boost-crypt-vcore-min",
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&volt)) {
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dev_info(dev, "failed to get boost-crypt-vcore-min");
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goto disable_caps;
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}
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cfg = host->crypt;
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if (ufs_mtk_init_host_clk(hba, "crypt_mux",
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&cfg->clk_crypt_mux))
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goto disable_caps;
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if (ufs_mtk_init_host_clk(hba, "crypt_lp",
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&cfg->clk_crypt_lp))
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goto disable_caps;
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if (ufs_mtk_init_host_clk(hba, "crypt_perf",
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&cfg->clk_crypt_perf))
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goto disable_caps;
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cfg->reg_vcore = reg;
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cfg->vcore_volt = volt;
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dev_info(dev, "caps: boost-crypt");
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return;
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disable_caps:
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host->caps &= ~UFS_MTK_CAP_BOOST_CRYPT_ENGINE;
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}
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/**
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* ufs_mtk_setup_clocks - enables/disable clocks
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* @hba: host controller instance
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@ -336,12 +497,14 @@ static int ufs_mtk_setup_clocks(struct ufs_hba *hba, bool on,
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}
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if (clk_pwr_off) {
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ufs_mtk_boost_crypt(hba, on);
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ufs_mtk_setup_ref_clk(hba, on);
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ufs_mtk_mphy_power_on(hba, on);
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}
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} else if (on && status == POST_CHANGE) {
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ufs_mtk_mphy_power_on(hba, on);
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ufs_mtk_setup_ref_clk(hba, on);
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ufs_mtk_boost_crypt(hba, on);
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}
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return ret;
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@ -359,8 +522,9 @@ static int ufs_mtk_setup_clocks(struct ufs_hba *hba, bool on,
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*/
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static int ufs_mtk_init(struct ufs_hba *hba)
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{
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struct ufs_mtk_host *host;
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const struct of_device_id *id;
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struct device *dev = hba->dev;
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struct ufs_mtk_host *host;
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int err = 0;
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host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
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@ -373,6 +537,18 @@ static int ufs_mtk_init(struct ufs_hba *hba)
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host->hba = hba;
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ufshcd_set_variant(hba, host);
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/* Get host capability and platform data */
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id = of_match_device(ufs_mtk_of_match, dev);
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if (!id) {
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err = -EINVAL;
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goto out;
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}
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if (id->data) {
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host->cfg = (struct ufs_mtk_host_cfg *)id->data;
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ufs_mtk_init_host_caps(hba);
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}
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err = ufs_mtk_bind_mphy(hba);
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if (err)
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goto out_variant_clear;
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@ -782,11 +958,6 @@ static int ufs_mtk_remove(struct platform_device *pdev)
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return 0;
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}
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static const struct of_device_id ufs_mtk_of_match[] = {
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{ .compatible = "mediatek,mt8183-ufshci"},
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{},
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};
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static const struct dev_pm_ops ufs_mtk_pm_ops = {
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.suspend = ufshcd_pltfrm_suspend,
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.resume = ufshcd_pltfrm_resume,
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@ -89,9 +89,31 @@ enum {
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TX_CLK_GATE_EN = 3,
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};
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/*
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* Host capability
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*/
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enum ufs_mtk_host_caps {
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UFS_MTK_CAP_BOOST_CRYPT_ENGINE = 1 << 0,
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};
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struct ufs_mtk_crypt_cfg {
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struct regulator *reg_vcore;
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struct clk *clk_crypt_perf;
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struct clk *clk_crypt_mux;
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struct clk *clk_crypt_lp;
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int vcore_volt;
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};
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struct ufs_mtk_host_cfg {
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enum ufs_mtk_host_caps caps;
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};
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struct ufs_mtk_host {
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struct ufs_hba *hba;
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struct phy *mphy;
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struct ufs_mtk_host_cfg *cfg;
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struct ufs_mtk_crypt_cfg *crypt;
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enum ufs_mtk_host_caps caps;
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struct reset_control *hci_reset;
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struct reset_control *unipro_reset;
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struct reset_control *crypto_reset;
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