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powerpc/64s: Fix hash ISA v3.0 TLBIEL instruction generation

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A typo has the R field of the instruction assigned by lucky dip a la
register allocator.

Fixes: d4748276ae ("powerpc/64s: Improve local TLB flush for boot and MCE on POWER9")
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20201126102530.691335-2-npiggin@gmail.com
This commit is contained in:
Nicholas Piggin 2020-11-26 20:25:27 +10:00 committed by Michael Ellerman
parent b6b79dd530
commit 5844cc25fd
1 changed files with 1 additions and 1 deletions
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arch/powerpc/mm/book3s64/hash_native.c
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@ -68,7 +68,7 @@ static __always_inline void tlbiel_hash_set_isa300(unsigned int set, unsigned in
rs = ((unsigned long)pid << PPC_BITLSHIFT(31));
asm volatile(PPC_TLBIEL(%0, %1, %2, %3, %4)
: : "r"(rb), "r"(rs), "i"(ric), "i"(prs), "r"(r)
: : "r"(rb), "r"(rs), "i"(ric), "i"(prs), "i"(r)
: "memory");
}