forked from Minki/linux
media: staging: max96712: Add basic support for MAX96712 GMSL2 deserializer
Add basic support for Maxim MAX96712 quad GMSL2 deserializers. The driver is capable of powering on the device and configuring the MIPI CSI-2 bus in a DPHY 4-lane configuration as well as operating the internal VTG (Video Timing Generator) and VPG (Video Pattern Generator). Using these features the driver is able to act as a 1080p @ 30 fps V4L2 video source. Producing either a checkerboard or gradient pattern on the CSI-2 bus, selectable thru a V4L2 control. While the driver is useful as-is and have been used to prove the correct operation of the MAX96712 itself and "downstream" devices using the MAX96712 as a video source there are a lot of features missing. Most notably the ability to operate the GMSL bus. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
This commit is contained in:
Niklas Söderlund
Mauro Carvalho Chehab
parent
819d679b58
commit
5814f32fef
@ -11523,6 +11523,12 @@ S: Maintained
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F: Documentation/devicetree/bindings/media/i2c/maxim,max9286.yaml
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F: drivers/media/i2c/max9286.c
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MAX96712 QUAD GMSL2 DESERIALIZER DRIVER
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M: Niklas Söderlund <niklas.soderlund@ragnatech.se>
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L: linux-media@vger.kernel.org
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S: Maintained
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F: drivers/staging/media/max96712/max96712.c
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MAX9860 MONO AUDIO VOICE CODEC DRIVER
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M: Peter Rosin <peda@axentia.se>
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L: alsa-devel@alsa-project.org (moderated for non-subscribers)
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@ -26,6 +26,8 @@ source "drivers/staging/media/hantro/Kconfig"
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source "drivers/staging/media/imx/Kconfig"
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source "drivers/staging/media/max96712/Kconfig"
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source "drivers/staging/media/meson/vdec/Kconfig"
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source "drivers/staging/media/omap4iss/Kconfig"
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@ -1,6 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_INTEL_ATOMISP) += atomisp/
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obj-$(CONFIG_VIDEO_IMX_MEDIA) += imx/
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obj-$(CONFIG_VIDEO_MAX96712) += max96712/
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obj-$(CONFIG_VIDEO_MESON_VDEC) += meson/vdec/
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obj-$(CONFIG_VIDEO_OMAP4) += omap4iss/
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obj-$(CONFIG_VIDEO_ROCKCHIP_VDEC) += rkvdec/
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13
drivers/staging/media/max96712/Kconfig
Normal file
13
drivers/staging/media/max96712/Kconfig
Normal file
@ -0,0 +1,13 @@
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# SPDX-License-Identifier: GPL-2.0
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config VIDEO_MAX96712
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tristate "Maxim MAX96712 Quad GMSL2 Deserializer support"
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depends on I2C
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depends on OF_GPIO
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select V4L2_FWNODE
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select VIDEO_V4L2_SUBDEV_API
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select MEDIA_CONTROLLER
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help
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This driver supports the Maxim MAX96712 Quad GMSL2 Deserializer.
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To compile this driver as a module, choose M here: the
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module will be called max96712.
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2
drivers/staging/media/max96712/Makefile
Normal file
2
drivers/staging/media/max96712/Makefile
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@ -0,0 +1,2 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_VIDEO_MAX96712) += max96712.o
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440
drivers/staging/media/max96712/max96712.c
Normal file
440
drivers/staging/media/max96712/max96712.c
Normal file
@ -0,0 +1,440 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Maxim MAX9286 Quad GMSL2 Deserializer Driver
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*
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* Copyright (C) 2021 Renesas Electronics Corporation
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* Copyright (C) 2021 Niklas Söderlund
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*/
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/module.h>
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#include <linux/of_graph.h>
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#include <linux/regmap.h>
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#include <media/v4l2-ctrls.h>
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#include <media/v4l2-fwnode.h>
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#include <media/v4l2-subdev.h>
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#define MAX96712_ID 0x20
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#define MAX96712_DPLL_FREQ 1000
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enum max96712_pattern {
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MAX96712_PATTERN_CHECKERBOARD = 0,
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MAX96712_PATTERN_GRADIENT,
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};
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struct max96712_priv {
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struct i2c_client *client;
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struct regmap *regmap;
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struct gpio_desc *gpiod_pwdn;
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struct v4l2_fwnode_bus_mipi_csi2 mipi;
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struct v4l2_subdev sd;
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struct v4l2_ctrl_handler ctrl_handler;
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struct media_pad pads[1];
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enum max96712_pattern pattern;
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};
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static int max96712_read(struct max96712_priv *priv, int reg)
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{
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int ret, val;
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ret = regmap_read(priv->regmap, reg, &val);
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if (ret) {
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dev_err(&priv->client->dev, "read 0x%04x failed\n", reg);
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return ret;
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}
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return val;
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}
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static int max96712_write(struct max96712_priv *priv, unsigned int reg, u8 val)
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{
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int ret;
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ret = regmap_write(priv->regmap, reg, val);
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if (ret)
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dev_err(&priv->client->dev, "write 0x%04x failed\n", reg);
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return ret;
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}
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static int max96712_update_bits(struct max96712_priv *priv, unsigned int reg,
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u8 mask, u8 val)
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{
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int ret;
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ret = regmap_update_bits(priv->regmap, reg, mask, val);
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if (ret)
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dev_err(&priv->client->dev, "update 0x%04x failed\n", reg);
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return ret;
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}
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static int max96712_write_bulk(struct max96712_priv *priv, unsigned int reg,
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const void *val, size_t val_count)
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{
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int ret;
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ret = regmap_bulk_write(priv->regmap, reg, val, val_count);
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if (ret)
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dev_err(&priv->client->dev, "bulk write 0x%04x failed\n", reg);
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return ret;
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}
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static int max96712_write_bulk_value(struct max96712_priv *priv,
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unsigned int reg, unsigned int val,
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size_t val_count)
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{
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unsigned int i;
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u8 values[4];
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for (i = 1; i <= val_count; i++)
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values[i - 1] = (val >> ((val_count - i) * 8)) & 0xff;
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return max96712_write_bulk(priv, reg, &values, val_count);
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}
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static void max96712_reset(struct max96712_priv *priv)
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{
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max96712_update_bits(priv, 0x13, 0x40, 0x40);
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msleep(20);
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}
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static void max96712_mipi_enable(struct max96712_priv *priv, bool enable)
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{
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if (enable) {
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max96712_update_bits(priv, 0x40b, 0x02, 0x02);
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max96712_update_bits(priv, 0x8a0, 0x80, 0x80);
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} else {
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max96712_update_bits(priv, 0x8a0, 0x80, 0x00);
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max96712_update_bits(priv, 0x40b, 0x02, 0x00);
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}
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}
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static void max96712_mipi_configure(struct max96712_priv *priv)
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{
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unsigned int i;
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u8 phy5 = 0;
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max96712_mipi_enable(priv, false);
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/* Select 2x4 mode. */
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max96712_write(priv, 0x8a0, 0x04);
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/* Configure a 4-lane DPHY using PHY0 and PHY1. */
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/* TODO: Add support for 2-lane and 1-lane configurations. */
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/* TODO: Add support CPHY mode. */
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max96712_write(priv, 0x94a, 0xc0);
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/* Configure lane mapping for PHY0 and PHY1. */
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/* TODO: Add support for lane swapping. */
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max96712_write(priv, 0x8a3, 0xe4);
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/* Configure lane polarity for PHY0 and PHY1. */
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for (i = 0; i < priv->mipi.num_data_lanes + 1; i++)
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if (priv->mipi.lane_polarities[i])
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phy5 |= BIT(i == 0 ? 5 : i < 3 ? i - 1 : i);
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max96712_write(priv, 0x8a5, phy5);
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/* Set link frequency for PHY0 and PHY1. */
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max96712_update_bits(priv, 0x415, 0x3f,
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((MAX96712_DPLL_FREQ / 100) & 0x1f) | BIT(5));
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max96712_update_bits(priv, 0x418, 0x3f,
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((MAX96712_DPLL_FREQ / 100) & 0x1f) | BIT(5));
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/* Enable PHY0 and PHY1 */
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max96712_update_bits(priv, 0x8a2, 0xf0, 0x30);
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}
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static void max96712_pattern_enable(struct max96712_priv *priv, bool enable)
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{
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const u32 h_active = 1920;
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const u32 h_fp = 88;
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const u32 h_sw = 44;
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const u32 h_bp = 148;
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const u32 h_tot = h_active + h_fp + h_sw + h_bp;
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const u32 v_active = 1080;
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const u32 v_fp = 4;
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const u32 v_sw = 5;
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const u32 v_bp = 36;
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const u32 v_tot = v_active + v_fp + v_sw + v_bp;
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if (!enable) {
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max96712_write(priv, 0x1051, 0x00);
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return;
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}
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/* PCLK 75MHz. */
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max96712_write(priv, 0x0009, 0x01);
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/* Configure Video Timing Generator for 1920x1080 @ 30 fps. */
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max96712_write_bulk_value(priv, 0x1052, 0, 3);
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max96712_write_bulk_value(priv, 0x1055, v_sw * h_tot, 3);
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max96712_write_bulk_value(priv, 0x1058,
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(v_active + v_fp + + v_bp) * h_tot, 3);
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max96712_write_bulk_value(priv, 0x105b, 0, 3);
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max96712_write_bulk_value(priv, 0x105e, h_sw, 2);
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max96712_write_bulk_value(priv, 0x1060, h_active + h_fp + h_bp, 2);
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max96712_write_bulk_value(priv, 0x1062, v_tot, 2);
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max96712_write_bulk_value(priv, 0x1064,
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h_tot * (v_sw + v_bp) + (h_sw + h_bp), 3);
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max96712_write_bulk_value(priv, 0x1067, h_active, 2);
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max96712_write_bulk_value(priv, 0x1069, h_fp + h_sw + h_bp, 2);
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max96712_write_bulk_value(priv, 0x106b, v_active, 2);
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/* Generate VS, HS and DE in free-running mode. */
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max96712_write(priv, 0x1050, 0xfb);
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/* Configure Video Pattern Generator. */
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if (priv->pattern == MAX96712_PATTERN_CHECKERBOARD) {
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/* Set checkerboard pattern size. */
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max96712_write(priv, 0x1074, 0x3c);
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max96712_write(priv, 0x1075, 0x3c);
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max96712_write(priv, 0x1076, 0x3c);
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/* Set checkerboard pattern colors. */
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max96712_write_bulk_value(priv, 0x106e, 0xfecc00, 3);
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max96712_write_bulk_value(priv, 0x1071, 0x006aa7, 3);
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/* Generate checkerboard pattern. */
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max96712_write(priv, 0x1051, 0x10);
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} else {
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/* Set gradient increment. */
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max96712_write(priv, 0x106d, 0x10);
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/* Generate gradient pattern. */
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max96712_write(priv, 0x1051, 0x20);
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}
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}
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static int max96712_s_stream(struct v4l2_subdev *sd, int enable)
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{
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struct max96712_priv *priv = v4l2_get_subdevdata(sd);
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if (enable) {
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max96712_pattern_enable(priv, true);
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max96712_mipi_enable(priv, true);
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} else {
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max96712_mipi_enable(priv, false);
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max96712_pattern_enable(priv, false);
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}
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return 0;
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}
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static const struct v4l2_subdev_video_ops max96712_video_ops = {
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.s_stream = max96712_s_stream,
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};
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static int max96712_get_pad_format(struct v4l2_subdev *sd,
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struct v4l2_subdev_state *sd_state,
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struct v4l2_subdev_format *format)
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{
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format->format.width = 1920;
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format->format.height = 1080;
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format->format.code = MEDIA_BUS_FMT_RGB888_1X24;
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format->format.field = V4L2_FIELD_NONE;
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return 0;
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}
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static const struct v4l2_subdev_pad_ops max96712_pad_ops = {
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.get_fmt = max96712_get_pad_format,
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.set_fmt = max96712_get_pad_format,
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};
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static struct v4l2_subdev_ops max96712_subdev_ops = {
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.video = &max96712_video_ops,
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.pad = &max96712_pad_ops,
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};
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static const char * const max96712_test_pattern[] = {
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"Checkerboard",
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"Gradient",
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};
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static int max96712_s_ctrl(struct v4l2_ctrl *ctrl)
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{
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struct max96712_priv *priv =
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container_of(ctrl->handler, struct max96712_priv, ctrl_handler);
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switch (ctrl->id) {
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case V4L2_CID_TEST_PATTERN:
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priv->pattern = ctrl->val ?
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MAX96712_PATTERN_GRADIENT :
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MAX96712_PATTERN_CHECKERBOARD;
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break;
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}
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return 0;
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}
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static const struct v4l2_ctrl_ops max96712_ctrl_ops = {
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.s_ctrl = max96712_s_ctrl,
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};
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static int max96712_v4l2_register(struct max96712_priv *priv)
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{
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long pixel_rate;
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int ret;
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v4l2_i2c_subdev_init(&priv->sd, priv->client, &max96712_subdev_ops);
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priv->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
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priv->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
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v4l2_ctrl_handler_init(&priv->ctrl_handler, 2);
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/*
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* TODO: Once V4L2_CID_LINK_FREQ is changed from a menu control to an
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* INT64 control it should be used here instead of V4L2_CID_PIXEL_RATE.
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*/
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pixel_rate = MAX96712_DPLL_FREQ / priv->mipi.num_data_lanes * 1000000;
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v4l2_ctrl_new_std(&priv->ctrl_handler, NULL, V4L2_CID_PIXEL_RATE,
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pixel_rate, pixel_rate, 1, pixel_rate);
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v4l2_ctrl_new_std_menu_items(&priv->ctrl_handler, &max96712_ctrl_ops,
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V4L2_CID_TEST_PATTERN,
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ARRAY_SIZE(max96712_test_pattern) - 1,
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0, 0, max96712_test_pattern);
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priv->sd.ctrl_handler = &priv->ctrl_handler;
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ret = priv->ctrl_handler.error;
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if (ret)
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goto error;
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priv->pads[0].flags = MEDIA_PAD_FL_SOURCE;
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ret = media_entity_pads_init(&priv->sd.entity, 1, priv->pads);
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if (ret)
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goto error;
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v4l2_set_subdevdata(&priv->sd, priv);
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ret = v4l2_async_register_subdev(&priv->sd);
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if (ret < 0) {
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dev_err(&priv->client->dev, "Unable to register subdevice\n");
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goto error;
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}
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return 0;
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error:
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v4l2_ctrl_handler_free(&priv->ctrl_handler);
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return ret;
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}
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static int max96712_parse_dt(struct max96712_priv *priv)
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{
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struct fwnode_handle *ep;
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struct v4l2_fwnode_endpoint v4l2_ep = {
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.bus_type = V4L2_MBUS_CSI2_DPHY
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};
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int ret;
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ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(&priv->client->dev), 4,
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0, 0);
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if (!ep) {
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dev_err(&priv->client->dev, "Not connected to subdevice\n");
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return -EINVAL;
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}
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ret = v4l2_fwnode_endpoint_parse(ep, &v4l2_ep);
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fwnode_handle_put(ep);
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if (ret) {
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dev_err(&priv->client->dev, "Could not parse v4l2 endpoint\n");
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return -EINVAL;
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}
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if (v4l2_ep.bus.mipi_csi2.num_data_lanes != 4) {
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dev_err(&priv->client->dev, "Only 4 data lanes supported\n");
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return -EINVAL;
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}
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priv->mipi = v4l2_ep.bus.mipi_csi2;
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return 0;
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}
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static const struct regmap_config max96712_i2c_regmap = {
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.reg_bits = 16,
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.val_bits = 8,
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.max_register = 0x1f00,
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};
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static int max96712_probe(struct i2c_client *client)
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{
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struct max96712_priv *priv;
|
||||
int ret;
|
||||
|
||||
priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
priv->client = client;
|
||||
i2c_set_clientdata(client, priv);
|
||||
|
||||
priv->regmap = devm_regmap_init_i2c(client, &max96712_i2c_regmap);
|
||||
if (IS_ERR(priv->regmap))
|
||||
return PTR_ERR(priv->regmap);
|
||||
|
||||
priv->gpiod_pwdn = devm_gpiod_get_optional(&client->dev, "enable",
|
||||
GPIOD_OUT_HIGH);
|
||||
if (IS_ERR(priv->gpiod_pwdn))
|
||||
return PTR_ERR(priv->gpiod_pwdn);
|
||||
|
||||
gpiod_set_consumer_name(priv->gpiod_pwdn, "max96712-pwdn");
|
||||
gpiod_set_value_cansleep(priv->gpiod_pwdn, 1);
|
||||
|
||||
if (priv->gpiod_pwdn)
|
||||
usleep_range(4000, 5000);
|
||||
|
||||
if (max96712_read(priv, 0x4a) != MAX96712_ID)
|
||||
return -ENODEV;
|
||||
|
||||
max96712_reset(priv);
|
||||
|
||||
ret = max96712_parse_dt(priv);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
max96712_mipi_configure(priv);
|
||||
|
||||
return max96712_v4l2_register(priv);
|
||||
}
|
||||
|
||||
static int max96712_remove(struct i2c_client *client)
|
||||
{
|
||||
struct max96712_priv *priv = i2c_get_clientdata(client);
|
||||
|
||||
v4l2_async_unregister_subdev(&priv->sd);
|
||||
|
||||
gpiod_set_value_cansleep(priv->gpiod_pwdn, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id max96712_of_table[] = {
|
||||
{ .compatible = "maxim,max96712" },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, max96712_of_table);
|
||||
|
||||
static struct i2c_driver max96712_i2c_driver = {
|
||||
.driver = {
|
||||
.name = "max96712",
|
||||
.of_match_table = of_match_ptr(max96712_of_table),
|
||||
},
|
||||
.probe_new = max96712_probe,
|
||||
.remove = max96712_remove,
|
||||
};
|
||||
|
||||
module_i2c_driver(max96712_i2c_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Maxim MAX96712 Quad GMSL2 Deserializer Driver");
|
||||
MODULE_AUTHOR("Niklas Söderlund <niklas.soderlund@ragnatech.se>");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue
Block a user