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Merge tag 'gvt-fixes-2022-08-22' of https://github.com/intel/gvt-linux into drm-intel-fixes

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gvt-fixes-2022-08-22

- CometLake regression fix in mmio table rework (Alex)
- misc kernel doc and typo fixes

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
From: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220822031215.GJ1089@zhen-hp.sh.intel.com
This commit is contained in:
Rodrigo Vivi 2022-08-29 10:00:04 -04:00
commit 58091b4958
5 changed files with 8 additions and 7 deletions
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4
drivers/gpu/drm/i915/gvt/aperture_gm.c
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@ -298,7 +298,7 @@ no_enough_resource:
}
/**
* inte_gvt_free_vgpu_resource - free HW resource owned by a vGPU
* intel_vgpu_free_resource() - free HW resource owned by a vGPU
* @vgpu: a vGPU
*
* This function is used to free the HW resource owned by a vGPU.
@ -328,7 +328,7 @@ void intel_vgpu_reset_resource(struct intel_vgpu *vgpu)
}
/**
* intel_alloc_vgpu_resource - allocate HW resource for a vGPU
* intel_vgpu_alloc_resource() - allocate HW resource for a vGPU
* @vgpu: vGPU
* @param: vGPU creation params
*

2
drivers/gpu/drm/i915/gvt/gtt.c
View File

@ -2341,7 +2341,7 @@ static int emulate_ggtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
gvt_vgpu_err("fail to populate guest ggtt entry\n");
/* guest driver may read/write the entry when partial
* update the entry in this situation p2m will fail
* settting the shadow entry to point to a scratch page
* setting the shadow entry to point to a scratch page
*/
ops->set_pfn(&m, gvt->gtt.scratch_mfn);
} else

4
drivers/gpu/drm/i915/gvt/handlers.c
View File

@ -905,7 +905,7 @@ static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu,
else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX)
index = FDI_RX_IMR_TO_PIPE(offset);
else {
gvt_vgpu_err("Unsupport registers %x\n", offset);
gvt_vgpu_err("Unsupported registers %x\n", offset);
return -EINVAL;
}
@ -3052,7 +3052,7 @@ int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
}
/**
* intel_t_default_mmio_write - default MMIO write handler
* intel_vgpu_default_mmio_write() - default MMIO write handler
* @vgpu: a vGPU
* @offset: access offset
* @p_data: write data buffer

2
drivers/gpu/drm/i915/gvt/mmio_context.c
View File

@ -546,7 +546,7 @@ static void switch_mmio(struct intel_vgpu *pre,
}
/**
* intel_gvt_switch_render_mmio - switch mmio context of specific engine
* intel_gvt_switch_mmio - switch mmio context of specific engine
* @pre: the last vGPU that own the engine
* @next: the vGPU to switch to
* @engine: the engine

3
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
View File

@ -1076,7 +1076,8 @@ static int iterate_skl_plus_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(GEN8_HDC_CHICKEN1);
MMIO_D(GEN9_WM_CHICKEN3);
if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
if (IS_KABYLAKE(dev_priv) ||
IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
MMIO_D(GAMT_CHKN_BIT_REG);
if (!IS_BROXTON(dev_priv))
MMIO_D(GEN9_CTX_PREEMPT_REG);