forked from Minki/linux
net: dsa: mv88e6xxx: Link aggregation support
Support offloading of LAGs to hardware. LAGs may be attached to a bridge in which case VLANs, multicast groups, etc. are also offloaded as usual. Signed-off-by: Tobias Waldekranz <tobias@waldekranz.com> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Tobias Waldekranz
Jakub Kicinski
parent
058102a6e9
commit
57e661aae6
@ -1396,15 +1396,32 @@ static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
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static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
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{
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struct dsa_switch_tree *dst = chip->ds->dst;
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struct dsa_switch *ds;
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struct dsa_port *dp;
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u16 pvlan = 0;
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if (!mv88e6xxx_has_pvt(chip))
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return 0;
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/* Skip the local source device, which uses in-chip port VLAN */
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if (dev != chip->ds->index)
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if (dev != chip->ds->index) {
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pvlan = mv88e6xxx_port_vlan(chip, dev, port);
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ds = dsa_switch_find(dst->index, dev);
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dp = ds ? dsa_to_port(ds, port) : NULL;
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if (dp && dp->lag_dev) {
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/* As the PVT is used to limit flooding of
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* FORWARD frames, which use the LAG ID as the
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* source port, we must translate dev/port to
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* the special "LAG device" in the PVT, using
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* the LAG ID as the port number.
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*/
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dev = MV88E6XXX_G2_PVT_ADRR_DEV_TRUNK;
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port = dsa_lag_id(dst, dp->lag_dev);
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}
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}
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return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
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}
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@ -5364,6 +5381,271 @@ static int mv88e6xxx_port_egress_floods(struct dsa_switch *ds, int port,
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return err;
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}
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static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds,
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struct net_device *lag,
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struct netdev_lag_upper_info *info)
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{
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struct dsa_port *dp;
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int id, members = 0;
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id = dsa_lag_id(ds->dst, lag);
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if (id < 0 || id >= ds->num_lag_ids)
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return false;
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dsa_lag_foreach_port(dp, ds->dst, lag)
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/* Includes the port joining the LAG */
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members++;
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if (members > 8)
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return false;
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/* We could potentially relax this to include active
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* backup in the future.
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*/
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if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
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return false;
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/* Ideally we would also validate that the hash type matches
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* the hardware. Alas, this is always set to unknown on team
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* interfaces.
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*/
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return true;
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}
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static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct net_device *lag)
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{
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struct mv88e6xxx_chip *chip = ds->priv;
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struct dsa_port *dp;
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u16 map = 0;
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int id;
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id = dsa_lag_id(ds->dst, lag);
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/* Build the map of all ports to distribute flows destined for
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* this LAG. This can be either a local user port, or a DSA
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* port if the LAG port is on a remote chip.
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*/
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dsa_lag_foreach_port(dp, ds->dst, lag)
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map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index));
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return mv88e6xxx_g2_trunk_mapping_write(chip, id, map);
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}
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static const u8 mv88e6xxx_lag_mask_table[8][8] = {
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/* Row number corresponds to the number of active members in a
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* LAG. Each column states which of the eight hash buckets are
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* mapped to the column:th port in the LAG.
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*
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* Example: In a LAG with three active ports, the second port
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* ([2][1]) would be selected for traffic mapped to buckets
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* 3,4,5 (0x38).
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*/
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{ 0xff, 0, 0, 0, 0, 0, 0, 0 },
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{ 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 },
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{ 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 },
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{ 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 },
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{ 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 },
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{ 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 },
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{ 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 },
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{ 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 },
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};
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static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port,
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int num_tx, int nth)
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{
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u8 active = 0;
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int i;
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num_tx = num_tx <= 8 ? num_tx : 8;
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if (nth < num_tx)
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active = mv88e6xxx_lag_mask_table[num_tx - 1][nth];
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for (i = 0; i < 8; i++) {
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if (BIT(i) & active)
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mask[i] |= BIT(port);
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}
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}
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static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds)
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{
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struct mv88e6xxx_chip *chip = ds->priv;
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unsigned int id, num_tx;
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struct net_device *lag;
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struct dsa_port *dp;
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int i, err, nth;
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u16 mask[8];
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u16 ivec;
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/* Assume no port is a member of any LAG. */
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ivec = BIT(mv88e6xxx_num_ports(chip)) - 1;
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/* Disable all masks for ports that _are_ members of a LAG. */
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list_for_each_entry(dp, &ds->dst->ports, list) {
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if (!dp->lag_dev || dp->ds != ds)
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continue;
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ivec &= ~BIT(dp->index);
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}
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for (i = 0; i < 8; i++)
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mask[i] = ivec;
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/* Enable the correct subset of masks for all LAG ports that
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* are in the Tx set.
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*/
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dsa_lags_foreach_id(id, ds->dst) {
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lag = dsa_lag_dev(ds->dst, id);
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if (!lag)
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continue;
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num_tx = 0;
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dsa_lag_foreach_port(dp, ds->dst, lag) {
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if (dp->lag_tx_enabled)
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num_tx++;
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}
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if (!num_tx)
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continue;
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nth = 0;
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dsa_lag_foreach_port(dp, ds->dst, lag) {
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if (!dp->lag_tx_enabled)
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continue;
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if (dp->ds == ds)
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mv88e6xxx_lag_set_port_mask(mask, dp->index,
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num_tx, nth);
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nth++;
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}
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}
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for (i = 0; i < 8; i++) {
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err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]);
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if (err)
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return err;
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}
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return 0;
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}
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static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds,
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struct net_device *lag)
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{
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int err;
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err = mv88e6xxx_lag_sync_masks(ds);
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if (!err)
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err = mv88e6xxx_lag_sync_map(ds, lag);
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return err;
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}
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static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port)
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{
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struct mv88e6xxx_chip *chip = ds->priv;
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int err;
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mv88e6xxx_reg_lock(chip);
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err = mv88e6xxx_lag_sync_masks(ds);
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mv88e6xxx_reg_unlock(chip);
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return err;
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}
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static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port,
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struct net_device *lag,
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struct netdev_lag_upper_info *info)
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{
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struct mv88e6xxx_chip *chip = ds->priv;
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int err, id;
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if (!mv88e6xxx_lag_can_offload(ds, lag, info))
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return -EOPNOTSUPP;
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id = dsa_lag_id(ds->dst, lag);
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mv88e6xxx_reg_lock(chip);
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err = mv88e6xxx_port_set_trunk(chip, port, true, id);
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if (err)
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goto err_unlock;
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err = mv88e6xxx_lag_sync_masks_map(ds, lag);
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if (err)
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goto err_clear_trunk;
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mv88e6xxx_reg_unlock(chip);
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return 0;
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err_clear_trunk:
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mv88e6xxx_port_set_trunk(chip, port, false, 0);
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err_unlock:
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mv88e6xxx_reg_unlock(chip);
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return err;
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}
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static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port,
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struct net_device *lag)
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{
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struct mv88e6xxx_chip *chip = ds->priv;
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int err_sync, err_trunk;
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mv88e6xxx_reg_lock(chip);
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err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
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err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0);
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mv88e6xxx_reg_unlock(chip);
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return err_sync ? : err_trunk;
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}
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static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index,
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int port)
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{
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struct mv88e6xxx_chip *chip = ds->priv;
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int err;
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mv88e6xxx_reg_lock(chip);
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err = mv88e6xxx_lag_sync_masks(ds);
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mv88e6xxx_reg_unlock(chip);
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return err;
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}
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static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index,
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int port, struct net_device *lag,
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struct netdev_lag_upper_info *info)
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{
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struct mv88e6xxx_chip *chip = ds->priv;
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int err;
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if (!mv88e6xxx_lag_can_offload(ds, lag, info))
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return -EOPNOTSUPP;
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mv88e6xxx_reg_lock(chip);
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err = mv88e6xxx_lag_sync_masks_map(ds, lag);
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if (err)
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goto unlock;
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err = mv88e6xxx_pvt_map(chip, sw_index, port);
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unlock:
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mv88e6xxx_reg_unlock(chip);
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return err;
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}
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static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index,
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int port, struct net_device *lag)
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{
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struct mv88e6xxx_chip *chip = ds->priv;
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int err_sync, err_pvt;
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mv88e6xxx_reg_lock(chip);
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err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
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err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port);
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mv88e6xxx_reg_unlock(chip);
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return err_sync ? : err_pvt;
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}
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static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
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.get_tag_protocol = mv88e6xxx_get_tag_protocol,
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.setup = mv88e6xxx_setup,
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@ -5416,6 +5698,12 @@ static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
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.devlink_param_get = mv88e6xxx_devlink_param_get,
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.devlink_param_set = mv88e6xxx_devlink_param_set,
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.devlink_info_get = mv88e6xxx_devlink_info_get,
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.port_lag_change = mv88e6xxx_port_lag_change,
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.port_lag_join = mv88e6xxx_port_lag_join,
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.port_lag_leave = mv88e6xxx_port_lag_leave,
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.crosschip_lag_change = mv88e6xxx_crosschip_lag_change,
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.crosschip_lag_join = mv88e6xxx_crosschip_lag_join,
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.crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave,
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};
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static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
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@ -5435,6 +5723,12 @@ static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
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ds->ageing_time_min = chip->info->age_time_coeff;
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ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
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/* Some chips support up to 32, but that requires enabling the
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* 5-bit port mode, which we do not support. 640k^W16 ought to
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* be enough for anyone.
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*/
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ds->num_lag_ids = 16;
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dev_set_drvdata(dev, ds);
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return dsa_register_switch(ds);
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@ -126,8 +126,8 @@ int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip, int target,
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/* Offset 0x07: Trunk Mask Table register */
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static int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num,
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bool hash, u16 mask)
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int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num,
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bool hash, u16 mask)
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{
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u16 val = (num << 12) | (mask & mv88e6xxx_port_mask(chip));
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@ -140,8 +140,8 @@ static int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num,
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/* Offset 0x08: Trunk Mapping Table register */
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static int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id,
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u16 map)
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int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id,
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u16 map)
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{
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const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1;
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u16 val = (id << 11) | (map & port_mask);
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@ -101,6 +101,7 @@
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#define MV88E6XXX_G2_PVT_ADDR_OP_WRITE_PVLAN 0x3000
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#define MV88E6XXX_G2_PVT_ADDR_OP_READ 0x4000
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#define MV88E6XXX_G2_PVT_ADDR_PTR_MASK 0x01ff
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#define MV88E6XXX_G2_PVT_ADRR_DEV_TRUNK 0x1f
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/* Offset 0x0C: Cross-chip Port VLAN Data Register */
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#define MV88E6XXX_G2_PVT_DATA 0x0c
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@ -345,6 +346,10 @@ int mv88e6352_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);
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int mv88e6xxx_g2_pot_clear(struct mv88e6xxx_chip *chip);
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int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num,
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bool hash, u16 mask);
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int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id,
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u16 map);
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int mv88e6xxx_g2_trunk_clear(struct mv88e6xxx_chip *chip);
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int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip, int target,
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@ -851,6 +851,27 @@ int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port,
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return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val);
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}
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int mv88e6xxx_port_set_trunk(struct mv88e6xxx_chip *chip, int port,
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bool trunk, u8 id)
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{
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u16 val;
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int err;
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err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val);
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if (err)
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return err;
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val &= ~MV88E6XXX_PORT_CTL1_TRUNK_ID_MASK;
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if (trunk)
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val |= MV88E6XXX_PORT_CTL1_TRUNK_PORT |
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(id << MV88E6XXX_PORT_CTL1_TRUNK_ID_SHIFT);
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else
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val &= ~MV88E6XXX_PORT_CTL1_TRUNK_PORT;
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return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val);
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}
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/* Offset 0x06: Port Based VLAN Map */
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int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map)
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@ -168,6 +168,9 @@
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/* Offset 0x05: Port Control 1 */
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#define MV88E6XXX_PORT_CTL1 0x05
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#define MV88E6XXX_PORT_CTL1_MESSAGE_PORT 0x8000
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#define MV88E6XXX_PORT_CTL1_TRUNK_PORT 0x4000
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#define MV88E6XXX_PORT_CTL1_TRUNK_ID_MASK 0x0f00
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#define MV88E6XXX_PORT_CTL1_TRUNK_ID_SHIFT 8
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#define MV88E6XXX_PORT_CTL1_FID_11_4_MASK 0x00ff
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/* Offset 0x06: Port Based VLAN Map */
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@ -351,6 +354,8 @@ int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
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u16 etype);
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int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port,
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bool message_port);
|
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int mv88e6xxx_port_set_trunk(struct mv88e6xxx_chip *chip, int port,
|
||||
bool trunk, u8 id);
|
||||
int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port,
|
||||
size_t size);
|
||||
int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user