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drm/amdgpu/gfx: Add mmSDMA2-7_EDC_COUNTER to support Arcturus

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Add mmSDMA2-7_EDC_COUNTER to support Arcturus

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Yong Zhao <Yong.Zhao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
James Zhu 2019-12-16 15:49:11 -05:00 committed by Alex Deucher
parent 107ab06136
commit 57cb635bb4
1 changed files with 20 additions and 4 deletions
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24
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
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@ -48,8 +48,15 @@
#include "amdgpu_ras.h" #include "amdgpu_ras.h"
#include "sdma0/sdma0_4_0_offset.h" #include "sdma0/sdma0_4_2_offset.h"
#include "sdma1/sdma1_4_0_offset.h" #include "sdma1/sdma1_4_2_offset.h"
#include "sdma2/sdma2_4_2_2_offset.h"
#include "sdma3/sdma3_4_2_2_offset.h"
#include "sdma4/sdma4_4_2_2_offset.h"
#include "sdma5/sdma5_4_2_2_offset.h"
#include "sdma6/sdma6_4_2_2_offset.h"
#include "sdma7/sdma7_4_2_2_offset.h"
#define GFX9_NUM_GFX_RINGS 1 #define GFX9_NUM_GFX_RINGS 1
#define GFX9_MEC_HPD_SIZE 4096 #define GFX9_MEC_HPD_SIZE 4096
#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
@ -3926,6 +3933,9 @@ static const u32 sgpr_init_compute_shader[] =
0xbe800080, 0xbf810000, 0xbe800080, 0xbf810000,
}; };
/* When below register arrays changed, please update gpr_reg_size,
and sec_ded_counter_reg_size in function gfx_v9_0_do_edc_gpr_workarounds,
to cover all gfx9 ASICs */
static const struct soc15_reg_entry vgpr_init_regs[] = { static const struct soc15_reg_entry vgpr_init_regs[] = {
{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 },
{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 },
@ -4011,9 +4021,15 @@ static const struct soc15_reg_entry sec_ded_counter_registers[] = {
{ SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 1, 16}, { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 1, 16},
{ SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 1, 2}, { SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 1, 2},
{ SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6}, { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6},
{ SOC15_REG_ENTRY(HDP, 0, mmHDP_EDC_CNT), 0, 1, 1},
{ SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 0, 1, 1}, { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 0, 1, 1},
{ SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_EDC_COUNTER), 0, 1, 1}, { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_EDC_COUNTER), 0, 1, 1},
{ SOC15_REG_ENTRY(HDP, 0, mmHDP_EDC_CNT), 0, 1, 1}, { SOC15_REG_ENTRY(SDMA2, 0, mmSDMA2_EDC_COUNTER), 0, 1, 1},
{ SOC15_REG_ENTRY(SDMA3, 0, mmSDMA3_EDC_COUNTER), 0, 1, 1},
{ SOC15_REG_ENTRY(SDMA4, 0, mmSDMA4_EDC_COUNTER), 0, 1, 1},
{ SOC15_REG_ENTRY(SDMA5, 0, mmSDMA5_EDC_COUNTER), 0, 1, 1},
{ SOC15_REG_ENTRY(SDMA6, 0, mmSDMA6_EDC_COUNTER), 0, 1, 1},
{ SOC15_REG_ENTRY(SDMA7, 0, mmSDMA7_EDC_COUNTER), 0, 1, 1},
}; };
static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev) static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev)
@ -4077,7 +4093,7 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
adev->gfx.config.max_sh_per_se; adev->gfx.config.max_sh_per_se;
int sgpr_work_group_size = 5; int sgpr_work_group_size = 5;
int gpr_reg_size = compute_dim_x / 16 + 6; int gpr_reg_size = compute_dim_x / 16 + 6;
int sec_ded_counter_reg_size = ARRAY_SIZE(sec_ded_counter_registers); int sec_ded_counter_reg_size = adev->sdma.num_instances + 34;
/* only support when RAS is enabled */ /* only support when RAS is enabled */
if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))