drm/amd/display: Block 6Ghz timing if SBIOS set HDMI_6G_en to 0
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1853,6 +1853,7 @@ static enum bp_result bios_parser_get_encoder_cap_info(
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info->DP_HBR2_EN = record->usHBR2En;
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info->DP_HBR2_EN = record->usHBR2En;
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info->DP_HBR3_EN = record->usHBR3En;
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info->DP_HBR3_EN = record->usHBR3En;
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info->HDMI_6GB_EN = record->usHDMI6GEn;
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return BP_RESULT_OK;
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return BP_RESULT_OK;
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}
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}
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@ -887,6 +887,9 @@ static bool dce110_link_encoder_validate_hdmi_output(
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crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
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crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
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return false;
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return false;
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if (!enc110->base.features.flags.bits.HDMI_6GB_EN &&
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adjusted_pix_clk_khz >= 300000)
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return false;
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return true;
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return true;
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}
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}
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@ -1008,6 +1011,7 @@ bool dce110_link_encoder_construct(
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bp_cap_info.DP_HBR2_EN;
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bp_cap_info.DP_HBR2_EN;
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enc110->base.features.flags.bits.IS_HBR3_CAPABLE =
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enc110->base.features.flags.bits.IS_HBR3_CAPABLE =
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bp_cap_info.DP_HBR3_EN;
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bp_cap_info.DP_HBR3_EN;
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enc110->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
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}
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}
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return true;
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return true;
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@ -37,6 +37,7 @@ struct encoder_feature_support {
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uint32_t IS_TPS3_CAPABLE:1;
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uint32_t IS_TPS3_CAPABLE:1;
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uint32_t IS_TPS4_CAPABLE:1;
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uint32_t IS_TPS4_CAPABLE:1;
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uint32_t IS_YCBCR_CAPABLE:1;
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uint32_t IS_YCBCR_CAPABLE:1;
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uint32_t HDMI_6GB_EN:1;
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} bits;
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} bits;
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uint32_t raw;
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uint32_t raw;
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} flags;
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} flags;
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