ARM: zynq: Introduce zynq_slcr_unlock()
Call special function for unlocking SLCR. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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@@ -70,6 +70,18 @@ static int zynq_slcr_read(u32 *val, u32 offset)
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return 0;
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return 0;
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}
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}
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/**
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* zynq_slcr_unlock - Unlock SLCR registers
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*
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* Return: a negative value on error, 0 on success
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*/
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static inline int zynq_slcr_unlock(void)
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{
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zynq_slcr_write(SLCR_UNLOCK_MAGIC, SLCR_UNLOCK_OFFSET);
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return 0;
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}
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/**
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/**
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* zynq_slcr_system_reset - Reset the entire system.
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* zynq_slcr_system_reset - Reset the entire system.
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*/
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*/
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@@ -82,7 +94,7 @@ void zynq_slcr_system_reset(void)
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* Note that this seems to require raw i/o
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* Note that this seems to require raw i/o
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* functions or there's a lockup?
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* functions or there's a lockup?
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*/
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*/
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writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK_OFFSET);
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zynq_slcr_unlock();
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/*
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/*
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* Clear 0x0F000000 bits of reboot status register to workaround
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* Clear 0x0F000000 bits of reboot status register to workaround
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@@ -166,7 +178,7 @@ int __init zynq_early_slcr_init(void)
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np->data = (__force void *)zynq_slcr_base;
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np->data = (__force void *)zynq_slcr_base;
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/* unlock the SLCR so that registers can be changed */
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/* unlock the SLCR so that registers can be changed */
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writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK_OFFSET);
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zynq_slcr_unlock();
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pr_info("%s mapped to %p\n", np->name, zynq_slcr_base);
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pr_info("%s mapped to %p\n", np->name, zynq_slcr_base);
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