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dp83640: correct the periodic output frequency

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The phyter driver incorrectly feeds the value of the period into what
is in fact a pulse width register, resulting in the actual period
being twice the dialed value. This patch fixes the issue and renames a
variable to make the code at bit more clear.

Signed-off-by: Richard Cochran <richardcochran@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Richard Cochran 2014-03-20 22:21:57 +01:00 committed by David S. Miller
parent fbf4b9349f
commit 564ca56e45
1 changed files with 6 additions and 5 deletions
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11
drivers/net/phy/dp83640.c
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@ -271,7 +271,7 @@ static void periodic_output(struct dp83640_clock *clock,
{ {
struct dp83640_private *dp83640 = clock->chosen; struct dp83640_private *dp83640 = clock->chosen;
struct phy_device *phydev = dp83640->phydev; struct phy_device *phydev = dp83640->phydev;
u32 sec, nsec, period; u32 sec, nsec, pwidth;
u16 gpio, ptp_trig, trigger, val; u16 gpio, ptp_trig, trigger, val;
gpio = on ? gpio_tab[PEROUT_GPIO] : 0; gpio = on ? gpio_tab[PEROUT_GPIO] : 0;
@ -296,8 +296,9 @@ static void periodic_output(struct dp83640_clock *clock,
sec = clkreq->perout.start.sec; sec = clkreq->perout.start.sec;
nsec = clkreq->perout.start.nsec; nsec = clkreq->perout.start.nsec;
period = clkreq->perout.period.sec * 1000000000UL; pwidth = clkreq->perout.period.sec * 1000000000UL;
period += clkreq->perout.period.nsec; pwidth += clkreq->perout.period.nsec;
pwidth /= 2;
mutex_lock(&clock->extreg_lock); mutex_lock(&clock->extreg_lock);
@ -310,8 +311,8 @@ static void periodic_output(struct dp83640_clock *clock,
ext_write(0, phydev, PAGE4, PTP_TDR, nsec >> 16); /* ns[31:16] */ ext_write(0, phydev, PAGE4, PTP_TDR, nsec >> 16); /* ns[31:16] */
ext_write(0, phydev, PAGE4, PTP_TDR, sec & 0xffff); /* sec[15:0] */ ext_write(0, phydev, PAGE4, PTP_TDR, sec & 0xffff); /* sec[15:0] */
ext_write(0, phydev, PAGE4, PTP_TDR, sec >> 16); /* sec[31:16] */ ext_write(0, phydev, PAGE4, PTP_TDR, sec >> 16); /* sec[31:16] */
ext_write(0, phydev, PAGE4, PTP_TDR, period & 0xffff); /* ns[15:0] */ ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff); /* ns[15:0] */
ext_write(0, phydev, PAGE4, PTP_TDR, period >> 16); /* ns[31:16] */ ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16); /* ns[31:16] */
/*enable trigger*/ /*enable trigger*/
val &= ~TRIG_LOAD; val &= ~TRIG_LOAD;