forked from Minki/linux
MIPS: Outline udelay and fix a few issues.
Outlining fixes the issue were on certain CPUs such as the R10000 family the delay loop would need an extra cycle if it overlaps a cacheline boundary. The rewrite also fixes build errors with GCC 4.4 which was changed in way incompatible with the kernel's inline assembly. Relying on pure C for computation of the delay value removes the need for explicit. The price we pay is a slight slowdown of the computation - to be fixed on another day. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
parent
3a553147ea
commit
5636919b5c
@ -39,8 +39,8 @@ struct cache_desc {
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#define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */
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struct cpuinfo_mips {
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unsigned long udelay_val;
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unsigned long asid_cache;
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unsigned int udelay_val;
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unsigned int asid_cache;
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/*
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* Capability and feature descriptor structure for MIPS CPU
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@ -11,94 +11,12 @@
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#ifndef _ASM_DELAY_H
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#define _ASM_DELAY_H
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#include <linux/param.h>
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#include <linux/smp.h>
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extern void __delay(unsigned int loops);
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extern void __ndelay(unsigned int ns);
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extern void __udelay(unsigned int us);
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#include <asm/compiler.h>
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#include <asm/war.h>
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static inline void __delay(unsigned long loops)
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{
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if (sizeof(long) == 4)
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__asm__ __volatile__ (
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" .set noreorder \n"
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" .align 3 \n"
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"1: bnez %0, 1b \n"
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" subu %0, 1 \n"
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" .set reorder \n"
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: "=r" (loops)
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: "0" (loops));
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else if (sizeof(long) == 8 && !DADDI_WAR)
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__asm__ __volatile__ (
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" .set noreorder \n"
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" .align 3 \n"
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"1: bnez %0, 1b \n"
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" dsubu %0, 1 \n"
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" .set reorder \n"
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: "=r" (loops)
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: "0" (loops));
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else if (sizeof(long) == 8 && DADDI_WAR)
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__asm__ __volatile__ (
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" .set noreorder \n"
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" .align 3 \n"
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"1: bnez %0, 1b \n"
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" dsubu %0, %2 \n"
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" .set reorder \n"
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: "=r" (loops)
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: "0" (loops), "r" (1));
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}
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/*
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* Division by multiplication: you don't have to worry about
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* loss of precision.
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*
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* Use only for very small delays ( < 1 msec). Should probably use a
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* lookup table, really, as the multiplications take much too long with
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* short delays. This is a "reasonable" implementation, though (and the
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* first constant multiplications gets optimized away if the delay is
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* a constant)
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*/
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static inline void __udelay(unsigned long usecs, unsigned long lpj)
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{
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unsigned long hi, lo;
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/*
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* The rates of 128 is rounded wrongly by the catchall case
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* for 64-bit. Excessive precission? Probably ...
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*/
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#if defined(CONFIG_64BIT) && (HZ == 128)
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usecs *= 0x0008637bd05af6c7UL; /* 2**64 / (1000000 / HZ) */
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#elif defined(CONFIG_64BIT)
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usecs *= (0x8000000000000000UL / (500000 / HZ));
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#else /* 32-bit junk follows here */
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usecs *= (unsigned long) (((0x8000000000000000ULL / (500000 / HZ)) +
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0x80000000ULL) >> 32);
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#endif
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if (sizeof(long) == 4)
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__asm__("multu\t%2, %3"
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: "=h" (usecs), "=l" (lo)
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: "r" (usecs), "r" (lpj)
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: GCC_REG_ACCUM);
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else if (sizeof(long) == 8 && !R4000_WAR)
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__asm__("dmultu\t%2, %3"
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: "=h" (usecs), "=l" (lo)
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: "r" (usecs), "r" (lpj)
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: GCC_REG_ACCUM);
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else if (sizeof(long) == 8 && R4000_WAR)
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__asm__("dmultu\t%3, %4\n\tmfhi\t%0"
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: "=r" (usecs), "=h" (hi), "=l" (lo)
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: "r" (usecs), "r" (lpj)
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: GCC_REG_ACCUM);
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__delay(usecs);
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}
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#define __udelay_val cpu_data[raw_smp_processor_id()].udelay_val
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#define udelay(usecs) __udelay((usecs), __udelay_val)
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#define ndelay(ns) __udelay(ns)
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#define udelay(us) __udelay(us)
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/* make sure "usecs *= ..." in udelay do not overflow. */
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#if HZ >= 1000
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@ -42,7 +42,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
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seq_printf(m, fmt, __cpu_name[n],
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(version >> 4) & 0x0f, version & 0x0f,
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(fp_vers >> 4) & 0x0f, fp_vers & 0x0f);
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seq_printf(m, "BogoMIPS\t\t: %lu.%02lu\n",
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seq_printf(m, "BogoMIPS\t\t: %u.%02u\n",
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cpu_data[n].udelay_val / (500000/HZ),
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(cpu_data[n].udelay_val / (5000/HZ)) % 100);
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seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no");
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@ -2,8 +2,8 @@
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# Makefile for MIPS-specific library files..
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#
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lib-y += csum_partial.o memcpy.o memcpy-inatomic.o memset.o strlen_user.o \
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strncpy_user.o strnlen_user.o uncached.o
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lib-y += csum_partial.o delay.o memcpy.o memcpy-inatomic.o memset.o \
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strlen_user.o strncpy_user.o strnlen_user.o uncached.o
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obj-y += iomap.o
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obj-$(CONFIG_PCI) += iomap-pci.o
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56
arch/mips/lib/delay.c
Normal file
56
arch/mips/lib/delay.c
Normal file
@ -0,0 +1,56 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994 by Waldorf Electronics
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* Copyright (C) 1995 - 2000, 01, 03 by Ralf Baechle
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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* Copyright (C) 2007 Maciej W. Rozycki
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*/
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#include <linux/module.h>
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#include <linux/param.h>
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#include <linux/smp.h>
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#include <asm/compiler.h>
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#include <asm/war.h>
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inline void __delay(unsigned int loops)
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{
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__asm__ __volatile__ (
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" .set noreorder \n"
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" .align 3 \n"
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"1: bnez %0, 1b \n"
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" subu %0, 1 \n"
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" .set reorder \n"
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: "=r" (loops)
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: "0" (loops));
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}
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EXPORT_SYMBOL(__delay);
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/*
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* Division by multiplication: you don't have to worry about
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* loss of precision.
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*
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* Use only for very small delays ( < 1 msec). Should probably use a
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* lookup table, really, as the multiplications take much too long with
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* short delays. This is a "reasonable" implementation, though (and the
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* first constant multiplications gets optimized away if the delay is
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* a constant)
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*/
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void __udelay(unsigned long us)
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{
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unsigned int lpj = current_cpu_data.udelay_val;
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__delay((us * 0x000010c7 * HZ * lpj) >> 32);
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}
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EXPORT_SYMBOL(__udelay);
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void __ndelay(unsigned long ns)
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{
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unsigned int lpj = current_cpu_data.udelay_val;
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__delay((us * 0x00000005 * HZ * lpj) >> 32);
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}
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EXPORT_SYMBOL(__ndelay);
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