drm/i915: Disable tesselation clock gating on tgl A0
Disable TEDOP clock gating flow by programming 0x20A0[19] = 1 References: HSDES#1407928979 Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20200207155138.30978-1-mika.kuoppala@linux.intel.com
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@ -1352,6 +1352,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
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wa_write_or(wal,
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GEN7_SARCHKMD,
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GEN7_DISABLE_SAMPLER_PREFETCH);
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/* Wa_1407928979:tgl */
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wa_write_or(wal,
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GEN7_FF_THREAD_MODE,
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GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
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}
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if (IS_GEN(i915, 11)) {
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@ -3165,6 +3165,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
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#define GEN7_FF_THREAD_MODE _MMIO(0x20a0)
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#define GEN7_FF_SCHED_MASK 0x0077070
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#define GEN8_FF_DS_REF_CNT_FFME (1 << 19)
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#define GEN12_FF_TESSELATION_DOP_GATE_DISABLE BIT(19)
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#define GEN7_FF_TS_SCHED_HS1 (0x5 << 16)
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#define GEN7_FF_TS_SCHED_HS0 (0x3 << 16)
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#define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16)
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