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ARM: OMAP5: Redo THUMB mode switch on secondary CPU

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Here's a redo of the patch [1] that effectively does the same
thing but is the right way to do things by using ENDPROC instead.
The firmware correctly switches to THUMB before entry.

The patch applies ontop of the earlier patch [1].

[1] https://lkml.org/lkml/2014/4/22/1044

Suggested-by: Dave Martin <Dave.Martin@arm.com>
Cc: Dave Martin <Dave.Martin@arm.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Nishanth Menon <nm@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Joel Fernandes <joelf@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Joel Fernandes 2014-04-29 21:53:47 -05:00 committed by Tony Lindgren
parent 4c05160342
commit 55fde31cae
1 changed files with 1 additions and 5 deletions
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6
arch/arm/mach-omap2/omap-headsmp.S
View File

@ -31,10 +31,6 @@
* register AuxCoreBoot0. * register AuxCoreBoot0.
*/ */
ENTRY(omap5_secondary_startup) ENTRY(omap5_secondary_startup)
.arm
THUMB( adr r9, BSYM(wait) ) @ CPU may be entered in ARM mode.
THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
THUMB( .thumb ) @ switch to Thumb now.
wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0 wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
ldr r0, [r2] ldr r0, [r2]
mov r0, r0, lsr #5 mov r0, r0, lsr #5
@ -43,7 +39,7 @@ wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
cmp r0, r4 cmp r0, r4
bne wait bne wait
b secondary_startup b secondary_startup
END(omap5_secondary_startup) ENDPROC(omap5_secondary_startup)
/* /*
* OMAP4 specific entry point for secondary CPU to jump from ROM * OMAP4 specific entry point for secondary CPU to jump from ROM
* code. This routine also provides a holding flag into which * code. This routine also provides a holding flag into which