forked from Minki/linux
Merge tag 'arm-soc/for-4.6/devicetree-arm64' of http://github.com/Broadcom/stblinux into next/dt64
Merge "Broadcom devicetree-arm64 changes for 4.6" from Florian Fainelli: This pull request contains Broadcom ARM64-based SoCs device tree changes: - Anup adds additional nodes to the Broadcom Northstart 2 Device Trees: SDHCI (iProc-compatible), ARM SP804 timers, ARM SP805 watchdog - Anup also adds a binding documentation for the ARM SP805 watchdog since there was not one in tree before - Ray adds PCIE root complex nodes to the Northstar 2 Device Tree nodes, using the iProc-compatible binding - Jayachandran C. adds binding documentation for the Broadcom Vulcan processors and reference platforms * tag 'arm-soc/for-4.6/devicetree-arm64' of http://github.com/Broadcom/stblinux: dt-bindings: Add documentation for Broadcom Vulcan arm64: dts: Add PCIe0 and PCIe4 DT nodes for NS2 arm64: dts: Add ARM SP805 watchdog DT node for NS2 dt-bindings: watchdog: Add ARM SP805 DT bindings arm64: dts: Add ARM SP804 timer DT nodes for NS2 arm64: dts: Add SDHCI DT node for NS2
This commit is contained in:
Arnd Bergmann
commit
55da9c0852
@ -0,0 +1,10 @@
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Broadcom Vulcan device tree bindings
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------------------------------------
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Boards with Broadcom Vulcan shall have the following root property:
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Broadcom Vulcan Evaluation Board:
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compatible = "brcm,vulcan-eval", "brcm,vulcan-soc";
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Generic Vulcan board:
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compatible = "brcm,vulcan-soc";
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@ -167,6 +167,7 @@ nodes to be present and contain the properties described below.
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"arm,cortex-r5"
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"arm,cortex-r7"
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"brcm,brahma-b15"
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"brcm,vulcan"
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"cavium,thunder"
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"faraday,fa526"
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"intel,sa110"
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17
Documentation/devicetree/bindings/watchdog/arm,sp805.txt
Normal file
17
Documentation/devicetree/bindings/watchdog/arm,sp805.txt
Normal file
@ -0,0 +1,17 @@
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ARM AMBA Primecell SP805 Watchdog
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Required properties:
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- compatible: Should be "arm,sp805" & "arm,primecell"
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- reg: Should contain location and length for watchdog timer register.
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- interrupts: Should contain the list of watchdog timer interrupts.
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- clocks: clocks driving the watchdog timer hardware. This list should be 2
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clocks. With 2 clocks, the order is wdogclk clock, apb_pclk.
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Example:
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watchdog@66090000 {
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compatible = "arm,sp805", "arm,primecell";
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reg = <0x66090000 0x1000>;
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interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apb_pclk>,<&apb_pclk>;
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clock-names = "wdogclk", "apb_pclk";
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};
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@ -52,6 +52,14 @@
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};
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};
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&pcie0 {
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status = "ok";
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};
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&pcie4 {
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status = "ok";
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};
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&i2c0 {
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status = "ok";
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};
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@ -64,6 +72,10 @@
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status = "ok";
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};
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&sdio0 {
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status = "ok";
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};
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&nand {
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nandcs@0 {
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compatible = "brcm,nandcs";
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@ -137,6 +137,80 @@
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};
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};
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pcie0: pcie@20020000 {
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compatible = "brcm,iproc-pcie";
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reg = <0 0x20020000 0 0x1000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 281 IRQ_TYPE_NONE>;
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linux,pci-domain = <0>;
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bus-range = <0x00 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>;
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brcm,pcie-ob;
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brcm,pcie-ob-oarr-size;
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brcm,pcie-ob-axi-offset = <0x00000000>;
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brcm,pcie-ob-window-size = <256>;
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status = "disabled";
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msi-parent = <&msi0>;
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msi0: msi@20020000 {
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compatible = "brcm,iproc-msi";
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msi-controller;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 277 IRQ_TYPE_NONE>,
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<GIC_SPI 278 IRQ_TYPE_NONE>,
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<GIC_SPI 279 IRQ_TYPE_NONE>,
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<GIC_SPI 280 IRQ_TYPE_NONE>;
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brcm,num-eq-region = <1>;
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brcm,num-msi-msg-region = <1>;
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};
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};
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pcie4: pcie@50020000 {
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compatible = "brcm,iproc-pcie";
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reg = <0 0x50020000 0 0x1000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 305 IRQ_TYPE_NONE>;
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linux,pci-domain = <4>;
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bus-range = <0x00 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>;
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brcm,pcie-ob;
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brcm,pcie-ob-oarr-size;
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brcm,pcie-ob-axi-offset = <0x30000000>;
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brcm,pcie-ob-window-size = <256>;
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status = "disabled";
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msi-parent = <&msi4>;
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msi4: msi@50020000 {
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compatible = "brcm,iproc-msi";
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msi-controller;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 301 IRQ_TYPE_NONE>,
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<GIC_SPI 302 IRQ_TYPE_NONE>,
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<GIC_SPI 303 IRQ_TYPE_NONE>,
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<GIC_SPI 304 IRQ_TYPE_NONE>;
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};
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};
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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@ -256,6 +330,46 @@
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<0x65260000 0x1000>;
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};
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timer0: timer@66030000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x66030000 0x1000>;
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interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&iprocslow>,
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<&iprocslow>,
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<&iprocslow>;
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clock-names = "timer1", "timer2", "apb_pclk";
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};
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timer1: timer@66040000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x66040000 0x1000>;
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interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&iprocslow>,
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<&iprocslow>,
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<&iprocslow>;
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clock-names = "timer1", "timer2", "apb_pclk";
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};
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timer2: timer@66050000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x66050000 0x1000>;
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interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&iprocslow>,
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<&iprocslow>,
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<&iprocslow>;
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clock-names = "timer1", "timer2", "apb_pclk";
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};
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timer3: timer@66060000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x66060000 0x1000>;
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interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&iprocslow>,
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<&iprocslow>,
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<&iprocslow>;
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clock-names = "timer1", "timer2", "apb_pclk";
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};
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i2c0: i2c@66080000 {
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compatible = "brcm,iproc-i2c";
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reg = <0x66080000 0x100>;
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@ -266,6 +380,14 @@
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status = "disabled";
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};
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wdt0: watchdog@66090000 {
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compatible = "arm,sp805", "arm,primecell";
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reg = <0x66090000 0x1000>;
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interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&iprocslow>, <&iprocslow>;
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clock-names = "wdogclk", "apb_pclk";
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};
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i2c1: i2c@660b0000 {
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compatible = "brcm,iproc-i2c";
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reg = <0x660b0000 0x100>;
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@ -291,6 +413,24 @@
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reg = <0x66220000 0x28>;
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};
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sdio0: sdhci@66420000 {
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compatible = "brcm,sdhci-iproc-cygnus";
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reg = <0x66420000 0x100>;
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interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
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bus-width = <8>;
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clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
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status = "disabled";
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};
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sdio1: sdhci@66430000 {
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compatible = "brcm,sdhci-iproc-cygnus";
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reg = <0x66430000 0x100>;
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interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
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bus-width = <8>;
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clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
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status = "disabled";
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};
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nand: nand@66460000 {
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compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
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reg = <0x66460000 0x600>,
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