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Merge branch 'ib-mtk' into devel

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This commit is contained in:
Linus Walleij 2018-09-18 14:55:54 -07:00
commit 55818b9023
12 changed files with 6831 additions and 1188 deletions
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41
drivers/pinctrl/mediatek/Kconfig
View File

@ -3,7 +3,7 @@ menu "MediaTek pinctrl drivers"
config EINT_MTK
bool "MediaTek External Interrupt Support"
depends on PINCTRL_MTK || PINCTRL_MT7622 || COMPILE_TEST
depends on PINCTRL_MTK || PINCTRL_MTK_MOORE || COMPILE_TEST
select IRQ_DOMAIN
config PINCTRL_MTK
@ -15,6 +15,24 @@ config PINCTRL_MTK
select EINT_MTK
select OF_GPIO
config PINCTRL_MTK_MOORE
bool "MediaTek Moore Core that implements generic binding"
depends on OF
select GENERIC_PINCONF
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select GPIOLIB
select OF_GPIO
config PINCTRL_MTK_PARIS
bool "MediaTek Paris Core that implements vendor binding"
depends on OF
select PINMUX
select GENERIC_PINCONF
select GPIOLIB
select EINT_MTK
select OF_GPIO
# For ARMv7 SoCs
config PINCTRL_MT2701
bool "Mediatek MT2701 pin control"
@ -23,6 +41,12 @@ config PINCTRL_MT2701
default MACH_MT2701
select PINCTRL_MTK
config PINCTRL_MT7623
bool "Mediatek MT7623 pin control with generic binding"
depends on MACH_MT7623 || COMPILE_TEST
depends on PINCTRL_MTK_MOORE
default y
config PINCTRL_MT8135
bool "Mediatek MT8135 pin control"
depends on MACH_MT8135 || COMPILE_TEST
@ -47,13 +71,9 @@ config PINCTRL_MT2712
config PINCTRL_MT7622
bool "MediaTek MT7622 pin control"
depends on OF
depends on ARM64 || COMPILE_TEST
select GENERIC_PINCONF
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select GPIOLIB
select OF_GPIO
depends on PINCTRL_MTK_MOORE
default y
config PINCTRL_MT8173
bool "Mediatek MT8173 pin control"
@ -62,6 +82,13 @@ config PINCTRL_MT8173
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK
config PINCTRL_MT8183
bool "Mediatek MT8183 pin control"
depends on OF
depends on ARM64 || COMPILE_TEST
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_PARIS
# For PMIC
config PINCTRL_MT6397
bool "Mediatek MT6397 pin control"

4
drivers/pinctrl/mediatek/Makefile
View File

@ -2,6 +2,8 @@
# Core
obj-$(CONFIG_EINT_MTK) += mtk-eint.o
obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o
obj-$(CONFIG_PINCTRL_MTK_MOORE) += pinctrl-moore.o pinctrl-mtk-common-v2.o
obj-$(CONFIG_PINCTRL_MTK_PARIS) += pinctrl-paris.o pinctrl-mtk-common-v2.o
# SoC Drivers
obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o
@ -9,5 +11,7 @@ obj-$(CONFIG_PINCTRL_MT2712) += pinctrl-mt2712.o
obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o
obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o
obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o

689
drivers/pinctrl/mediatek/pinctrl-moore.c Normal file
View File

@ -0,0 +1,689 @@
// SPDX-License-Identifier: GPL-2.0
/*
* MediaTek Pinctrl Moore Driver, which implement the generic dt-binding
* pinctrl-bindings.txt for MediaTek SoC.
*
* Copyright (C) 2017-2018 MediaTek Inc.
* Author: Sean Wang <sean.wang@mediatek.com>
*
*/
#include "pinctrl-moore.h"
#define PINCTRL_PINCTRL_DEV KBUILD_MODNAME
/* Custom pinconf parameters */
#define MTK_PIN_CONFIG_TDSEL (PIN_CONFIG_END + 1)
#define MTK_PIN_CONFIG_RDSEL (PIN_CONFIG_END + 2)
#define MTK_PIN_CONFIG_PU_ADV (PIN_CONFIG_END + 3)
#define MTK_PIN_CONFIG_PD_ADV (PIN_CONFIG_END + 4)
static const struct pinconf_generic_params mtk_custom_bindings[] = {
{"mediatek,tdsel", MTK_PIN_CONFIG_TDSEL, 0},
{"mediatek,rdsel", MTK_PIN_CONFIG_RDSEL, 0},
{"mediatek,pull-up-adv", MTK_PIN_CONFIG_PU_ADV, 1},
{"mediatek,pull-down-adv", MTK_PIN_CONFIG_PD_ADV, 1},
};
#ifdef CONFIG_DEBUG_FS
static const struct pin_config_item mtk_conf_items[] = {
PCONFDUMP(MTK_PIN_CONFIG_TDSEL, "tdsel", NULL, true),
PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true),
PCONFDUMP(MTK_PIN_CONFIG_PU_ADV, "pu-adv", NULL, true),
PCONFDUMP(MTK_PIN_CONFIG_PD_ADV, "pd-adv", NULL, true),
};
#endif
static int mtk_pinmux_set_mux(struct pinctrl_dev *pctldev,
unsigned int selector, unsigned int group)
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
struct function_desc *func;
struct group_desc *grp;
int i;
func = pinmux_generic_get_function(pctldev, selector);
if (!func)
return -EINVAL;
grp = pinctrl_generic_get_group(pctldev, group);
if (!grp)
return -EINVAL;
dev_dbg(pctldev->dev, "enable function %s group %s\n",
func->name, grp->name);
for (i = 0; i < grp->num_pins; i++) {
const struct mtk_pin_desc *desc;
int *pin_modes = grp->data;
int pin = grp->pins[i];
desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
pin_modes[i]);
}
return 0;
}
static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int pin)
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
const struct mtk_pin_desc *desc;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
hw->soc->gpio_m);
}
static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int pin, bool input)
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
const struct mtk_pin_desc *desc;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
/* hardware would take 0 as input direction */
return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !input);
}
static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
unsigned int pin, unsigned long *config)
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
u32 param = pinconf_to_config_param(*config);
int val, val2, err, reg, ret = 1;
const struct mtk_pin_desc *desc;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
if (hw->soc->bias_disable_get) {
err = hw->soc->bias_disable_get(hw, desc, &ret);
if (err)
return err;
} else {
return -ENOTSUPP;
}
break;
case PIN_CONFIG_BIAS_PULL_UP:
if (hw->soc->bias_get) {
err = hw->soc->bias_get(hw, desc, 1, &ret);
if (err)
return err;
} else {
return -ENOTSUPP;
}
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
if (hw->soc->bias_get) {
err = hw->soc->bias_get(hw, desc, 0, &ret);
if (err)
return err;
} else {
return -ENOTSUPP;
}
break;
case PIN_CONFIG_SLEW_RATE:
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SR, &val);
if (err)
return err;
if (!val)
return -EINVAL;
break;
case PIN_CONFIG_INPUT_ENABLE:
case PIN_CONFIG_OUTPUT_ENABLE:
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &val);
if (err)
return err;
/* HW takes input mode as zero; output mode as non-zero */
if ((val && param == PIN_CONFIG_INPUT_ENABLE) ||
(!val && param == PIN_CONFIG_OUTPUT_ENABLE))
return -EINVAL;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &val);
if (err)
return err;
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SMT, &val2);
if (err)
return err;
if (val || !val2)
return -EINVAL;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
if (hw->soc->drive_get) {
err = hw->soc->drive_get(hw, desc, &ret);
if (err)
return err;
} else {
err = -ENOTSUPP;
}
break;
case MTK_PIN_CONFIG_TDSEL:
case MTK_PIN_CONFIG_RDSEL:
reg = (param == MTK_PIN_CONFIG_TDSEL) ?
PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
err = mtk_hw_get_value(hw, desc, reg, &val);
if (err)
return err;
ret = val;
break;
case MTK_PIN_CONFIG_PU_ADV:
case MTK_PIN_CONFIG_PD_ADV:
if (hw->soc->adv_pull_get) {
bool pullup;
pullup = param == MTK_PIN_CONFIG_PU_ADV;
err = hw->soc->adv_pull_get(hw, desc, pullup, &ret);
if (err)
return err;
} else {
return -ENOTSUPP;
}
break;
default:
return -ENOTSUPP;
}
*config = pinconf_to_config_packed(param, ret);
return 0;
}
static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *configs, unsigned int num_configs)
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
const struct mtk_pin_desc *desc;
u32 reg, param, arg;
int cfg, err = 0;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
for (cfg = 0; cfg < num_configs; cfg++) {
param = pinconf_to_config_param(configs[cfg]);
arg = pinconf_to_config_argument(configs[cfg]);
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
if (hw->soc->bias_disable_set) {
err = hw->soc->bias_disable_set(hw, desc);
if (err)
return err;
} else {
return -ENOTSUPP;
}
break;
case PIN_CONFIG_BIAS_PULL_UP:
if (hw->soc->bias_set) {
err = hw->soc->bias_set(hw, desc, 1);
if (err)
return err;
} else {
return -ENOTSUPP;
}
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
if (hw->soc->bias_set) {
err = hw->soc->bias_set(hw, desc, 0);
if (err)
return err;
} else {
return -ENOTSUPP;
}
break;
case PIN_CONFIG_OUTPUT_ENABLE:
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,
MTK_DISABLE);
if (err)
goto err;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
MTK_OUTPUT);
if (err)
goto err;
break;
case PIN_CONFIG_INPUT_ENABLE:
if (hw->soc->ies_present) {
mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_IES,
MTK_ENABLE);
}
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
MTK_INPUT);
if (err)
goto err;
break;
case PIN_CONFIG_SLEW_RATE:
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SR,
arg);
if (err)
goto err;
break;
case PIN_CONFIG_OUTPUT:
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
MTK_OUTPUT);
if (err)
goto err;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO,
arg);
if (err)
goto err;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
/* arg = 1: Input mode & SMT enable ;
* arg = 0: Output mode & SMT disable
*/
arg = arg ? 2 : 1;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
arg & 1);
if (err)
goto err;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,
!!(arg & 2));
if (err)
goto err;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
if (hw->soc->drive_set) {
err = hw->soc->drive_set(hw, desc, arg);
if (err)
return err;
} else {
err = -ENOTSUPP;
}
break;
case MTK_PIN_CONFIG_TDSEL:
case MTK_PIN_CONFIG_RDSEL:
reg = (param == MTK_PIN_CONFIG_TDSEL) ?
PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
err = mtk_hw_set_value(hw, desc, reg, arg);
if (err)
goto err;
break;
case MTK_PIN_CONFIG_PU_ADV:
case MTK_PIN_CONFIG_PD_ADV:
if (hw->soc->adv_pull_set) {
bool pullup;
pullup = param == MTK_PIN_CONFIG_PU_ADV;
err = hw->soc->adv_pull_set(hw, desc, pullup,
arg);
if (err)
return err;
} else {
return -ENOTSUPP;
}
break;
default:
err = -ENOTSUPP;
}
}
err:
return err;
}
static int mtk_pinconf_group_get(struct pinctrl_dev *pctldev,
unsigned int group, unsigned long *config)
{
const unsigned int *pins;
unsigned int i, npins, old = 0;
int ret;
ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
if (ret)
return ret;
for (i = 0; i < npins; i++) {
if (mtk_pinconf_get(pctldev, pins[i], config))
return -ENOTSUPP;
/* configs do not match between two pins */
if (i && old != *config)
return -ENOTSUPP;
old = *config;
}
return 0;
}
static int mtk_pinconf_group_set(struct pinctrl_dev *pctldev,
unsigned int group, unsigned long *configs,
unsigned int num_configs)
{
const unsigned int *pins;
unsigned int i, npins;
int ret;
ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
if (ret)
return ret;
for (i = 0; i < npins; i++) {
ret = mtk_pinconf_set(pctldev, pins[i], configs, num_configs);
if (ret)
return ret;
}
return 0;
}
static const struct pinctrl_ops mtk_pctlops = {
.get_groups_count = pinctrl_generic_get_group_count,
.get_group_name = pinctrl_generic_get_group_name,
.get_group_pins = pinctrl_generic_get_group_pins,
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
.dt_free_map = pinconf_generic_dt_free_map,
};
static const struct pinmux_ops mtk_pmxops = {
.get_functions_count = pinmux_generic_get_function_count,
.get_function_name = pinmux_generic_get_function_name,
.get_function_groups = pinmux_generic_get_function_groups,
.set_mux = mtk_pinmux_set_mux,
.gpio_request_enable = mtk_pinmux_gpio_request_enable,
.gpio_set_direction = mtk_pinmux_gpio_set_direction,
.strict = true,
};
static const struct pinconf_ops mtk_confops = {
.is_generic = true,
.pin_config_get = mtk_pinconf_get,
.pin_config_set = mtk_pinconf_set,
.pin_config_group_get = mtk_pinconf_group_get,
.pin_config_group_set = mtk_pinconf_group_set,
.pin_config_config_dbg_show = pinconf_generic_dump_config,
};
static struct pinctrl_desc mtk_desc = {
.name = PINCTRL_PINCTRL_DEV,
.pctlops = &mtk_pctlops,
.pmxops = &mtk_pmxops,
.confops = &mtk_confops,
.owner = THIS_MODULE,
};
static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio)
{
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
const struct mtk_pin_desc *desc;
int value, err;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
if (err)
return err;
return !!value;
}
static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
{
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
const struct mtk_pin_desc *desc;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value);
}
static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio)
{
return pinctrl_gpio_direction_input(chip->base + gpio);
}
static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
int value)
{
mtk_gpio_set(chip, gpio, value);
return pinctrl_gpio_direction_output(chip->base + gpio);
}
static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
{
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
const struct mtk_pin_desc *desc;
if (!hw->eint)
return -ENOTSUPP;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
if (desc->eint.eint_n == EINT_NA)
return -ENOTSUPP;
return mtk_eint_find_irq(hw->eint, desc->eint.eint_n);
}
static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
unsigned long config)
{
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
const struct mtk_pin_desc *desc;
u32 debounce;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
if (!hw->eint ||
pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE ||
desc->eint.eint_n == EINT_NA)
return -ENOTSUPP;
debounce = pinconf_to_config_argument(config);
return mtk_eint_set_debounce(hw->eint, desc->eint.eint_n, debounce);
}
static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np)
{
struct gpio_chip *chip = &hw->chip;
int ret;
chip->label = PINCTRL_PINCTRL_DEV;
chip->parent = hw->dev;
chip->request = gpiochip_generic_request;
chip->free = gpiochip_generic_free;
chip->direction_input = mtk_gpio_direction_input;
chip->direction_output = mtk_gpio_direction_output;
chip->get = mtk_gpio_get;
chip->set = mtk_gpio_set;
chip->to_irq = mtk_gpio_to_irq,
chip->set_config = mtk_gpio_set_config,
chip->base = -1;
chip->ngpio = hw->soc->npins;
chip->of_node = np;
chip->of_gpio_n_cells = 2;
ret = gpiochip_add_data(chip, hw);
if (ret < 0)
return ret;
/* Just for backward compatible for these old pinctrl nodes without
* "gpio-ranges" property. Otherwise, called directly from a
* DeviceTree-supported pinctrl driver is DEPRECATED.
* Please see Section 2.1 of
* Documentation/devicetree/bindings/gpio/gpio.txt on how to
* bind pinctrl and gpio drivers via the "gpio-ranges" property.
*/
if (!of_find_property(np, "gpio-ranges", NULL)) {
ret = gpiochip_add_pin_range(chip, dev_name(hw->dev), 0, 0,
chip->ngpio);
if (ret < 0) {
gpiochip_remove(chip);
return ret;
}
}
return 0;
}
static int mtk_build_groups(struct mtk_pinctrl *hw)
{
int err, i;
for (i = 0; i < hw->soc->ngrps; i++) {
const struct group_desc *group = hw->soc->grps + i;
err = pinctrl_generic_add_group(hw->pctrl, group->name,
group->pins, group->num_pins,
group->data);
if (err < 0) {
dev_err(hw->dev, "Failed to register group %s\n",
group->name);
return err;
}
}
return 0;
}
static int mtk_build_functions(struct mtk_pinctrl *hw)
{
int i, err;
for (i = 0; i < hw->soc->nfuncs ; i++) {
const struct function_desc *func = hw->soc->funcs + i;
err = pinmux_generic_add_function(hw->pctrl, func->name,
func->group_names,
func->num_group_names,
func->data);
if (err < 0) {
dev_err(hw->dev, "Failed to register function %s\n",
func->name);
return err;
}
}
return 0;
}
int mtk_moore_pinctrl_probe(struct platform_device *pdev,
const struct mtk_pin_soc *soc)
{
struct pinctrl_pin_desc *pins;
struct resource *res;
struct mtk_pinctrl *hw;
int err, i;
hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
if (!hw)
return -ENOMEM;
hw->soc = soc;
hw->dev = &pdev->dev;
if (!hw->soc->nbase_names) {
dev_err(&pdev->dev,
"SoC should be assigned at least one register base\n");
return -EINVAL;
}
hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names,
sizeof(*hw->base), GFP_KERNEL);
if (IS_ERR(hw->base))
return PTR_ERR(hw->base);
for (i = 0; i < hw->soc->nbase_names; i++) {
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
hw->soc->base_names[i]);
if (!res) {
dev_err(&pdev->dev, "missing IO resource\n");
return -ENXIO;
}
hw->base[i] = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(hw->base[i]))
return PTR_ERR(hw->base[i]);
}
hw->nbase = hw->soc->nbase_names;
/* Copy from internal struct mtk_pin_desc to register to the core */
pins = devm_kmalloc_array(&pdev->dev, hw->soc->npins, sizeof(*pins),
GFP_KERNEL);
if (IS_ERR(pins))
return PTR_ERR(pins);
for (i = 0; i < hw->soc->npins; i++) {
pins[i].number = hw->soc->pins[i].number;
pins[i].name = hw->soc->pins[i].name;
}
/* Setup pins descriptions per SoC types */
mtk_desc.pins = (const struct pinctrl_pin_desc *)pins;
mtk_desc.npins = hw->soc->npins;
mtk_desc.num_custom_params = ARRAY_SIZE(mtk_custom_bindings);
mtk_desc.custom_params = mtk_custom_bindings;
#ifdef CONFIG_DEBUG_FS
mtk_desc.custom_conf_items = mtk_conf_items;
#endif
err = devm_pinctrl_register_and_init(&pdev->dev, &mtk_desc, hw,
&hw->pctrl);
if (err)
return err;
/* Setup groups descriptions per SoC types */
err = mtk_build_groups(hw);
if (err) {
dev_err(&pdev->dev, "Failed to build groups\n");
return err;
}
/* Setup functions descriptions per SoC types */
err = mtk_build_functions(hw);
if (err) {
dev_err(&pdev->dev, "Failed to build functions\n");
return err;
}
/* For able to make pinctrl_claim_hogs, we must not enable pinctrl
* until all groups and functions are being added one.
*/
err = pinctrl_enable(hw->pctrl);
if (err)
return err;
err = mtk_build_eint(hw, pdev);
if (err)
dev_warn(&pdev->dev,
"Failed to add EINT, but pinctrl still can work\n");
/* Build gpiochip should be after pinctrl_enable is done */
err = mtk_build_gpiochip(hw, pdev->dev.of_node);
if (err) {
dev_err(&pdev->dev, "Failed to add gpio_chip\n");
return err;
}
platform_set_drvdata(pdev, hw);
return 0;
}

53
drivers/pinctrl/mediatek/pinctrl-moore.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2017-2018 MediaTek Inc.
*
* Author: Sean Wang <sean.wang@mediatek.com>
*
*/
#ifndef __PINCTRL_MOORE_H
#define __PINCTRL_MOORE_H
#include <linux/gpio.h>
#include <linux/gpio/driver.h>
#include <linux/io.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include "../core.h"
#include "../pinconf.h"
#include "../pinmux.h"
#include "mtk-eint.h"
#include "pinctrl-mtk-common-v2.h"
#define MTK_RANGE(_a) { .range = (_a), .nranges = ARRAY_SIZE(_a), }
#define MTK_PIN(_number, _name, _eint_m, _eint_n, _drv_n) { \
.number = _number, \
.name = _name, \
.eint = { \
.eint_m = _eint_m, \
.eint_n = _eint_n, \
}, \
.drv_n = _drv_n, \
.funcs = NULL, \
}
#define PINCTRL_PIN_GROUP(name, id) \
{ \
name, \
id##_pins, \
ARRAY_SIZE(id##_pins), \
id##_funcs, \
}
int mtk_moore_pinctrl_probe(struct platform_device *pdev,
const struct mtk_pin_soc *soc);
#endif /* __PINCTRL_MOORE_H */

1402
drivers/pinctrl/mediatek/pinctrl-mt7622.c
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1441
drivers/pinctrl/mediatek/pinctrl-mt7623.c Normal file
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544
drivers/pinctrl/mediatek/pinctrl-mt8183.c Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2018 MediaTek Inc.
*
* Author: Zhiyong Tao <zhiyong.tao@mediatek.com>
*
*/
#include "pinctrl-mtk-mt8183.h"
#include "pinctrl-paris.h"
/* MT8183 have multiple bases to program pin configuration listed as the below:
* iocfg[0]:0x10005000, iocfg[1]:0x11F20000, iocfg[2]:0x11E80000,
* iocfg[3]:0x11E70000, iocfg[4]:0x11E90000, iocfg[5]:0x11D30000,
* iocfg[6]:0x11D20000, iocfg[7]:0x11C50000, iocfg[8]:0x11F30000.
* _i_based could be used to indicate what base the pin should be mapped into.
*/
#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \
PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
_x_bits, 32, 0)
#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \
PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
_x_bits, 32, 1)
static const struct mtk_pin_field_calc mt8183_pin_mode_range[] = {
PIN_FIELD(0, 192, 0x300, 0x10, 0, 4),
};
static const struct mtk_pin_field_calc mt8183_pin_dir_range[] = {
PIN_FIELD(0, 192, 0x0, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt8183_pin_di_range[] = {
PIN_FIELD(0, 192, 0x200, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt8183_pin_do_range[] = {
PIN_FIELD(0, 192, 0x100, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt8183_pin_ies_range[] = {
PINS_FIELD_BASE(0, 3, 6, 0x000, 0x10, 3, 1),
PINS_FIELD_BASE(4, 7, 6, 0x000, 0x10, 5, 1),
PIN_FIELD_BASE(8, 8, 6, 0x000, 0x10, 0, 1),
PINS_FIELD_BASE(9, 10, 6, 0x000, 0x10, 12, 1),
PIN_FIELD_BASE(11, 11, 1, 0x000, 0x10, 3, 1),
PIN_FIELD_BASE(12, 12, 1, 0x000, 0x10, 7, 1),
PINS_FIELD_BASE(13, 16, 2, 0x000, 0x10, 2, 1),
PINS_FIELD_BASE(17, 20, 2, 0x000, 0x10, 3, 1),
PINS_FIELD_BASE(21, 24, 2, 0x000, 0x10, 4, 1),
PINS_FIELD_BASE(25, 28, 2, 0x000, 0x10, 5, 1),
PIN_FIELD_BASE(29, 29, 2, 0x000, 0x10, 6, 1),
PIN_FIELD_BASE(30, 30, 2, 0x000, 0x10, 7, 1),
PINS_FIELD_BASE(31, 31, 2, 0x000, 0x10, 8, 1),
PINS_FIELD_BASE(32, 34, 2, 0x000, 0x10, 7, 1),
PINS_FIELD_BASE(35, 37, 3, 0x000, 0x10, 0, 1),
PINS_FIELD_BASE(38, 40, 3, 0x000, 0x10, 1, 1),
PINS_FIELD_BASE(41, 42, 3, 0x000, 0x10, 2, 1),
PINS_FIELD_BASE(43, 45, 3, 0x000, 0x10, 3, 1),
PINS_FIELD_BASE(46, 47, 3, 0x000, 0x10, 4, 1),
PINS_FIELD_BASE(48, 49, 3, 0x000, 0x10, 5, 1),
PINS_FIELD_BASE(50, 51, 4, 0x000, 0x10, 0, 1),
PINS_FIELD_BASE(52, 57, 4, 0x000, 0x10, 1, 1),
PINS_FIELD_BASE(58, 60, 4, 0x000, 0x10, 2, 1),
PINS_FIELD_BASE(61, 64, 5, 0x000, 0x10, 0, 1),
PINS_FIELD_BASE(65, 66, 5, 0x000, 0x10, 1, 1),
PINS_FIELD_BASE(67, 68, 5, 0x000, 0x10, 2, 1),
PINS_FIELD_BASE(69, 71, 5, 0x000, 0x10, 3, 1),
PINS_FIELD_BASE(72, 76, 5, 0x000, 0x10, 4, 1),
PINS_FIELD_BASE(77, 80, 5, 0x000, 0x10, 5, 1),
PIN_FIELD_BASE(81, 81, 5, 0x000, 0x10, 6, 1),
PINS_FIELD_BASE(82, 83, 5, 0x000, 0x10, 7, 1),
PIN_FIELD_BASE(84, 84, 5, 0x000, 0x10, 6, 1),
PINS_FIELD_BASE(85, 88, 5, 0x000, 0x10, 8, 1),
PIN_FIELD_BASE(89, 89, 6, 0x000, 0x10, 11, 1),
PIN_FIELD_BASE(90, 90, 6, 0x000, 0x10, 1, 1),
PINS_FIELD_BASE(91, 94, 6, 0x000, 0x10, 2, 1),
PINS_FIELD_BASE(95, 96, 6, 0x000, 0x10, 6, 1),
PINS_FIELD_BASE(97, 98, 6, 0x000, 0x10, 7, 1),
PIN_FIELD_BASE(99, 99, 6, 0x000, 0x10, 8, 1),
PIN_FIELD_BASE(100, 100, 6, 0x000, 0x10, 9, 1),
PINS_FIELD_BASE(101, 102, 6, 0x000, 0x10, 10, 1),
PINS_FIELD_BASE(103, 104, 6, 0x000, 0x10, 13, 1),
PINS_FIELD_BASE(105, 106, 6, 0x000, 0x10, 14, 1),
PIN_FIELD_BASE(107, 107, 7, 0x000, 0x10, 0, 1),
PIN_FIELD_BASE(108, 108, 7, 0x000, 0x10, 1, 1),
PIN_FIELD_BASE(109, 109, 7, 0x000, 0x10, 2, 1),
PIN_FIELD_BASE(110, 110, 7, 0x000, 0x10, 0, 1),
PIN_FIELD_BASE(111, 111, 7, 0x000, 0x10, 3, 1),
PIN_FIELD_BASE(112, 112, 7, 0x000, 0x10, 2, 1),
PIN_FIELD_BASE(113, 113, 7, 0x000, 0x10, 4, 1),
PIN_FIELD_BASE(114, 114, 7, 0x000, 0x10, 5, 1),
PIN_FIELD_BASE(115, 115, 7, 0x000, 0x10, 6, 1),
PIN_FIELD_BASE(116, 116, 7, 0x000, 0x10, 7, 1),
PIN_FIELD_BASE(117, 117, 7, 0x000, 0x10, 8, 1),
PIN_FIELD_BASE(118, 118, 7, 0x000, 0x10, 9, 1),
PIN_FIELD_BASE(119, 119, 7, 0x000, 0x10, 10, 1),
PIN_FIELD_BASE(120, 120, 7, 0x000, 0x10, 11, 1),
PIN_FIELD_BASE(121, 121, 7, 0x000, 0x10, 12, 1),
PIN_FIELD_BASE(122, 122, 8, 0x000, 0x10, 0, 1),
PIN_FIELD_BASE(123, 123, 8, 0x000, 0x10, 1, 1),
PIN_FIELD_BASE(124, 124, 8, 0x000, 0x10, 2, 1),
PINS_FIELD_BASE(125, 130, 8, 0x000, 0x10, 1, 1),
PIN_FIELD_BASE(131, 131, 8, 0x000, 0x10, 3, 1),
PIN_FIELD_BASE(132, 132, 8, 0x000, 0x10, 1, 1),
PIN_FIELD_BASE(133, 133, 8, 0x000, 0x10, 4, 1),
PIN_FIELD_BASE(134, 134, 1, 0x000, 0x10, 0, 1),
PIN_FIELD_BASE(135, 135, 1, 0x000, 0x10, 1, 1),
PINS_FIELD_BASE(136, 143, 1, 0x000, 0x10, 2, 1),
PINS_FIELD_BASE(144, 147, 1, 0x000, 0x10, 4, 1),
PIN_FIELD_BASE(148, 148, 1, 0x000, 0x10, 5, 1),
PIN_FIELD_BASE(149, 149, 1, 0x000, 0x10, 6, 1),
PINS_FIELD_BASE(150, 153, 1, 0x000, 0x10, 8, 1),
PIN_FIELD_BASE(154, 154, 1, 0x000, 0x10, 9, 1),
PINS_FIELD_BASE(155, 157, 1, 0x000, 0x10, 10, 1),
PINS_FIELD_BASE(158, 160, 1, 0x000, 0x10, 8, 1),
PINS_FIELD_BASE(161, 164, 2, 0x000, 0x10, 0, 1),
PINS_FIELD_BASE(165, 166, 2, 0x000, 0x10, 1, 1),
PINS_FIELD_BASE(167, 168, 4, 0x000, 0x10, 2, 1),
PIN_FIELD_BASE(169, 169, 4, 0x000, 0x10, 3, 1),
PINS_FIELD_BASE(170, 174, 4, 0x000, 0x10, 4, 1),
PINS_FIELD_BASE(175, 176, 4, 0x000, 0x10, 3, 1),
PINS_FIELD_BASE(177, 179, 6, 0x000, 0x10, 4, 1),
};
static const struct mtk_pin_field_calc mt8183_pin_smt_range[] = {
PINS_FIELD_BASE(0, 3, 6, 0x010, 0x10, 3, 1),
PINS_FIELD_BASE(4, 7, 6, 0x010, 0x10, 5, 1),
PIN_FIELD_BASE(8, 8, 6, 0x010, 0x10, 0, 1),
PINS_FIELD_BASE(9, 10, 6, 0x010, 0x10, 12, 1),
PIN_FIELD_BASE(11, 11, 1, 0x010, 0x10, 3, 1),
PIN_FIELD_BASE(12, 12, 1, 0x010, 0x10, 7, 1),
PINS_FIELD_BASE(13, 16, 2, 0x010, 0x10, 2, 1),
PINS_FIELD_BASE(17, 20, 2, 0x010, 0x10, 3, 1),
PINS_FIELD_BASE(21, 24, 2, 0x010, 0x10, 4, 1),
PINS_FIELD_BASE(25, 28, 2, 0x010, 0x10, 5, 1),
PIN_FIELD_BASE(29, 29, 2, 0x010, 0x10, 6, 1),
PIN_FIELD_BASE(30, 30, 2, 0x010, 0x10, 7, 1),
PINS_FIELD_BASE(31, 31, 2, 0x010, 0x10, 8, 1),
PINS_FIELD_BASE(32, 34, 2, 0x010, 0x10, 7, 1),
PINS_FIELD_BASE(35, 37, 3, 0x010, 0x10, 0, 1),
PINS_FIELD_BASE(38, 40, 3, 0x010, 0x10, 1, 1),
PINS_FIELD_BASE(41, 42, 3, 0x010, 0x10, 2, 1),
PINS_FIELD_BASE(43, 45, 3, 0x010, 0x10, 3, 1),
PINS_FIELD_BASE(46, 47, 3, 0x010, 0x10, 4, 1),
PINS_FIELD_BASE(48, 49, 3, 0x010, 0x10, 5, 1),
PINS_FIELD_BASE(50, 51, 4, 0x010, 0x10, 0, 1),
PINS_FIELD_BASE(52, 57, 4, 0x010, 0x10, 1, 1),
PINS_FIELD_BASE(58, 60, 4, 0x010, 0x10, 2, 1),
PINS_FIELD_BASE(61, 64, 5, 0x010, 0x10, 0, 1),
PINS_FIELD_BASE(65, 66, 5, 0x010, 0x10, 1, 1),
PINS_FIELD_BASE(67, 68, 5, 0x010, 0x10, 2, 1),
PINS_FIELD_BASE(69, 71, 5, 0x010, 0x10, 3, 1),
PINS_FIELD_BASE(72, 76, 5, 0x010, 0x10, 4, 1),
PINS_FIELD_BASE(77, 80, 5, 0x010, 0x10, 5, 1),
PIN_FIELD_BASE(81, 81, 5, 0x010, 0x10, 6, 1),
PINS_FIELD_BASE(82, 83, 5, 0x010, 0x10, 7, 1),
PIN_FIELD_BASE(84, 84, 5, 0x010, 0x10, 6, 1),
PINS_FIELD_BASE(85, 88, 5, 0x010, 0x10, 8, 1),
PIN_FIELD_BASE(89, 89, 6, 0x010, 0x10, 11, 1),
PIN_FIELD_BASE(90, 90, 6, 0x010, 0x10, 1, 1),
PINS_FIELD_BASE(91, 94, 6, 0x010, 0x10, 2, 1),
PINS_FIELD_BASE(95, 96, 6, 0x010, 0x10, 6, 1),
PINS_FIELD_BASE(97, 98, 6, 0x010, 0x10, 7, 1),
PIN_FIELD_BASE(99, 99, 6, 0x010, 0x10, 8, 1),
PIN_FIELD_BASE(100, 100, 6, 0x010, 0x10, 9, 1),
PINS_FIELD_BASE(101, 102, 6, 0x010, 0x10, 10, 1),
PINS_FIELD_BASE(103, 104, 6, 0x010, 0x10, 13, 1),
PINS_FIELD_BASE(105, 106, 6, 0x010, 0x10, 14, 1),
PIN_FIELD_BASE(107, 107, 7, 0x010, 0x10, 0, 1),
PIN_FIELD_BASE(108, 108, 7, 0x010, 0x10, 1, 1),
PIN_FIELD_BASE(109, 109, 7, 0x010, 0x10, 2, 1),
PIN_FIELD_BASE(110, 110, 7, 0x010, 0x10, 0, 1),
PIN_FIELD_BASE(111, 111, 7, 0x010, 0x10, 3, 1),
PIN_FIELD_BASE(112, 112, 7, 0x010, 0x10, 2, 1),
PIN_FIELD_BASE(113, 113, 7, 0x010, 0x10, 4, 1),
PIN_FIELD_BASE(114, 114, 7, 0x010, 0x10, 5, 1),
PIN_FIELD_BASE(115, 115, 7, 0x010, 0x10, 6, 1),
PIN_FIELD_BASE(116, 116, 7, 0x010, 0x10, 7, 1),
PIN_FIELD_BASE(117, 117, 7, 0x010, 0x10, 8, 1),
PIN_FIELD_BASE(118, 118, 7, 0x010, 0x10, 9, 1),
PIN_FIELD_BASE(119, 119, 7, 0x010, 0x10, 10, 1),
PIN_FIELD_BASE(120, 120, 7, 0x010, 0x10, 11, 1),
PIN_FIELD_BASE(121, 121, 7, 0x010, 0x10, 12, 1),
PIN_FIELD_BASE(122, 122, 8, 0x010, 0x10, 0, 1),
PIN_FIELD_BASE(123, 123, 8, 0x010, 0x10, 1, 1),
PIN_FIELD_BASE(124, 124, 8, 0x010, 0x10, 2, 1),
PINS_FIELD_BASE(125, 130, 8, 0x010, 0x10, 1, 1),
PIN_FIELD_BASE(131, 131, 8, 0x010, 0x10, 3, 1),
PIN_FIELD_BASE(132, 132, 8, 0x010, 0x10, 1, 1),
PIN_FIELD_BASE(133, 133, 8, 0x010, 0x10, 4, 1),
PIN_FIELD_BASE(134, 134, 1, 0x010, 0x10, 0, 1),
PIN_FIELD_BASE(135, 135, 1, 0x010, 0x10, 1, 1),
PINS_FIELD_BASE(136, 143, 1, 0x010, 0x10, 2, 1),
PINS_FIELD_BASE(144, 147, 1, 0x010, 0x10, 4, 1),
PIN_FIELD_BASE(148, 148, 1, 0x010, 0x10, 5, 1),
PIN_FIELD_BASE(149, 149, 1, 0x010, 0x10, 6, 1),
PINS_FIELD_BASE(150, 153, 1, 0x010, 0x10, 8, 1),
PIN_FIELD_BASE(154, 154, 1, 0x010, 0x10, 9, 1),
PINS_FIELD_BASE(155, 157, 1, 0x010, 0x10, 10, 1),
PINS_FIELD_BASE(158, 160, 1, 0x010, 0x10, 8, 1),
PINS_FIELD_BASE(161, 164, 2, 0x010, 0x10, 0, 1),
PINS_FIELD_BASE(165, 166, 2, 0x010, 0x10, 1, 1),
PINS_FIELD_BASE(167, 168, 4, 0x010, 0x10, 2, 1),
PIN_FIELD_BASE(169, 169, 4, 0x010, 0x10, 3, 1),
PINS_FIELD_BASE(170, 174, 4, 0x010, 0x10, 4, 1),
PINS_FIELD_BASE(175, 176, 4, 0x010, 0x10, 3, 1),
PINS_FIELD_BASE(177, 179, 6, 0x010, 0x10, 4, 1),
};
static const struct mtk_pin_field_calc mt8183_pin_pullen_range[] = {
PIN_FIELD_BASE(0, 3, 6, 0x060, 0x10, 6, 1),
PIN_FIELD_BASE(4, 7, 6, 0x060, 0x10, 11, 1),
PIN_FIELD_BASE(8, 8, 6, 0x060, 0x10, 0, 1),
PIN_FIELD_BASE(9, 10, 6, 0x060, 0x10, 26, 1),
PIN_FIELD_BASE(11, 11, 1, 0x060, 0x10, 10, 1),
PIN_FIELD_BASE(12, 12, 1, 0x060, 0x10, 17, 1),
PIN_FIELD_BASE(13, 28, 2, 0x060, 0x10, 6, 1),
PIN_FIELD_BASE(43, 49, 3, 0x060, 0x10, 8, 1),
PIN_FIELD_BASE(50, 60, 4, 0x060, 0x10, 0, 1),
PIN_FIELD_BASE(61, 88, 5, 0x060, 0x10, 0, 1),
PIN_FIELD_BASE(89, 89, 6, 0x060, 0x10, 24, 1),
PIN_FIELD_BASE(90, 90, 6, 0x060, 0x10, 1, 1),
PIN_FIELD_BASE(95, 95, 6, 0x060, 0x10, 15, 1),
PIN_FIELD_BASE(96, 102, 6, 0x060, 0x10, 17, 1),
PIN_FIELD_BASE(103, 106, 6, 0x060, 0x10, 28, 1),
PIN_FIELD_BASE(107, 121, 7, 0x060, 0x10, 0, 1),
PIN_FIELD_BASE(134, 143, 1, 0x060, 0x10, 0, 1),
PIN_FIELD_BASE(144, 149, 1, 0x060, 0x10, 11, 1),
PIN_FIELD_BASE(150, 160, 1, 0x060, 0x10, 18, 1),
PIN_FIELD_BASE(161, 166, 2, 0x060, 0x10, 0, 1),
PIN_FIELD_BASE(167, 176, 4, 0x060, 0x10, 11, 1),
PIN_FIELD_BASE(177, 177, 6, 0x060, 0x10, 10, 1),
PIN_FIELD_BASE(178, 178, 6, 0x060, 0x10, 16, 1),
PIN_FIELD_BASE(179, 179, 6, 0x060, 0x10, 25, 1),
};
static const struct mtk_pin_field_calc mt8183_pin_pullsel_range[] = {
PIN_FIELD_BASE(0, 3, 6, 0x080, 0x10, 6, 1),
PIN_FIELD_BASE(4, 7, 6, 0x080, 0x10, 11, 1),
PIN_FIELD_BASE(8, 8, 6, 0x080, 0x10, 0, 1),
PIN_FIELD_BASE(9, 10, 6, 0x080, 0x10, 26, 1),
PIN_FIELD_BASE(11, 11, 1, 0x080, 0x10, 10, 1),
PIN_FIELD_BASE(12, 12, 1, 0x080, 0x10, 17, 1),
PIN_FIELD_BASE(13, 28, 2, 0x080, 0x10, 6, 1),
PIN_FIELD_BASE(43, 49, 3, 0x080, 0x10, 8, 1),
PIN_FIELD_BASE(50, 60, 4, 0x080, 0x10, 0, 1),
PIN_FIELD_BASE(61, 88, 5, 0x080, 0x10, 0, 1),
PIN_FIELD_BASE(89, 89, 6, 0x080, 0x10, 24, 1),
PIN_FIELD_BASE(90, 90, 6, 0x080, 0x10, 1, 1),
PIN_FIELD_BASE(95, 95, 6, 0x080, 0x10, 15, 1),
PIN_FIELD_BASE(96, 102, 6, 0x080, 0x10, 17, 1),
PIN_FIELD_BASE(103, 106, 6, 0x080, 0x10, 28, 1),
PIN_FIELD_BASE(107, 121, 7, 0x080, 0x10, 0, 1),
PIN_FIELD_BASE(134, 143, 1, 0x080, 0x10, 0, 1),
PIN_FIELD_BASE(144, 149, 1, 0x080, 0x10, 11, 1),
PIN_FIELD_BASE(150, 160, 1, 0x080, 0x10, 18, 1),
PIN_FIELD_BASE(161, 166, 2, 0x080, 0x10, 0, 1),
PIN_FIELD_BASE(167, 176, 4, 0x080, 0x10, 11, 1),
PIN_FIELD_BASE(177, 177, 6, 0x080, 0x10, 10, 1),
PIN_FIELD_BASE(178, 178, 6, 0x080, 0x10, 16, 1),
PIN_FIELD_BASE(179, 179, 6, 0x080, 0x10, 25, 1),
};
static const struct mtk_pin_field_calc mt8183_pin_drv_range[] = {
PINS_FIELD_BASE(0, 3, 6, 0x0A0, 0x10, 12, 3),
PINS_FIELD_BASE(4, 7, 6, 0x0A0, 0x10, 20, 3),
PIN_FIELD_BASE(8, 8, 6, 0x0A0, 0x10, 0, 3),
PINS_FIELD_BASE(9, 10, 6, 0x0B0, 0x10, 16, 3),
PIN_FIELD_BASE(11, 11, 1, 0x0A0, 0x10, 12, 3),
PIN_FIELD_BASE(12, 12, 1, 0x0A0, 0x10, 28, 3),
PINS_FIELD_BASE(13, 16, 2, 0x0A0, 0x10, 8, 3),
PINS_FIELD_BASE(17, 20, 2, 0x0A0, 0x10, 12, 3),
PINS_FIELD_BASE(21, 24, 2, 0x0A0, 0x10, 16, 3),
PINS_FIELD_BASE(25, 28, 2, 0x0A0, 0x10, 20, 3),
PIN_FIELD_BASE(29, 29, 2, 0x0A0, 0x10, 24, 3),
PIN_FIELD_BASE(30, 30, 2, 0x0A0, 0x10, 28, 3),
PINS_FIELD_BASE(31, 31, 2, 0x0B0, 0x10, 0, 3),
PINS_FIELD_BASE(32, 34, 2, 0x0A0, 0x10, 28, 3),
PINS_FIELD_BASE(35, 37, 3, 0x0A0, 0x10, 0, 3),
PINS_FIELD_BASE(38, 40, 3, 0x0A0, 0x10, 4, 3),
PINS_FIELD_BASE(41, 42, 3, 0x0A0, 0x10, 8, 3),
PINS_FIELD_BASE(43, 45, 3, 0x0A0, 0x10, 12, 3),
PINS_FIELD_BASE(46, 47, 3, 0x0A0, 0x10, 16, 3),
PINS_FIELD_BASE(48, 49, 3, 0x0A0, 0x10, 20, 3),
PINS_FIELD_BASE(50, 51, 4, 0x0A0, 0x10, 0, 3),
PINS_FIELD_BASE(52, 57, 4, 0x0A0, 0x10, 4, 3),
PINS_FIELD_BASE(58, 60, 4, 0x0A0, 0x10, 8, 3),
PINS_FIELD_BASE(61, 64, 5, 0x0A0, 0x10, 0, 3),
PINS_FIELD_BASE(65, 66, 5, 0x0A0, 0x10, 4, 3),
PINS_FIELD_BASE(67, 68, 5, 0x0A0, 0x10, 8, 3),
PINS_FIELD_BASE(69, 71, 5, 0x0A0, 0x10, 12, 3),
PINS_FIELD_BASE(72, 76, 5, 0x0A0, 0x10, 16, 3),
PINS_FIELD_BASE(77, 80, 5, 0x0A0, 0x10, 20, 3),
PIN_FIELD_BASE(81, 81, 5, 0x0A0, 0x10, 24, 3),
PINS_FIELD_BASE(82, 83, 5, 0x0A0, 0x10, 28, 3),
PIN_FIELD_BASE(84, 84, 5, 0x0A0, 0x10, 24, 3),
PINS_FIELD_BASE(85, 88, 5, 0x0B0, 0x10, 0, 3),
PIN_FIELD_BASE(89, 89, 6, 0x0B0, 0x10, 12, 3),
PIN_FIELD_BASE(90, 90, 6, 0x0A0, 0x10, 4, 3),
PINS_FIELD_BASE(91, 94, 6, 0x0A0, 0x10, 8, 3),
PINS_FIELD_BASE(95, 96, 6, 0x0A0, 0x10, 24, 3),
PINS_FIELD_BASE(97, 98, 6, 0x0A0, 0x10, 28, 3),
PIN_FIELD_BASE(99, 99, 6, 0x0B0, 0x10, 0, 3),
PIN_FIELD_BASE(100, 100, 6, 0x0B0, 0x10, 4, 3),
PINS_FIELD_BASE(101, 102, 6, 0x0B0, 0x10, 8, 3),
PINS_FIELD_BASE(103, 104, 6, 0x0B0, 0x10, 20, 3),
PINS_FIELD_BASE(105, 106, 6, 0x0B0, 0x10, 24, 3),
PIN_FIELD_BASE(107, 107, 7, 0x0A0, 0x10, 0, 3),
PIN_FIELD_BASE(108, 108, 7, 0x0A0, 0x10, 4, 3),
PIN_FIELD_BASE(109, 109, 7, 0x0A0, 0x10, 8, 3),
PIN_FIELD_BASE(110, 110, 7, 0x0A0, 0x10, 0, 3),
PIN_FIELD_BASE(111, 111, 7, 0x0A0, 0x10, 4, 3),
PIN_FIELD_BASE(112, 112, 7, 0x0A0, 0x10, 8, 3),
PIN_FIELD_BASE(113, 113, 7, 0x0A0, 0x10, 16, 3),
PIN_FIELD_BASE(114, 114, 7, 0x0A0, 0x10, 20, 3),
PIN_FIELD_BASE(115, 115, 7, 0x0A0, 0x10, 24, 3),
PIN_FIELD_BASE(116, 116, 7, 0x0A0, 0x10, 28, 3),
PIN_FIELD_BASE(117, 117, 7, 0x0B0, 0x10, 0, 3),
PIN_FIELD_BASE(118, 118, 7, 0x0B0, 0x10, 4, 3),
PIN_FIELD_BASE(119, 119, 7, 0x0B0, 0x10, 8, 3),
PIN_FIELD_BASE(120, 120, 7, 0x0B0, 0x10, 12, 3),
PIN_FIELD_BASE(121, 121, 7, 0x0B0, 0x10, 16, 3),
PIN_FIELD_BASE(122, 122, 8, 0x0A0, 0x10, 0, 3),
PIN_FIELD_BASE(123, 123, 8, 0x0A0, 0x10, 4, 3),
PIN_FIELD_BASE(124, 124, 8, 0x0A0, 0x10, 8, 3),
PINS_FIELD_BASE(125, 130, 8, 0x0A0, 0x10, 4, 3),
PIN_FIELD_BASE(131, 131, 8, 0x0A0, 0x10, 12, 3),
PIN_FIELD_BASE(132, 132, 8, 0x0A0, 0x10, 4, 3),
PIN_FIELD_BASE(133, 133, 8, 0x0A0, 0x10, 16, 3),
PIN_FIELD_BASE(134, 134, 1, 0x0A0, 0x10, 0, 3),
PIN_FIELD_BASE(135, 135, 1, 0x0A0, 0x10, 4, 3),
PINS_FIELD_BASE(136, 143, 1, 0x0A0, 0x10, 8, 3),
PINS_FIELD_BASE(144, 147, 1, 0x0A0, 0x10, 16, 3),
PIN_FIELD_BASE(148, 148, 1, 0x0A0, 0x10, 20, 3),
PIN_FIELD_BASE(149, 149, 1, 0x0A0, 0x10, 24, 3),
PINS_FIELD_BASE(150, 153, 1, 0x0B0, 0x10, 0, 3),
PIN_FIELD_BASE(154, 154, 1, 0x0B0, 0x10, 4, 3),
PINS_FIELD_BASE(155, 157, 1, 0x0B0, 0x10, 8, 3),
PINS_FIELD_BASE(158, 160, 1, 0x0B0, 0x10, 0, 3),
PINS_FIELD_BASE(161, 164, 2, 0x0A0, 0x10, 0, 3),
PINS_FIELD_BASE(165, 166, 2, 0x0A0, 0x10, 4, 3),
PINS_FIELD_BASE(167, 168, 4, 0x0A0, 0x10, 8, 3),
PIN_FIELD_BASE(169, 169, 4, 0x0A0, 0x10, 12, 3),
PINS_FIELD_BASE(170, 174, 4, 0x0A0, 0x10, 16, 3),
PINS_FIELD_BASE(175, 176, 4, 0x0A0, 0x10, 12, 3),
PINS_FIELD_BASE(177, 179, 6, 0x0A0, 0x10, 16, 3),
};
static const struct mtk_pin_field_calc mt8183_pin_pupd_range[] = {
PIN_FIELD_BASE(29, 29, 2, 0x0C0, 0x10, 2, 1),
PIN_FIELD_BASE(30, 30, 2, 0x0C0, 0x10, 6, 1),
PIN_FIELD_BASE(31, 31, 2, 0x0C0, 0x10, 10, 1),
PIN_FIELD_BASE(32, 32, 2, 0x0C0, 0x10, 14, 1),
PIN_FIELD_BASE(33, 33, 2, 0x0C0, 0x10, 18, 1),
PIN_FIELD_BASE(34, 34, 2, 0x0C0, 0x10, 22, 1),
PIN_FIELD_BASE(35, 35, 3, 0x0C0, 0x10, 2, 1),
PIN_FIELD_BASE(36, 36, 3, 0x0C0, 0x10, 6, 1),
PIN_FIELD_BASE(37, 37, 3, 0x0C0, 0x10, 10, 1),
PIN_FIELD_BASE(38, 38, 3, 0x0C0, 0x10, 14, 1),
PIN_FIELD_BASE(39, 39, 3, 0x0C0, 0x10, 18, 1),
PIN_FIELD_BASE(40, 40, 3, 0x0C0, 0x10, 22, 1),
PIN_FIELD_BASE(41, 41, 3, 0x0C0, 0x10, 26, 1),
PIN_FIELD_BASE(42, 42, 3, 0x0C0, 0x10, 30, 1),
PIN_FIELD_BASE(91, 91, 6, 0x0C0, 0x10, 2, 1),
PIN_FIELD_BASE(92, 92, 6, 0x0C0, 0x10, 6, 1),
PIN_FIELD_BASE(93, 93, 6, 0x0C0, 0x10, 10, 1),
PIN_FIELD_BASE(94, 94, 6, 0x0C0, 0x10, 14, 1),
PIN_FIELD_BASE(122, 122, 8, 0x0C0, 0x10, 2, 1),
PIN_FIELD_BASE(123, 123, 8, 0x0C0, 0x10, 6, 1),
PIN_FIELD_BASE(124, 124, 8, 0x0C0, 0x10, 10, 1),
PIN_FIELD_BASE(125, 125, 8, 0x0C0, 0x10, 14, 1),
PIN_FIELD_BASE(126, 126, 8, 0x0C0, 0x10, 18, 1),
PIN_FIELD_BASE(127, 127, 8, 0x0C0, 0x10, 22, 1),
PIN_FIELD_BASE(128, 128, 8, 0x0C0, 0x10, 26, 1),
PIN_FIELD_BASE(129, 129, 8, 0x0C0, 0x10, 30, 1),
PIN_FIELD_BASE(130, 130, 8, 0x0D0, 0x10, 2, 1),
PIN_FIELD_BASE(131, 131, 8, 0x0D0, 0x10, 6, 1),
PIN_FIELD_BASE(132, 132, 8, 0x0D0, 0x10, 10, 1),
PIN_FIELD_BASE(133, 133, 8, 0x0D0, 0x10, 14, 1),
};
static const struct mtk_pin_field_calc mt8183_pin_r0_range[] = {
PIN_FIELD_BASE(29, 29, 2, 0x0C0, 0x10, 0, 1),
PIN_FIELD_BASE(30, 30, 2, 0x0C0, 0x10, 4, 1),
PIN_FIELD_BASE(31, 31, 2, 0x0C0, 0x10, 8, 1),
PIN_FIELD_BASE(32, 32, 2, 0x0C0, 0x10, 12, 1),
PIN_FIELD_BASE(33, 33, 2, 0x0C0, 0x10, 16, 1),
PIN_FIELD_BASE(34, 34, 2, 0x0C0, 0x10, 20, 1),
PIN_FIELD_BASE(35, 35, 3, 0x0C0, 0x10, 0, 1),
PIN_FIELD_BASE(36, 36, 3, 0x0C0, 0x10, 4, 1),
PIN_FIELD_BASE(37, 37, 3, 0x0C0, 0x10, 8, 1),
PIN_FIELD_BASE(38, 38, 3, 0x0C0, 0x10, 12, 1),
PIN_FIELD_BASE(39, 39, 3, 0x0C0, 0x10, 16, 1),
PIN_FIELD_BASE(40, 40, 3, 0x0C0, 0x10, 20, 1),
PIN_FIELD_BASE(41, 41, 3, 0x0C0, 0x10, 24, 1),
PIN_FIELD_BASE(42, 42, 3, 0x0C0, 0x10, 28, 1),
PIN_FIELD_BASE(48, 48, 3, 0x0F0, 0x10, 18, 1),
PIN_FIELD_BASE(49, 49, 3, 0x0F0, 0x10, 13, 1),
PIN_FIELD_BASE(50, 50, 4, 0x0F0, 0x10, 10, 1),
PIN_FIELD_BASE(51, 51, 4, 0x0F0, 0x10, 5, 1),
PIN_FIELD_BASE(81, 81, 5, 0x0F0, 0x10, 7, 1),
PIN_FIELD_BASE(82, 82, 5, 0x0F0, 0x10, 5, 1),
PIN_FIELD_BASE(83, 83, 5, 0x0F0, 0x10, 15, 1),
PIN_FIELD_BASE(84, 84, 5, 0x0F0, 0x10, 17, 1),
PIN_FIELD_BASE(91, 91, 6, 0x0C0, 0x10, 0, 1),
PIN_FIELD_BASE(92, 92, 6, 0x0C0, 0x10, 4, 1),
PIN_FIELD_BASE(93, 93, 6, 0x0C0, 0x10, 8, 1),
PIN_FIELD_BASE(94, 94, 6, 0x0C0, 0x10, 12, 1),
PIN_FIELD_BASE(103, 103, 6, 0x0F0, 0x10, 20, 1),
PIN_FIELD_BASE(104, 104, 6, 0x0F0, 0x10, 10, 1),
PIN_FIELD_BASE(105, 105, 6, 0x0F0, 0x10, 22, 1),
PIN_FIELD_BASE(106, 106, 6, 0x0F0, 0x10, 12, 1),
PIN_FIELD_BASE(122, 122, 8, 0x0C0, 0x10, 0, 1),
PIN_FIELD_BASE(123, 123, 8, 0x0C0, 0x10, 4, 1),
PIN_FIELD_BASE(124, 124, 8, 0x0C0, 0x10, 8, 1),
PIN_FIELD_BASE(125, 125, 8, 0x0C0, 0x10, 12, 1),
PIN_FIELD_BASE(126, 126, 8, 0x0C0, 0x10, 16, 1),
PIN_FIELD_BASE(127, 127, 8, 0x0C0, 0x10, 20, 1),
PIN_FIELD_BASE(128, 128, 8, 0x0C0, 0x10, 24, 1),
PIN_FIELD_BASE(129, 129, 8, 0x0C0, 0x10, 28, 1),
PIN_FIELD_BASE(130, 130, 8, 0x0D0, 0x10, 0, 1),
PIN_FIELD_BASE(131, 131, 8, 0x0D0, 0x10, 4, 1),
PIN_FIELD_BASE(132, 132, 8, 0x0D0, 0x10, 8, 1),
PIN_FIELD_BASE(133, 133, 8, 0x0D0, 0x10, 12, 1),
};
static const struct mtk_pin_field_calc mt8183_pin_r1_range[] = {
PIN_FIELD_BASE(29, 29, 2, 0x0C0, 0x10, 1, 1),
PIN_FIELD_BASE(30, 30, 2, 0x0C0, 0x10, 5, 1),
PIN_FIELD_BASE(31, 31, 2, 0x0C0, 0x10, 9, 1),
PIN_FIELD_BASE(32, 32, 2, 0x0C0, 0x10, 13, 1),
PIN_FIELD_BASE(33, 33, 2, 0x0C0, 0x10, 17, 1),
PIN_FIELD_BASE(34, 34, 2, 0x0C0, 0x10, 21, 1),
PIN_FIELD_BASE(35, 35, 3, 0x0C0, 0x10, 1, 1),
PIN_FIELD_BASE(36, 36, 3, 0x0C0, 0x10, 5, 1),
PIN_FIELD_BASE(37, 37, 3, 0x0C0, 0x10, 9, 1),
PIN_FIELD_BASE(38, 38, 3, 0x0C0, 0x10, 13, 1),
PIN_FIELD_BASE(39, 39, 3, 0x0C0, 0x10, 17, 1),
PIN_FIELD_BASE(40, 40, 3, 0x0C0, 0x10, 21, 1),
PIN_FIELD_BASE(41, 41, 3, 0x0C0, 0x10, 25, 1),
PIN_FIELD_BASE(42, 42, 3, 0x0C0, 0x10, 29, 1),
PIN_FIELD_BASE(48, 48, 3, 0x0F0, 0x10, 19, 1),
PIN_FIELD_BASE(49, 49, 3, 0x0F0, 0x10, 14, 1),
PIN_FIELD_BASE(50, 50, 4, 0x0F0, 0x10, 11, 1),
PIN_FIELD_BASE(51, 51, 4, 0x0F0, 0x10, 6, 1),
PIN_FIELD_BASE(81, 81, 5, 0x0F0, 0x10, 8, 1),
PIN_FIELD_BASE(82, 82, 5, 0x0F0, 0x10, 6, 1),
PIN_FIELD_BASE(83, 83, 5, 0x0F0, 0x10, 16, 1),
PIN_FIELD_BASE(84, 84, 5, 0x0F0, 0x10, 18, 1),
PIN_FIELD_BASE(91, 91, 6, 0x0C0, 0x10, 1, 1),
PIN_FIELD_BASE(92, 92, 6, 0x0C0, 0x10, 5, 1),
PIN_FIELD_BASE(93, 93, 6, 0x0C0, 0x10, 9, 1),
PIN_FIELD_BASE(94, 94, 6, 0x0C0, 0x10, 13, 1),
PIN_FIELD_BASE(103, 103, 6, 0x0F0, 0x10, 21, 1),
PIN_FIELD_BASE(104, 104, 6, 0x0F0, 0x10, 11, 1),
PIN_FIELD_BASE(105, 105, 6, 0x0F0, 0x10, 23, 1),
PIN_FIELD_BASE(106, 106, 6, 0x0F0, 0x10, 13, 1),
PIN_FIELD_BASE(122, 122, 8, 0x0C0, 0x10, 1, 1),
PIN_FIELD_BASE(123, 123, 8, 0x0C0, 0x10, 5, 1),
PIN_FIELD_BASE(124, 124, 8, 0x0C0, 0x10, 9, 1),
PIN_FIELD_BASE(125, 125, 8, 0x0C0, 0x10, 13, 1),
PIN_FIELD_BASE(126, 126, 8, 0x0C0, 0x10, 17, 1),
PIN_FIELD_BASE(127, 127, 8, 0x0C0, 0x10, 21, 1),
PIN_FIELD_BASE(128, 128, 8, 0x0C0, 0x10, 25, 1),
PIN_FIELD_BASE(129, 129, 8, 0x0C0, 0x10, 29, 1),
PIN_FIELD_BASE(130, 130, 8, 0x0D0, 0x10, 1, 1),
PIN_FIELD_BASE(131, 131, 8, 0x0D0, 0x10, 5, 1),
PIN_FIELD_BASE(132, 132, 8, 0x0D0, 0x10, 9, 1),
PIN_FIELD_BASE(133, 133, 8, 0x0D0, 0x10, 13, 1),
};
static const struct mtk_pin_reg_calc mt8183_reg_cals[PINCTRL_PIN_REG_MAX] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8183_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8183_pin_dir_range),
[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8183_pin_di_range),
[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8183_pin_do_range),
[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8183_pin_smt_range),
[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8183_pin_ies_range),
[PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt8183_pin_pullen_range),
[PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt8183_pin_pullsel_range),
[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8183_pin_drv_range),
[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt8183_pin_pupd_range),
[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8183_pin_r0_range),
[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8183_pin_r1_range),
};
static const char * const mt8183_pinctrl_register_base_names[] = {
"iocfg0", "iocfg1", "iocfg2", "iocfg3", "iocfg4", "iocfg5",
"iocfg6", "iocfg7", "iocfg8",
};
static const struct mtk_eint_hw mt8183_eint_hw = {
.port_mask = 7,
.ports = 6,
.ap_num = 212,
.db_cnt = 13,
};
static const struct mtk_pin_soc mt8183_data = {
.reg_cal = mt8183_reg_cals,
.pins = mtk_pins_mt8183,
.npins = ARRAY_SIZE(mtk_pins_mt8183),
.ngrps = ARRAY_SIZE(mtk_pins_mt8183),
.eint_hw = &mt8183_eint_hw,
.gpio_m = 0,
.ies_present = true,
.base_names = mt8183_pinctrl_register_base_names,
.nbase_names = ARRAY_SIZE(mt8183_pinctrl_register_base_names),
.bias_disable_set = mtk_pinconf_bias_disable_set_rev1,
.bias_disable_get = mtk_pinconf_bias_disable_get_rev1,
.bias_set = mtk_pinconf_bias_set_rev1,
.bias_get = mtk_pinconf_bias_get_rev1,
.drive_set = mtk_pinconf_drive_set_rev1,
.drive_get = mtk_pinconf_drive_get_rev1,
.adv_pull_get = mtk_pinconf_adv_pull_get,
.adv_pull_set = mtk_pinconf_adv_pull_set,
};
static const struct of_device_id mt8183_pinctrl_of_match[] = {
{ .compatible = "mediatek,mt8183-pinctrl", },
{ }
};
static int mt8183_pinctrl_probe(struct platform_device *pdev)
{
return mtk_paris_pinctrl_probe(pdev, &mt8183_data);
}
static struct platform_driver mt8183_pinctrl_driver = {
.driver = {
.name = "mt8183-pinctrl",
.of_match_table = mt8183_pinctrl_of_match,
},
.probe = mt8183_pinctrl_probe,
};
static int __init mt8183_pinctrl_init(void)
{
return platform_driver_register(&mt8183_pinctrl_driver);
}
arch_initcall(mt8183_pinctrl_init);

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drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2018 MediaTek Inc.
*
* Author: Sean Wang <sean.wang@mediatek.com>
*
*/
#include <linux/device.h>
#include <linux/err.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/of_irq.h>
#include "mtk-eint.h"
#include "pinctrl-mtk-common-v2.h"
/**
* struct mtk_drive_desc - the structure that holds the information
* of the driving current
* @min: the minimum current of this group
* @max: the maximum current of this group
* @step: the step current of this group
* @scal: the weight factor
*
* formula: output = ((input) / step - 1) * scal
*/
struct mtk_drive_desc {
u8 min;
u8 max;
u8 step;
u8 scal;
};
/* The groups of drive strength */
const struct mtk_drive_desc mtk_drive[] = {
[DRV_GRP0] = { 4, 16, 4, 1 },
[DRV_GRP1] = { 4, 16, 4, 2 },
[DRV_GRP2] = { 2, 8, 2, 1 },
[DRV_GRP3] = { 2, 8, 2, 2 },
[DRV_GRP4] = { 2, 16, 2, 1 },
};
static void mtk_w32(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 val)
{
writel_relaxed(val, pctl->base[i] + reg);
}
static u32 mtk_r32(struct mtk_pinctrl *pctl, u8 i, u32 reg)
{
return readl_relaxed(pctl->base[i] + reg);
}
void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set)
{
u32 val;
val = mtk_r32(pctl, i, reg);
val &= ~mask;
val |= set;
mtk_w32(pctl, i, reg, val);
}
static int mtk_hw_pin_field_lookup(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc,
int field, struct mtk_pin_field *pfd)
{
const struct mtk_pin_field_calc *c, *e;
const struct mtk_pin_reg_calc *rc;
u32 bits;
if (hw->soc->reg_cal && hw->soc->reg_cal[field].range) {
rc = &hw->soc->reg_cal[field];
} else {
dev_dbg(hw->dev,
"Not support field %d for pin %d (%s)\n",
field, desc->number, desc->name);
return -ENOTSUPP;
}
c = rc->range;
e = c + rc->nranges;
while (c < e) {
if (desc->number >= c->s_pin && desc->number <= c->e_pin)
break;
c++;
}
if (c >= e) {
dev_dbg(hw->dev, "Not support field %d for pin = %d (%s)\n",
field, desc->number, desc->name);
return -ENOTSUPP;
}
if (c->i_base > hw->nbase - 1) {
dev_err(hw->dev,
"Invalid base for field %d for pin = %d (%s)\n",
field, desc->number, desc->name);
return -EINVAL;
}
/* Calculated bits as the overall offset the pin is located at,
* if c->fixed is held, that determines the all the pins in the
* range use the same field with the s_pin.
*/
bits = c->fixed ? c->s_bit : c->s_bit +
(desc->number - c->s_pin) * (c->x_bits);
/* Fill pfd from bits. For example 32-bit register applied is assumed
* when c->sz_reg is equal to 32.
*/
pfd->index = c->i_base;
pfd->offset = c->s_addr + c->x_addrs * (bits / c->sz_reg);
pfd->bitpos = bits % c->sz_reg;
pfd->mask = (1 << c->x_bits) - 1;
/* pfd->next is used for indicating that bit wrapping-around happens
* which requires the manipulation for bit 0 starting in the next
* register to form the complete field read/write.
*/
pfd->next = pfd->bitpos + c->x_bits > c->sz_reg ? c->x_addrs : 0;
return 0;
}
static int mtk_hw_pin_field_get(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc,
int field, struct mtk_pin_field *pfd)
{
if (field < 0 || field >= PINCTRL_PIN_REG_MAX) {
dev_err(hw->dev, "Invalid Field %d\n", field);
return -EINVAL;
}
return mtk_hw_pin_field_lookup(hw, desc, field, pfd);
}
static void mtk_hw_bits_part(struct mtk_pin_field *pf, int *h, int *l)
{
*l = 32 - pf->bitpos;
*h = get_count_order(pf->mask) - *l;
}
static void mtk_hw_write_cross_field(struct mtk_pinctrl *hw,
struct mtk_pin_field *pf, int value)
{
int nbits_l, nbits_h;
mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
mtk_rmw(hw, pf->index, pf->offset, pf->mask << pf->bitpos,
(value & pf->mask) << pf->bitpos);
mtk_rmw(hw, pf->index, pf->offset + pf->next, BIT(nbits_h) - 1,
(value & pf->mask) >> nbits_l);
}
static void mtk_hw_read_cross_field(struct mtk_pinctrl *hw,
struct mtk_pin_field *pf, int *value)
{
int nbits_l, nbits_h, h, l;
mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
l = (mtk_r32(hw, pf->index, pf->offset)
>> pf->bitpos) & (BIT(nbits_l) - 1);
h = (mtk_r32(hw, pf->index, pf->offset + pf->next))
& (BIT(nbits_h) - 1);
*value = (h << nbits_l) | l;
}
int mtk_hw_set_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
int field, int value)
{
struct mtk_pin_field pf;
int err;
err = mtk_hw_pin_field_get(hw, desc, field, &pf);
if (err)
return err;
if (!pf.next)
mtk_rmw(hw, pf.index, pf.offset, pf.mask << pf.bitpos,
(value & pf.mask) << pf.bitpos);
else
mtk_hw_write_cross_field(hw, &pf, value);
return 0;
}
int mtk_hw_get_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
int field, int *value)
{
struct mtk_pin_field pf;
int err;
err = mtk_hw_pin_field_get(hw, desc, field, &pf);
if (err)
return err;
if (!pf.next)
*value = (mtk_r32(hw, pf.index, pf.offset)
>> pf.bitpos) & pf.mask;
else
mtk_hw_read_cross_field(hw, &pf, value);
return 0;
}
static int mtk_xt_find_eint_num(struct mtk_pinctrl *hw, unsigned long eint_n)
{
const struct mtk_pin_desc *desc;
int i = 0;
desc = (const struct mtk_pin_desc *)hw->soc->pins;
while (i < hw->soc->npins) {
if (desc[i].eint.eint_n == eint_n)
return desc[i].number;
i++;
}
return EINT_NA;
}
static int mtk_xt_get_gpio_n(void *data, unsigned long eint_n,
unsigned int *gpio_n,
struct gpio_chip **gpio_chip)
{
struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
const struct mtk_pin_desc *desc;
desc = (const struct mtk_pin_desc *)hw->soc->pins;
*gpio_chip = &hw->chip;
/* Be greedy to guess first gpio_n is equal to eint_n */
if (desc[eint_n].eint.eint_n == eint_n)
*gpio_n = eint_n;
else
*gpio_n = mtk_xt_find_eint_num(hw, eint_n);
return *gpio_n == EINT_NA ? -EINVAL : 0;
}
static int mtk_xt_get_gpio_state(void *data, unsigned long eint_n)
{
struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
const struct mtk_pin_desc *desc;
struct gpio_chip *gpio_chip;
unsigned int gpio_n;
int value, err;
err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip);
if (err)
return err;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n];
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
if (err)
return err;
return !!value;
}
static int mtk_xt_set_gpio_as_eint(void *data, unsigned long eint_n)
{
struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
const struct mtk_pin_desc *desc;
struct gpio_chip *gpio_chip;
unsigned int gpio_n;
int err;
err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip);
if (err)
return err;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n];
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
desc->eint.eint_m);
if (err)
return err;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, MTK_INPUT);
if (err)
return err;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, MTK_ENABLE);
if (err)
return err;
return 0;
}
static const struct mtk_eint_xt mtk_eint_xt = {
.get_gpio_n = mtk_xt_get_gpio_n,
.get_gpio_state = mtk_xt_get_gpio_state,
.set_gpio_as_eint = mtk_xt_set_gpio_as_eint,
};
int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct resource *res;
if (!IS_ENABLED(CONFIG_EINT_MTK))
return 0;
if (!of_property_read_bool(np, "interrupt-controller"))
return -ENODEV;
hw->eint = devm_kzalloc(hw->dev, sizeof(*hw->eint), GFP_KERNEL);
if (!hw->eint)
return -ENOMEM;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "eint");
if (!res) {
dev_err(&pdev->dev, "Unable to get eint resource\n");
return -ENODEV;
}
hw->eint->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(hw->eint->base))
return PTR_ERR(hw->eint->base);
hw->eint->irq = irq_of_parse_and_map(np, 0);
if (!hw->eint->irq)
return -EINVAL;
if (!hw->soc->eint_hw)
return -ENODEV;
hw->eint->dev = &pdev->dev;
hw->eint->hw = hw->soc->eint_hw;
hw->eint->pctl = hw;
hw->eint->gpio_xlate = &mtk_eint_xt;
return mtk_eint_do_init(hw->eint);
}
/* Revision 0 */
int mtk_pinconf_bias_disable_set(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc)
{
int err;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU,
MTK_DISABLE);
if (err)
return err;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD,
MTK_DISABLE);
if (err)
return err;
return 0;
}
int mtk_pinconf_bias_disable_get(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, int *res)
{
int v, v2;
int err;
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &v);
if (err)
return err;
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &v2);
if (err)
return err;
if (v == MTK_ENABLE || v2 == MTK_ENABLE)
return -EINVAL;
*res = 1;
return 0;
}
int mtk_pinconf_bias_set(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, bool pullup)
{
int err, arg;
arg = pullup ? 1 : 2;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, arg & 1);
if (err)
return err;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD,
!!(arg & 2));
if (err)
return err;
return 0;
}
int mtk_pinconf_bias_get(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, bool pullup, int *res)
{
int reg, err, v;
reg = pullup ? PINCTRL_PIN_REG_PU : PINCTRL_PIN_REG_PD;
err = mtk_hw_get_value(hw, desc, reg, &v);
if (err)
return err;
if (!v)
return -EINVAL;
*res = 1;
return 0;
}
/* Revision 1 */
int mtk_pinconf_bias_disable_set_rev1(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc)
{
int err;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN,
MTK_DISABLE);
if (err)
return err;
return 0;
}
int mtk_pinconf_bias_disable_get_rev1(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, int *res)
{
int v, err;
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, &v);
if (err)
return err;
if (v == MTK_ENABLE)
return -EINVAL;
*res = 1;
return 0;
}
int mtk_pinconf_bias_set_rev1(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, bool pullup)
{
int err, arg;
arg = pullup ? MTK_PULLUP : MTK_PULLDOWN;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN,
MTK_ENABLE);
if (err)
return err;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, arg);
if (err)
return err;
return 0;
}
int mtk_pinconf_bias_get_rev1(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, bool pullup,
int *res)
{
int err, v;
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, &v);
if (err)
return err;
if (v == MTK_DISABLE)
return -EINVAL;
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, &v);
if (err)
return err;
if (pullup ^ (v == MTK_PULLUP))
return -EINVAL;
*res = 1;
return 0;
}
/* Revision 0 */
int mtk_pinconf_drive_set(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, u32 arg)
{
const struct mtk_drive_desc *tb;
int err = -ENOTSUPP;
tb = &mtk_drive[desc->drv_n];
/* 4mA when (e8, e4) = (0, 0)
* 8mA when (e8, e4) = (0, 1)
* 12mA when (e8, e4) = (1, 0)
* 16mA when (e8, e4) = (1, 1)
*/
if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) {
arg = (arg / tb->step - 1) * tb->scal;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_E4,
arg & 0x1);
if (err)
return err;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_E8,
(arg & 0x2) >> 1);
if (err)
return err;
}
return err;
}
int mtk_pinconf_drive_get(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, int *val)
{
const struct mtk_drive_desc *tb;
int err, val1, val2;
tb = &mtk_drive[desc->drv_n];
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_E4, &val1);
if (err)
return err;
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_E8, &val2);
if (err)
return err;
/* 4mA when (e8, e4) = (0, 0); 8mA when (e8, e4) = (0, 1)
* 12mA when (e8, e4) = (1, 0); 16mA when (e8, e4) = (1, 1)
*/
*val = (((val2 << 1) + val1) / tb->scal + 1) * tb->step;
return 0;
}
/* Revision 1 */
int mtk_pinconf_drive_set_rev1(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, u32 arg)
{
const struct mtk_drive_desc *tb;
int err = -ENOTSUPP;
tb = &mtk_drive[desc->drv_n];
if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) {
arg = (arg / tb->step - 1) * tb->scal;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV,
arg);
if (err)
return err;
}
return err;
}
int mtk_pinconf_drive_get_rev1(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, int *val)
{
const struct mtk_drive_desc *tb;
int err, val1;
tb = &mtk_drive[desc->drv_n];
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV, &val1);
if (err)
return err;
*val = ((val1 & 0x7) / tb->scal + 1) * tb->step;
return 0;
}
int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, bool pullup,
u32 arg)
{
int err;
/* 10K off & 50K (75K) off, when (R0, R1) = (0, 0);
* 10K off & 50K (75K) on, when (R0, R1) = (0, 1);
* 10K on & 50K (75K) off, when (R0, R1) = (1, 0);
* 10K on & 50K (75K) on, when (R0, R1) = (1, 1)
*/
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R0, arg & 1);
if (err)
return 0;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R1,
!!(arg & 2));
if (err)
return 0;
arg = pullup ? 0 : 1;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PUPD, arg);
/* If PUPD register is not supported for that pin, let's fallback to
* general bias control.
*/
if (err == -ENOTSUPP) {
if (hw->soc->bias_set) {
err = hw->soc->bias_set(hw, desc, pullup);
if (err)
return err;
} else {
return -ENOTSUPP;
}
}
return err;
}
int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, bool pullup,
u32 *val)
{
u32 t, t2;
int err;
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PUPD, &t);
/* If PUPD register is not supported for that pin, let's fallback to
* general bias control.
*/
if (err == -ENOTSUPP) {
if (hw->soc->bias_get) {
err = hw->soc->bias_get(hw, desc, pullup, val);
if (err)
return err;
} else {
return -ENOTSUPP;
}
} else {
/* t == 0 supposes PULLUP for the customized PULL setup */
if (err)
return err;
if (pullup ^ !t)
return -EINVAL;
}
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R0, &t);
if (err)
return err;
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R1, &t2);
if (err)
return err;
*val = (t | t2 << 1) & 0x7;
return 0;
}

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drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2018 MediaTek Inc.
*
* Author: Sean Wang <sean.wang@mediatek.com>
*
*/
#ifndef __PINCTRL_MTK_COMMON_V2_H
#define __PINCTRL_MTK_COMMON_V2_H
#define MTK_INPUT 0
#define MTK_OUTPUT 1
#define MTK_DISABLE 0
#define MTK_ENABLE 1
#define MTK_PULLDOWN 0
#define MTK_PULLUP 1
#define EINT_NA -1
#define PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, \
_s_bit, _x_bits, _sz_reg, _fixed) { \
.s_pin = _s_pin, \
.e_pin = _e_pin, \
.i_base = _i_base, \
.s_addr = _s_addr, \
.x_addrs = _x_addrs, \
.s_bit = _s_bit, \
.x_bits = _x_bits, \
.sz_reg = _sz_reg, \
.fixed = _fixed, \
}
#define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
_x_bits, 32, 0)
#define PINS_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
_x_bits, 32, 1)
/* List these attributes which could be modified for the pin */
enum {
PINCTRL_PIN_REG_MODE,
PINCTRL_PIN_REG_DIR,
PINCTRL_PIN_REG_DI,
PINCTRL_PIN_REG_DO,
PINCTRL_PIN_REG_SR,
PINCTRL_PIN_REG_SMT,
PINCTRL_PIN_REG_PD,
PINCTRL_PIN_REG_PU,
PINCTRL_PIN_REG_E4,
PINCTRL_PIN_REG_E8,
PINCTRL_PIN_REG_TDSEL,
PINCTRL_PIN_REG_RDSEL,
PINCTRL_PIN_REG_DRV,
PINCTRL_PIN_REG_PUPD,
PINCTRL_PIN_REG_R0,
PINCTRL_PIN_REG_R1,
PINCTRL_PIN_REG_IES,
PINCTRL_PIN_REG_PULLEN,
PINCTRL_PIN_REG_PULLSEL,
PINCTRL_PIN_REG_MAX,
};
/* Group the pins by the driving current */
enum {
DRV_FIXED,
DRV_GRP0,
DRV_GRP1,
DRV_GRP2,
DRV_GRP3,
DRV_GRP4,
DRV_GRP_MAX,
};
static const char * const mtk_default_register_base_names[] = {
"base",
};
/* struct mtk_pin_field - the structure that holds the information of the field
* used to describe the attribute for the pin
* @base: the index pointing to the entry in base address list
* @offset: the register offset relative to the base address
* @mask: the mask used to filter out the field from the register
* @bitpos: the start bit relative to the register
* @next: the indication that the field would be extended to the
next register
*/
struct mtk_pin_field {
u8 index;
u32 offset;
u32 mask;
u8 bitpos;
u8 next;
};
/* struct mtk_pin_field_calc - the structure that holds the range providing
* the guide used to look up the relevant field
* @s_pin: the start pin within the range
* @e_pin: the end pin within the range
* @i_base: the index pointing to the entry in base address list
* @s_addr: the start address for the range
* @x_addrs: the address distance between two consecutive registers
* within the range
* @s_bit: the start bit for the first register within the range
* @x_bits: the bit distance between two consecutive pins within
* the range
* @sz_reg: the size of bits in a register
* @fixed: the consecutive pins share the same bits with the 1st
* pin
*/
struct mtk_pin_field_calc {
u16 s_pin;
u16 e_pin;
u8 i_base;
u32 s_addr;
u8 x_addrs;
u8 s_bit;
u8 x_bits;
u8 sz_reg;
u8 fixed;
};
/* struct mtk_pin_reg_calc - the structure that holds all ranges used to
* determine which register the pin would make use of
* for certain pin attribute.
* @range: the start address for the range
* @nranges: the number of items in the range
*/
struct mtk_pin_reg_calc {
const struct mtk_pin_field_calc *range;
unsigned int nranges;
};
/**
* struct mtk_func_desc - the structure that providing information
* all the funcs for this pin
* @name: the name of function
* @muxval: the mux to the function
*/
struct mtk_func_desc {
const char *name;
u8 muxval;
};
/**
* struct mtk_eint_desc - the structure that providing information
* for eint data per pin
* @eint_m: the eint mux for this pin
* @eitn_n: the eint number for this pin
*/
struct mtk_eint_desc {
u8 eint_m;
u16 eint_n;
};
/**
* struct mtk_pin_desc - the structure that providing information
* for each pin of chips
* @number: unique pin number from the global pin number space
* @name: name for this pin
* @eint: the eint data for this pin
* @drv_n: the index with the driving group
* @funcs: all available functions for this pins (only used in
* those drivers compatible to pinctrl-mtk-common.c-like
* ones)
*/
struct mtk_pin_desc {
unsigned int number;
const char *name;
struct mtk_eint_desc eint;
u8 drv_n;
struct mtk_func_desc *funcs;
};
struct mtk_pinctrl_group {
const char *name;
unsigned long config;
unsigned pin;
};
struct mtk_pinctrl;
/* struct mtk_pin_soc - the structure that holds SoC-specific data */
struct mtk_pin_soc {
const struct mtk_pin_reg_calc *reg_cal;
const struct mtk_pin_desc *pins;
unsigned int npins;
const struct group_desc *grps;
unsigned int ngrps;
const struct function_desc *funcs;
unsigned int nfuncs;
const struct mtk_eint_regs *eint_regs;
const struct mtk_eint_hw *eint_hw;
/* Specific parameters per SoC */
u8 gpio_m;
bool ies_present;
const char * const *base_names;
unsigned int nbase_names;
/* Specific pinconfig operations */
int (*bias_disable_set)(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc);
int (*bias_disable_get)(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, int *res);
int (*bias_set)(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, bool pullup);
int (*bias_get)(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, bool pullup, int *res);
int (*drive_set)(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, u32 arg);
int (*drive_get)(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, int *val);
int (*adv_pull_set)(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, bool pullup,
u32 arg);
int (*adv_pull_get)(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, bool pullup,
u32 *val);
/* Specific driver data */
void *driver_data;
};
struct mtk_pinctrl {
struct pinctrl_dev *pctrl;
void __iomem **base;
u8 nbase;
struct device *dev;
struct gpio_chip chip;
const struct mtk_pin_soc *soc;
struct mtk_eint *eint;
struct mtk_pinctrl_group *groups;
const char **grp_names;
};
void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set);
int mtk_hw_set_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
int field, int value);
int mtk_hw_get_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
int field, int *value);
int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev);
int mtk_pinconf_bias_disable_set(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc);
int mtk_pinconf_bias_disable_get(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, int *res);
int mtk_pinconf_bias_set(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, bool pullup);
int mtk_pinconf_bias_get(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, bool pullup,
int *res);
int mtk_pinconf_bias_disable_set_rev1(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc);
int mtk_pinconf_bias_disable_get_rev1(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc,
int *res);
int mtk_pinconf_bias_set_rev1(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, bool pullup);
int mtk_pinconf_bias_get_rev1(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, bool pullup,
int *res);
int mtk_pinconf_drive_set(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, u32 arg);
int mtk_pinconf_drive_get(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, int *val);
int mtk_pinconf_drive_set_rev1(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, u32 arg);
int mtk_pinconf_drive_get_rev1(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, int *val);
int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, bool pullup,
u32 arg);
int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, bool pullup,
u32 *val);
#endif /* __PINCTRL_MTK_COMMON_V2_H */

1916
drivers/pinctrl/mediatek/pinctrl-mtk-mt8183.h Normal file
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drivers/pinctrl/mediatek/pinctrl-paris.c Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* MediaTek Pinctrl Paris Driver, which implement the vendor per-pin
* bindings for MediaTek SoC.
*
* Copyright (C) 2018 MediaTek Inc.
* Author: Sean Wang <sean.wang@mediatek.com>
* Zhiyong Tao <zhiyong.tao@mediatek.com>
* Hongzhou.Yang <hongzhou.yang@mediatek.com>
*/
#include <dt-bindings/pinctrl/mt65xx.h>
#include "pinctrl-paris.h"
#define PINCTRL_PINCTRL_DEV KBUILD_MODNAME
/* Custom pinconf parameters */
#define MTK_PIN_CONFIG_TDSEL (PIN_CONFIG_END + 1)
#define MTK_PIN_CONFIG_RDSEL (PIN_CONFIG_END + 2)
#define MTK_PIN_CONFIG_PU_ADV (PIN_CONFIG_END + 3)
#define MTK_PIN_CONFIG_PD_ADV (PIN_CONFIG_END + 4)
static const struct pinconf_generic_params mtk_custom_bindings[] = {
{"mediatek,tdsel", MTK_PIN_CONFIG_TDSEL, 0},
{"mediatek,rdsel", MTK_PIN_CONFIG_RDSEL, 0},
{"mediatek,pull-up-adv", MTK_PIN_CONFIG_PU_ADV, 1},
{"mediatek,pull-down-adv", MTK_PIN_CONFIG_PD_ADV, 1},
};
#ifdef CONFIG_DEBUG_FS
static const struct pin_config_item mtk_conf_items[] = {
PCONFDUMP(MTK_PIN_CONFIG_TDSEL, "tdsel", NULL, true),
PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true),
PCONFDUMP(MTK_PIN_CONFIG_PU_ADV, "pu-adv", NULL, true),
PCONFDUMP(MTK_PIN_CONFIG_PD_ADV, "pd-adv", NULL, true),
};
#endif
static const char * const mtk_gpio_functions[] = {
"func0", "func1", "func2", "func3",
"func4", "func5", "func6", "func7",
"func8", "func9", "func10", "func11",
"func12", "func13", "func14", "func15",
};
static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int pin)
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
const struct mtk_pin_desc *desc;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
hw->soc->gpio_m);
}
static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int pin, bool input)
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
const struct mtk_pin_desc *desc;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
/* hardware would take 0 as input direction */
return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !input);
}
static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
unsigned int pin, unsigned long *config)
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
u32 param = pinconf_to_config_param(*config);
int val, val2, err, reg, ret = 1;
const struct mtk_pin_desc *desc;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
if (hw->soc->bias_disable_get) {
err = hw->soc->bias_disable_get(hw, desc, &ret);
if (err)
return err;
} else {
return -ENOTSUPP;
}
break;
case PIN_CONFIG_BIAS_PULL_UP:
if (hw->soc->bias_get) {
err = hw->soc->bias_get(hw, desc, 1, &ret);
if (err)
return err;
} else {
return -ENOTSUPP;
}
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
if (hw->soc->bias_get) {
err = hw->soc->bias_get(hw, desc, 0, &ret);
if (err)
return err;
} else {
return -ENOTSUPP;
}
break;
case PIN_CONFIG_SLEW_RATE:
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SR, &val);
if (err)
return err;
if (!val)
return -EINVAL;
break;
case PIN_CONFIG_INPUT_ENABLE:
case PIN_CONFIG_OUTPUT_ENABLE:
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &val);
if (err)
return err;
/* HW takes input mode as zero; output mode as non-zero */
if ((val && param == PIN_CONFIG_INPUT_ENABLE) ||
(!val && param == PIN_CONFIG_OUTPUT_ENABLE))
return -EINVAL;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &val);
if (err)
return err;
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SMT, &val2);
if (err)
return err;
if (val || !val2)
return -EINVAL;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
if (hw->soc->drive_get) {
err = hw->soc->drive_get(hw, desc, &ret);
if (err)
return err;
} else {
err = -ENOTSUPP;
}
break;
case MTK_PIN_CONFIG_TDSEL:
case MTK_PIN_CONFIG_RDSEL:
reg = (param == MTK_PIN_CONFIG_TDSEL) ?
PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
err = mtk_hw_get_value(hw, desc, reg, &val);
if (err)
return err;
ret = val;
break;
case MTK_PIN_CONFIG_PU_ADV:
case MTK_PIN_CONFIG_PD_ADV:
if (hw->soc->adv_pull_get) {
bool pullup;
pullup = param == MTK_PIN_CONFIG_PU_ADV;
err = hw->soc->adv_pull_get(hw, desc, pullup, &ret);
if (err)
return err;
} else {
return -ENOTSUPP;
}
break;
default:
return -ENOTSUPP;
}
*config = pinconf_to_config_packed(param, ret);
return 0;
}
static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
enum pin_config_param param,
enum pin_config_param arg)
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
const struct mtk_pin_desc *desc;
int err = 0;
u32 reg;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
switch ((u32)param) {
case PIN_CONFIG_BIAS_DISABLE:
if (hw->soc->bias_disable_set) {
err = hw->soc->bias_disable_set(hw, desc);
if (err)
return err;
} else {
return -ENOTSUPP;
}
break;
case PIN_CONFIG_BIAS_PULL_UP:
if (hw->soc->bias_set) {
err = hw->soc->bias_set(hw, desc, 1);
if (err)
return err;
} else {
return -ENOTSUPP;
}
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
if (hw->soc->bias_set) {
err = hw->soc->bias_set(hw, desc, 0);
if (err)
return err;
} else {
return -ENOTSUPP;
}
break;
case PIN_CONFIG_OUTPUT_ENABLE:
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,
MTK_DISABLE);
if (err)
goto err;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
MTK_OUTPUT);
if (err)
goto err;
break;
case PIN_CONFIG_INPUT_ENABLE:
if (hw->soc->ies_present) {
mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_IES,
MTK_ENABLE);
}
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
MTK_INPUT);
if (err)
goto err;
break;
case PIN_CONFIG_SLEW_RATE:
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SR,
arg);
if (err)
goto err;
break;
case PIN_CONFIG_OUTPUT:
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
MTK_OUTPUT);
if (err)
goto err;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO,
arg);
if (err)
goto err;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
/* arg = 1: Input mode & SMT enable ;
* arg = 0: Output mode & SMT disable
*/
arg = arg ? 2 : 1;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
arg & 1);
if (err)
goto err;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,
!!(arg & 2));
if (err)
goto err;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
if (hw->soc->drive_set) {
err = hw->soc->drive_set(hw, desc, arg);
if (err)
return err;
} else {
return -ENOTSUPP;
}
break;
case MTK_PIN_CONFIG_TDSEL:
case MTK_PIN_CONFIG_RDSEL:
reg = (param == MTK_PIN_CONFIG_TDSEL) ?
PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
err = mtk_hw_set_value(hw, desc, reg, arg);
if (err)
goto err;
break;
case MTK_PIN_CONFIG_PU_ADV:
case MTK_PIN_CONFIG_PD_ADV:
if (hw->soc->adv_pull_set) {
bool pullup;
pullup = param == MTK_PIN_CONFIG_PU_ADV;
err = hw->soc->adv_pull_set(hw, desc, pullup,
arg);
if (err)
return err;
} else {
return -ENOTSUPP;
}
break;
default:
err = -ENOTSUPP;
}
err:
return err;
}
static struct mtk_pinctrl_group *
mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *hw, u32 pin)
{
int i;
for (i = 0; i < hw->soc->ngrps; i++) {
struct mtk_pinctrl_group *grp = hw->groups + i;
if (grp->pin == pin)
return grp;
}
return NULL;
}
static const struct mtk_func_desc *
mtk_pctrl_find_function_by_pin(struct mtk_pinctrl *hw, u32 pin_num, u32 fnum)
{
const struct mtk_pin_desc *pin = hw->soc->pins + pin_num;
const struct mtk_func_desc *func = pin->funcs;
while (func && func->name) {
if (func->muxval == fnum)
return func;
func++;
}
return NULL;
}
static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *hw, u32 pin_num,
u32 fnum)
{
int i;
for (i = 0; i < hw->soc->npins; i++) {
const struct mtk_pin_desc *pin = hw->soc->pins + i;
if (pin->number == pin_num) {
const struct mtk_func_desc *func = pin->funcs;
while (func && func->name) {
if (func->muxval == fnum)
return true;
func++;
}
break;
}
}
return false;
}
static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl,
u32 pin, u32 fnum,
struct mtk_pinctrl_group *grp,
struct pinctrl_map **map,
unsigned *reserved_maps,
unsigned *num_maps)
{
bool ret;
if (*num_maps == *reserved_maps)
return -ENOSPC;
(*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
(*map)[*num_maps].data.mux.group = grp->name;
ret = mtk_pctrl_is_function_valid(pctl, pin, fnum);
if (!ret) {
dev_err(pctl->dev, "invalid function %d on pin %d .\n",
fnum, pin);
return -EINVAL;
}
(*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum];
(*num_maps)++;
return 0;
}
static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
struct device_node *node,
struct pinctrl_map **map,
unsigned *reserved_maps,
unsigned *num_maps)
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
int num_pins, num_funcs, maps_per_pin, i, err;
struct mtk_pinctrl_group *grp;
unsigned int num_configs;
bool has_config = false;
unsigned long *configs;
u32 pinfunc, pin, func;
struct property *pins;
unsigned reserve = 0;
pins = of_find_property(node, "pinmux", NULL);
if (!pins) {
dev_err(hw->dev, "missing pins property in node %s .\n",
node->name);
return -EINVAL;
}
err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
&num_configs);
if (err)
return err;
if (num_configs)
has_config = true;
num_pins = pins->length / sizeof(u32);
num_funcs = num_pins;
maps_per_pin = 0;
if (num_funcs)
maps_per_pin++;
if (has_config && num_pins >= 1)
maps_per_pin++;
if (!num_pins || !maps_per_pin) {
err = -EINVAL;
goto exit;
}
reserve = num_pins * maps_per_pin;
err = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps,
reserve);
if (err < 0)
goto exit;
for (i = 0; i < num_pins; i++) {
err = of_property_read_u32_index(node, "pinmux", i, &pinfunc);
if (err)
goto exit;
pin = MTK_GET_PIN_NO(pinfunc);
func = MTK_GET_PIN_FUNC(pinfunc);
if (pin >= hw->soc->npins ||
func >= ARRAY_SIZE(mtk_gpio_functions)) {
dev_err(hw->dev, "invalid pins value.\n");
err = -EINVAL;
goto exit;
}
grp = mtk_pctrl_find_group_by_pin(hw, pin);
if (!grp) {
dev_err(hw->dev, "unable to match pin %d to group\n",
pin);
err = -EINVAL;
goto exit;
}
err = mtk_pctrl_dt_node_to_map_func(hw, pin, func, grp, map,
reserved_maps, num_maps);
if (err < 0)
goto exit;
if (has_config) {
err = pinctrl_utils_add_map_configs(pctldev, map,
reserved_maps,
num_maps,
grp->name,
configs,
num_configs,
PIN_MAP_TYPE_CONFIGS_GROUP);
if (err < 0)
goto exit;
}
}
err = 0;
exit:
kfree(configs);
return err;
}
static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np_config,
struct pinctrl_map **map,
unsigned *num_maps)
{
struct device_node *np;
unsigned reserved_maps;
int ret;
*map = NULL;
*num_maps = 0;
reserved_maps = 0;
for_each_child_of_node(np_config, np) {
ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map,
&reserved_maps,
num_maps);
if (ret < 0) {
pinctrl_utils_free_map(pctldev, *map, *num_maps);
of_node_put(np);
return ret;
}
}
return 0;
}
static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
return hw->soc->ngrps;
}
static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned group)
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
return hw->groups[group].name;
}
static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned group, const unsigned **pins,
unsigned *num_pins)
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
*pins = (unsigned *)&hw->groups[group].pin;
*num_pins = 1;
return 0;
}
static const struct pinctrl_ops mtk_pctlops = {
.dt_node_to_map = mtk_pctrl_dt_node_to_map,
.dt_free_map = pinctrl_utils_free_map,
.get_groups_count = mtk_pctrl_get_groups_count,
.get_group_name = mtk_pctrl_get_group_name,
.get_group_pins = mtk_pctrl_get_group_pins,
};
static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(mtk_gpio_functions);
}
static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev,
unsigned selector)
{
return mtk_gpio_functions[selector];
}
static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
unsigned function,
const char * const **groups,
unsigned * const num_groups)
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
*groups = hw->grp_names;
*num_groups = hw->soc->ngrps;
return 0;
}
static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
unsigned function,
unsigned group)
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
struct mtk_pinctrl_group *grp = hw->groups + group;
const struct mtk_func_desc *desc_func;
const struct mtk_pin_desc *desc;
bool ret;
ret = mtk_pctrl_is_function_valid(hw, grp->pin, function);
if (!ret) {
dev_err(hw->dev, "invalid function %d on group %d .\n",
function, group);
return -EINVAL;
}
desc_func = mtk_pctrl_find_function_by_pin(hw, grp->pin, function);
if (!desc_func)
return -EINVAL;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[grp->pin];
mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, desc_func->muxval);
return 0;
}
static const struct pinmux_ops mtk_pmxops = {
.get_functions_count = mtk_pmx_get_funcs_cnt,
.get_function_name = mtk_pmx_get_func_name,
.get_function_groups = mtk_pmx_get_func_groups,
.set_mux = mtk_pmx_set_mux,
.gpio_set_direction = mtk_pinmux_gpio_set_direction,
.gpio_request_enable = mtk_pinmux_gpio_request_enable,
};
static int mtk_pconf_group_get(struct pinctrl_dev *pctldev, unsigned group,
unsigned long *config)
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
*config = hw->groups[group].config;
return 0;
}
static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
unsigned long *configs, unsigned num_configs)
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
struct mtk_pinctrl_group *grp = &hw->groups[group];
int i, ret;
for (i = 0; i < num_configs; i++) {
ret = mtk_pinconf_set(pctldev, grp->pin,
pinconf_to_config_param(configs[i]),
pinconf_to_config_argument(configs[i]));
if (ret < 0)
return ret;
grp->config = configs[i];
}
return 0;
}
static const struct pinconf_ops mtk_confops = {
.pin_config_get = mtk_pinconf_get,
.pin_config_group_get = mtk_pconf_group_get,
.pin_config_group_set = mtk_pconf_group_set,
};
static struct pinctrl_desc mtk_desc = {
.name = PINCTRL_PINCTRL_DEV,
.pctlops = &mtk_pctlops,
.pmxops = &mtk_pmxops,
.confops = &mtk_confops,
.owner = THIS_MODULE,
};
static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
{
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
const struct mtk_pin_desc *desc;
int value, err;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &value);
if (err)
return err;
return !value;
}
static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio)
{
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
const struct mtk_pin_desc *desc;
int value, err;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
if (err)
return err;
return !!value;
}
static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
{
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
const struct mtk_pin_desc *desc;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value);
}
static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio)
{
return pinctrl_gpio_direction_input(chip->base + gpio);
}
static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
int value)
{
mtk_gpio_set(chip, gpio, value);
return pinctrl_gpio_direction_output(chip->base + gpio);
}
static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
{
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
const struct mtk_pin_desc *desc;
if (!hw->eint)
return -ENOTSUPP;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
if (desc->eint.eint_n == EINT_NA)
return -ENOTSUPP;
return mtk_eint_find_irq(hw->eint, desc->eint.eint_n);
}
static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
unsigned long config)
{
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
const struct mtk_pin_desc *desc;
u32 debounce;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
if (!hw->eint ||
pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE ||
desc->eint.eint_n == EINT_NA)
return -ENOTSUPP;
debounce = pinconf_to_config_argument(config);
return mtk_eint_set_debounce(hw->eint, desc->eint.eint_n, debounce);
}
static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np)
{
struct gpio_chip *chip = &hw->chip;
int ret;
chip->label = PINCTRL_PINCTRL_DEV;
chip->parent = hw->dev;
chip->request = gpiochip_generic_request;
chip->free = gpiochip_generic_free;
chip->get_direction = mtk_gpio_get_direction;
chip->direction_input = mtk_gpio_direction_input;
chip->direction_output = mtk_gpio_direction_output;
chip->get = mtk_gpio_get;
chip->set = mtk_gpio_set;
chip->to_irq = mtk_gpio_to_irq,
chip->set_config = mtk_gpio_set_config,
chip->base = -1;
chip->ngpio = hw->soc->npins;
chip->of_node = np;
chip->of_gpio_n_cells = 2;
ret = gpiochip_add_data(chip, hw);
if (ret < 0)
return ret;
return 0;
}
static int mtk_pctrl_build_state(struct platform_device *pdev)
{
struct mtk_pinctrl *hw = platform_get_drvdata(pdev);
int i;
/* Allocate groups */
hw->groups = devm_kmalloc_array(&pdev->dev, hw->soc->ngrps,
sizeof(*hw->groups), GFP_KERNEL);
if (!hw->groups)
return -ENOMEM;
/* We assume that one pin is one group, use pin name as group name. */
hw->grp_names = devm_kmalloc_array(&pdev->dev, hw->soc->ngrps,
sizeof(*hw->grp_names), GFP_KERNEL);
if (!hw->grp_names)
return -ENOMEM;
for (i = 0; i < hw->soc->npins; i++) {
const struct mtk_pin_desc *pin = hw->soc->pins + i;
struct mtk_pinctrl_group *group = hw->groups + i;
group->name = pin->name;
group->pin = pin->number;
hw->grp_names[i] = pin->name;
}
return 0;
}
int mtk_paris_pinctrl_probe(struct platform_device *pdev,
const struct mtk_pin_soc *soc)
{
struct pinctrl_pin_desc *pins;
struct mtk_pinctrl *hw;
struct resource *res;
int err, i;
hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
if (!hw)
return -ENOMEM;
platform_set_drvdata(pdev, hw);
hw->soc = soc;
hw->dev = &pdev->dev;
if (!hw->soc->nbase_names) {
dev_err(&pdev->dev,
"SoC should be assigned at least one register base\n");
return -EINVAL;
}
hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names,
sizeof(*hw->base), GFP_KERNEL);
if (IS_ERR(hw->base))
return PTR_ERR(hw->base);
for (i = 0; i < hw->soc->nbase_names; i++) {
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
hw->soc->base_names[i]);
if (!res) {
dev_err(&pdev->dev, "missing IO resource\n");
return -ENXIO;
}
hw->base[i] = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(hw->base[i]))
return PTR_ERR(hw->base[i]);
}
hw->nbase = hw->soc->nbase_names;
err = mtk_pctrl_build_state(pdev);
if (err) {
dev_err(&pdev->dev, "build state failed: %d\n", err);
return -EINVAL;
}
/* Copy from internal struct mtk_pin_desc to register to the core */
pins = devm_kmalloc_array(&pdev->dev, hw->soc->npins, sizeof(*pins),
GFP_KERNEL);
if (IS_ERR(pins))
return PTR_ERR(pins);
for (i = 0; i < hw->soc->npins; i++) {
pins[i].number = hw->soc->pins[i].number;
pins[i].name = hw->soc->pins[i].name;
}
/* Setup pins descriptions per SoC types */
mtk_desc.pins = (const struct pinctrl_pin_desc *)pins;
mtk_desc.npins = hw->soc->npins;
mtk_desc.num_custom_params = ARRAY_SIZE(mtk_custom_bindings);
mtk_desc.custom_params = mtk_custom_bindings;
#ifdef CONFIG_DEBUG_FS
mtk_desc.custom_conf_items = mtk_conf_items;
#endif
err = devm_pinctrl_register_and_init(&pdev->dev, &mtk_desc, hw,
&hw->pctrl);
if (err)
return err;
err = pinctrl_enable(hw->pctrl);
if (err)
return err;
err = mtk_build_eint(hw, pdev);
if (err)
dev_warn(&pdev->dev,
"Failed to add EINT, but pinctrl still can work\n");
/* Build gpiochip should be after pinctrl_enable is done */
err = mtk_build_gpiochip(hw, pdev->dev.of_node);
if (err) {
dev_err(&pdev->dev, "Failed to add gpio_chip\n");
return err;
}
platform_set_drvdata(pdev, hw);
return 0;
}

65
drivers/pinctrl/mediatek/pinctrl-paris.h Normal file
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@ -0,0 +1,65 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2018 MediaTek Inc.
*
* Author: Sean Wang <sean.wang@mediatek.com>
* Zhiyong Tao <zhiyong.tao@mediatek.com>
* Hongzhou.Yang <hongzhou.yang@mediatek.com>
*/
#ifndef __PINCTRL_PARIS_H
#define __PINCTRL_PARIS_H
#include <linux/gpio.h>
#include <linux/gpio/driver.h>
#include <linux/io.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include "../core.h"
#include "../pinconf.h"
#include "../pinctrl-utils.h"
#include "../pinmux.h"
#include "mtk-eint.h"
#include "pinctrl-mtk-common-v2.h"
#define MTK_RANGE(_a) { .range = (_a), .nranges = ARRAY_SIZE(_a), }
#define MTK_EINT_FUNCTION(_eintmux, _eintnum) \
{ \
.eint_m = _eintmux, \
.eint_n = _eintnum, \
}
#define MTK_FUNCTION(_val, _name) \
{ \
.muxval = _val, \
.name = _name, \
}
#define MTK_PIN(_number, _name, _eint, _drv_n, ...) { \
.number = _number, \
.name = _name, \
.eint = _eint, \
.drv_n = _drv_n, \
.funcs = (struct mtk_func_desc[]){ \
__VA_ARGS__, { } }, \
}
#define PINCTRL_PIN_GROUP(name, id) \
{ \
name, \
id##_pins, \
ARRAY_SIZE(id##_pins), \
id##_funcs, \
}
int mtk_paris_pinctrl_probe(struct platform_device *pdev,
const struct mtk_pin_soc *soc);
#endif /* __PINCTRL_PARIS_H */