New clock-ids+exports for two clocks, cleanup for some boilerplate code
for clocks we cannot really control from the kernel, but want to define separately to match the hardware-description (watchdog in secure-grf). Improvement in mmc phase calculation and cleanup of some rate defintions. -----BEGIN PGP SIGNATURE----- iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAl0Zz4EQHGhlaWtvQHNu dGVjaC5kZQAKCRDzpnnJnNEdgcXICACK8QHJcINYRl68As6BC0YzEVZnVmGwHBOx 8TlE34D/kUyXhfRBMu+PZZLiOzg14Qs9p8oZh8FPFQ5UtpBTH1TmdRnHtOxxDDXy jpEeH7jpsL5xcXoxvbHsyv+VqmVhEr2zNY6CjxeDEmanUmHwQqxZ71OzLuuq1ccR p7Nw1xjW/IHyIKEq5SomKHtulWawfQ7t6xN/IEgbwnAkZO+TzvZBqU44uUhTew2u 6OuBB5AKDTKPkDJjvM/pJzxdLWpxTXm2wgVPbHTJWcVR6MkMSP2V2RaZ0niTPF9q lp5Nf1/gWj5RMv8WTOqG/Qfy4+1OLBsApyZrsU5t00bTPTUAZ2nW =drW4 -----END PGP SIGNATURE----- Merge tag 'v5.3-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip Pull Rockchip clk driver updates from Heiko Stuebner: - New clock-ids+exports for two clocks - Cleanup for some boilerplate code for clocks we cannot really control from the kernel, but want to define separately to match the hardware-description (watchdog in secure-grf) - Improvement in mmc phase calculation and cleanup of some rate defintions * tag 'v5.3-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: export HDMIPHY clock on rk3228 clk: rockchip: add watchdog pclk on rk3328 clk: rockchip: add clock id for hdmi_phy special clock on rk3228 clk: rockchip: add clock id for watchdog pclk on rk3328 clk: rockchip: convert pclk_wdt boilerplat to new SGRF_GATE macro clk: rockchip: add a type from SGRF-controlled gate clocks clk: rockchip: Remove 48 MHz PLL rate from rk3288 clk: rockchip: add 1.464GHz cpu-clock rate to rk3228 clk: rockchip: Slightly more accurate math in rockchip_mmc_get_phase() clk: rockchip: Don't yell about bad mmc phases when getting clk: rockchip: Use clk_hw_get_rate() in MMC phase calculation
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commit
55692cedf3
@ -55,29 +55,27 @@ static unsigned long rockchip_mmc_recalc(struct clk_hw *hw,
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static int rockchip_mmc_get_phase(struct clk_hw *hw)
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{
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struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw);
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unsigned long rate = clk_get_rate(hw->clk);
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unsigned long rate = clk_hw_get_rate(hw);
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u32 raw_value;
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u16 degrees;
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u32 delay_num = 0;
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/* See the comment for rockchip_mmc_set_phase below */
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if (!rate) {
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pr_err("%s: invalid clk rate\n", __func__);
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if (!rate)
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return -EINVAL;
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}
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raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift);
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degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90;
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if (raw_value & ROCKCHIP_MMC_DELAY_SEL) {
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/* degrees/delaynum * 10000 */
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/* degrees/delaynum * 1000000 */
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unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) *
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36 * (rate / 1000000);
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36 * (rate / 10000);
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delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK);
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delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET;
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degrees += DIV_ROUND_CLOSEST(delay_num * factor, 10000);
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degrees += DIV_ROUND_CLOSEST(delay_num * factor, 1000000);
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}
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return degrees % 360;
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@ -86,7 +84,7 @@ static int rockchip_mmc_get_phase(struct clk_hw *hw)
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static int rockchip_mmc_set_phase(struct clk_hw *hw, int degrees)
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{
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struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw);
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unsigned long rate = clk_get_rate(hw->clk);
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unsigned long rate = clk_hw_get_rate(hw);
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u8 nineties, remainder;
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u8 delay_num;
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u32 raw_value;
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@ -803,6 +803,9 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
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GATE(ACLK_GIC, "aclk_gic", "aclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 12, GFLAGS),
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GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_pre", 0, PX30_CLKGATE_CON(13), 15, GFLAGS),
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/* aclk_dmac is controlled by sgrf_soc_con1[11]. */
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SGRF_GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_pre"),
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GATE(0, "hclk_bus_niu", "hclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 9, GFLAGS),
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GATE(0, "hclk_rom", "hclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 14, GFLAGS),
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GATE(HCLK_PDM, "hclk_pdm", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 1, GFLAGS),
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@ -966,7 +969,6 @@ static void __init px30_clk_init(struct device_node *np)
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{
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struct rockchip_clk_provider *ctx;
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void __iomem *reg_base;
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struct clk *clk;
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reg_base = of_iomap(np, 0);
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if (!reg_base) {
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@ -981,14 +983,6 @@ static void __init px30_clk_init(struct device_node *np)
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return;
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}
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/* aclk_dmac is controlled by sgrf_soc_con1[11]. */
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clk = clk_register_fixed_factor(NULL, "aclk_dmac", "aclk_bus_pre", 0, 1, 1);
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if (IS_ERR(clk))
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pr_warn("%s: could not register clock aclk_dmac: %ld\n",
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__func__, PTR_ERR(clk));
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else
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rockchip_clk_add_lookup(ctx, clk, ACLK_DMAC);
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rockchip_clk_register_plls(ctx, px30_pll_clks,
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ARRAY_SIZE(px30_pll_clks),
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PX30_GRF_SOC_STATUS0);
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@ -110,6 +110,7 @@ static struct rockchip_cpuclk_rate_table rk3228_cpuclk_rates[] __initdata = {
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RK3228_CPUCLK_RATE(1608000000, 1, 7),
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RK3228_CPUCLK_RATE(1512000000, 1, 7),
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RK3228_CPUCLK_RATE(1488000000, 1, 5),
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RK3228_CPUCLK_RATE(1464000000, 1, 5),
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RK3228_CPUCLK_RATE(1416000000, 1, 5),
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RK3228_CPUCLK_RATE(1392000000, 1, 5),
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RK3228_CPUCLK_RATE(1296000000, 1, 5),
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@ -255,7 +256,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
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RK2928_CLKGATE_CON(4), 0, GFLAGS),
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/* PD_MISC */
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MUX(0, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT,
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MUX(SCLK_HDMI_PHY, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT,
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RK2928_MISC_CON, 13, 1, MFLAGS),
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MUX(0, "usb480m_phy", mux_usb480m_phy_p, CLK_SET_RATE_PARENT,
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RK2928_MISC_CON, 14, 1, MFLAGS),
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@ -122,7 +122,6 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = {
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RK3066_PLL_RATE( 160000000, 1, 80, 12),
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RK3066_PLL_RATE( 157500000, 1, 105, 16),
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RK3066_PLL_RATE( 126000000, 1, 84, 16),
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RK3066_PLL_RATE( 48000000, 1, 64, 32),
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{ /* sentinel */ },
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};
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@ -776,6 +775,9 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
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GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(14), 11, GFLAGS),
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GATE(0, "pclk_alive_niu", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 12, GFLAGS),
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/* Watchdog pclk is controlled by RK3288_SGRF_SOC_CON0[1]. */
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SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_pd_alive"),
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/* pclk_pd_pmu gates */
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GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 0, GFLAGS),
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GATE(0, "pclk_intmem1", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 1, GFLAGS),
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@ -924,7 +926,6 @@ static struct syscore_ops rk3288_clk_syscore_ops = {
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static void __init rk3288_clk_init(struct device_node *np)
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{
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struct rockchip_clk_provider *ctx;
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struct clk *clk;
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rk3288_cru_base = of_iomap(np, 0);
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if (!rk3288_cru_base) {
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@ -939,14 +940,6 @@ static void __init rk3288_clk_init(struct device_node *np)
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return;
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}
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/* Watchdog pclk is controlled by RK3288_SGRF_SOC_CON0[1]. */
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clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_pd_alive", 0, 1, 1);
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if (IS_ERR(clk))
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pr_warn("%s: could not register clock pclk_wdt: %ld\n",
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__func__, PTR_ERR(clk));
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else
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rockchip_clk_add_lookup(ctx, clk, PCLK_WDT);
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rockchip_clk_register_plls(ctx, rk3288_pll_clks,
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ARRAY_SIZE(rk3288_pll_clks),
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RK3288_GRF_SOC_STATUS1);
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@ -800,6 +800,9 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
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GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 0, RK3328_CLKGATE_CON(17), 15, GFLAGS),
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GATE(0, "pclk_pmu", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(28), 3, GFLAGS),
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/* Watchdog pclk is controlled from the secure GRF */
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SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_bus"),
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GATE(PCLK_USB3PHY_OTG, "pclk_usb3phy_otg", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(28), 1, GFLAGS),
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GATE(PCLK_USB3PHY_PIPE, "pclk_usb3phy_pipe", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(28), 2, GFLAGS),
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GATE(PCLK_USB3_GRF, "pclk_usb3_grf", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 2, GFLAGS),
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@ -820,6 +820,9 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
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GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 2, GFLAGS),
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GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 1, GFLAGS),
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/* Watchdog pclk is controlled by sgrf_soc_con3[7]. */
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SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_pd_alive"),
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/*
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* pclk_vio gates
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* pclk_vio comes from the exactly same source as hclk_vio
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@ -871,7 +874,6 @@ static void __init rk3368_clk_init(struct device_node *np)
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{
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struct rockchip_clk_provider *ctx;
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void __iomem *reg_base;
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struct clk *clk;
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reg_base = of_iomap(np, 0);
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if (!reg_base) {
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@ -886,14 +888,6 @@ static void __init rk3368_clk_init(struct device_node *np)
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return;
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}
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/* Watchdog pclk is controlled by sgrf_soc_con3[7]. */
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clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_pd_alive", 0, 1, 1);
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if (IS_ERR(clk))
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pr_warn("%s: could not register clock pclk_wdt: %ld\n",
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__func__, PTR_ERR(clk));
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else
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rockchip_clk_add_lookup(ctx, clk, PCLK_WDT);
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rockchip_clk_register_plls(ctx, rk3368_pll_clks,
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ARRAY_SIZE(rk3368_pll_clks),
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RK3368_GRF_SOC_STATUS0);
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@ -1304,6 +1304,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
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GATE(PCLK_PMU_INTR_ARB, "pclk_pmu_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 9, GFLAGS),
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GATE(PCLK_SGRF, "pclk_sgrf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 10, GFLAGS),
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/* Watchdog pclk is controlled by RK3399 SECURE_GRF_SOC_CON3[8]. */
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SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_alive"),
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GATE(SCLK_MIPIDPHY_REF, "clk_mipidphy_ref", "xin24m", 0, RK3399_CLKGATE_CON(11), 14, GFLAGS),
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GATE(SCLK_DPHY_PLL, "clk_dphy_pll", "clk_mipidphy_ref", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 0, GFLAGS),
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@ -1531,7 +1534,6 @@ static void __init rk3399_clk_init(struct device_node *np)
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{
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struct rockchip_clk_provider *ctx;
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void __iomem *reg_base;
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struct clk *clk;
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reg_base = of_iomap(np, 0);
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if (!reg_base) {
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@ -1546,14 +1548,6 @@ static void __init rk3399_clk_init(struct device_node *np)
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return;
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}
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/* Watchdog pclk is controlled by RK3399 SECURE_GRF_SOC_CON3[8]. */
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clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_alive", 0, 1, 1);
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if (IS_ERR(clk))
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pr_warn("%s: could not register clock pclk_wdt: %ld\n",
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__func__, PTR_ERR(clk));
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else
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rockchip_clk_add_lookup(ctx, clk, PCLK_WDT);
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rockchip_clk_register_plls(ctx, rk3399_pll_clks,
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ARRAY_SIZE(rk3399_pll_clks), -1);
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@ -820,6 +820,10 @@ struct rockchip_clk_branch {
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.gate_offset = -1, \
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}
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/* SGRF clocks are only accessible from secure mode, so not controllable */
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#define SGRF_GATE(_id, cname, pname) \
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FACTOR(_id, cname, pname, 0, 1, 1)
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struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
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void __iomem *base, unsigned long nr_clks);
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void rockchip_clk_of_add_provider(struct device_node *np,
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@ -73,6 +73,7 @@
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#define SCLK_WIFI 141
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#define SCLK_OTGPHY0 142
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#define SCLK_OTGPHY1 143
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#define SCLK_HDMI_PHY 144
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/* dclk gates */
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#define DCLK_VOP 190
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@ -173,6 +173,7 @@
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#define PCLK_DCF 233
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#define PCLK_SARADC 234
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#define PCLK_ACODECPHY 235
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#define PCLK_WDT 236
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/* hclk gates */
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#define HCLK_PERI 308
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