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drm/amd/pp: Not call cgs interface to get display info

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DC/Non DC all will update display configuration
when the display state changed
No need to get display info through cgs interface

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rex Zhu 2018-03-27 13:32:02 +08:00 committed by Alex Deucher
parent d91ea4969b
commit 555fd70c59
13 changed files with 61 additions and 136 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/drm/amd/powerplay/amd_powerplay.c
View File

@ -54,6 +54,7 @@ static int amd_powerplay_create(struct amdgpu_device *adev)
hwmgr->chip_family = adev->family; hwmgr->chip_family = adev->family;
hwmgr->chip_id = adev->asic_type; hwmgr->chip_id = adev->asic_type;
hwmgr->feature_mask = amdgpu_pp_feature_mask; hwmgr->feature_mask = amdgpu_pp_feature_mask;
hwmgr->display_config = &adev->pm.pm_display_cfg;
adev->powerplay.pp_handle = hwmgr; adev->powerplay.pp_handle = hwmgr;
adev->powerplay.pp_funcs = &pp_dpm_funcs; adev->powerplay.pp_funcs = &pp_dpm_funcs;
return 0; return 0;

8
drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
View File

@ -265,13 +265,11 @@ int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
if (display_config == NULL) if (display_config == NULL)
return -EINVAL; return -EINVAL;
hwmgr->display_config = *display_config;
if (NULL != hwmgr->hwmgr_func->set_deep_sleep_dcefclk) if (NULL != hwmgr->hwmgr_func->set_deep_sleep_dcefclk)
hwmgr->hwmgr_func->set_deep_sleep_dcefclk(hwmgr, hwmgr->display_config.min_dcef_deep_sleep_set_clk); hwmgr->hwmgr_func->set_deep_sleep_dcefclk(hwmgr, display_config->min_dcef_deep_sleep_set_clk);
for (index = 0; index < hwmgr->display_config.num_path_including_non_display; index++) { for (index = 0; index < display_config->num_path_including_non_display; index++) {
if (hwmgr->display_config.displays[index].controller_id != 0) if (display_config->displays[index].controller_id != 0)
number_of_active_display++; number_of_active_display++;
} }

2
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
View File

@ -161,7 +161,7 @@ static int smu10_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input)
struct PP_Clocks clocks = {0}; struct PP_Clocks clocks = {0};
struct pp_display_clock_request clock_req; struct pp_display_clock_request clock_req;
clocks.dcefClock = hwmgr->display_config.min_dcef_set_clk; clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
clock_req.clock_type = amd_pp_dcf_clock; clock_req.clock_type = amd_pp_dcf_clock;
clock_req.clock_freq_in_khz = clocks.dcefClock * 10; clock_req.clock_freq_in_khz = clocks.dcefClock * 10;

56
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
View File

@ -2777,8 +2777,6 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
struct PP_Clocks minimum_clocks = {0}; struct PP_Clocks minimum_clocks = {0};
bool disable_mclk_switching; bool disable_mclk_switching;
bool disable_mclk_switching_for_frame_lock; bool disable_mclk_switching_for_frame_lock;
struct cgs_display_info info = {0};
struct cgs_mode_info mode_info = {0};
const struct phm_clock_and_voltage_limits *max_limits; const struct phm_clock_and_voltage_limits *max_limits;
uint32_t i; uint32_t i;
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
@ -2787,7 +2785,6 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
int32_t count; int32_t count;
int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0; int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
info.mode_info = &mode_info;
data->battery_state = (PP_StateUILabel_Battery == data->battery_state = (PP_StateUILabel_Battery ==
request_ps->classification.ui_label); request_ps->classification.ui_label);
@ -2809,10 +2806,8 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
} }
} }
cgs_get_active_displays_info(hwmgr->device, &info); minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock;
minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
minimum_clocks.engineClock = hwmgr->display_config.min_core_set_clock;
minimum_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock;
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_StablePState)) { PHM_PlatformCaps_StablePState)) {
@ -2843,12 +2838,12 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
PHM_PlatformCaps_DisableMclkSwitchingForFrameLock); PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
if (info.display_count == 0) if (hwmgr->display_config->num_display == 0)
disable_mclk_switching = false; disable_mclk_switching = false;
else else
disable_mclk_switching = ((1 < info.display_count) || disable_mclk_switching = ((1 < hwmgr->display_config->num_display) ||
disable_mclk_switching_for_frame_lock || disable_mclk_switching_for_frame_lock ||
smu7_vblank_too_short(hwmgr, mode_info.vblank_time_us)); smu7_vblank_too_short(hwmgr, hwmgr->display_config->min_vblank_time));
sclk = smu7_ps->performance_levels[0].engine_clock; sclk = smu7_ps->performance_levels[0].engine_clock;
mclk = smu7_ps->performance_levels[0].memory_clock; mclk = smu7_ps->performance_levels[0].memory_clock;
@ -3479,7 +3474,6 @@ static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, cons
[smu7_ps->performance_level_count - 1].memory_clock; [smu7_ps->performance_level_count - 1].memory_clock;
struct PP_Clocks min_clocks = {0}; struct PP_Clocks min_clocks = {0};
uint32_t i; uint32_t i;
struct cgs_display_info info = {0};
for (i = 0; i < sclk_table->count; i++) { for (i = 0; i < sclk_table->count; i++) {
if (sclk == sclk_table->dpm_levels[i].value) if (sclk == sclk_table->dpm_levels[i].value)
@ -3506,9 +3500,8 @@ static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, cons
if (i >= mclk_table->count) if (i >= mclk_table->count)
data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
cgs_get_active_displays_info(hwmgr->device, &info);
if (data->display_timing.num_existing_displays != info.display_count) if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK; data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
return 0; return 0;
@ -3907,15 +3900,8 @@ smu7_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
static int static int
smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr) smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
{ {
uint32_t num_active_displays = 0; if (hwmgr->display_config->num_display > 1 &&
struct cgs_display_info info = {0}; !hwmgr->display_config->multi_monitor_in_sync)
info.mode_info = NULL;
cgs_get_active_displays_info(hwmgr->device, &info);
num_active_displays = info.display_count;
if (num_active_displays > 1 && hwmgr->display_config.multi_monitor_in_sync != true)
smu7_notify_smc_display_change(hwmgr, false); smu7_notify_smc_display_change(hwmgr, false);
return 0; return 0;
@ -3930,33 +3916,24 @@ smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
static int smu7_program_display_gap(struct pp_hwmgr *hwmgr) static int smu7_program_display_gap(struct pp_hwmgr *hwmgr)
{ {
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
uint32_t num_active_displays = 0;
uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL); uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
uint32_t display_gap2; uint32_t display_gap2;
uint32_t pre_vbi_time_in_us; uint32_t pre_vbi_time_in_us;
uint32_t frame_time_in_us; uint32_t frame_time_in_us;
uint32_t ref_clock; uint32_t ref_clock, refresh_rate;
uint32_t refresh_rate = 0;
struct cgs_display_info info = {0};
struct cgs_mode_info mode_info = {0};
info.mode_info = &mode_info; display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (hwmgr->display_config->num_display > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
cgs_get_active_displays_info(hwmgr->device, &info);
num_active_displays = info.display_count;
display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap); cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
ref_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); ref_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
refresh_rate = hwmgr->display_config->vrefresh;
refresh_rate = mode_info.refresh_rate;
if (0 == refresh_rate) if (0 == refresh_rate)
refresh_rate = 60; refresh_rate = 60;
frame_time_in_us = 1000000 / refresh_rate; frame_time_in_us = 1000000 / refresh_rate;
pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us; pre_vbi_time_in_us = frame_time_in_us - 200 - hwmgr->display_config->min_vblank_time;
data->frame_time_x2 = frame_time_in_us * 2 / 100; data->frame_time_x2 = frame_time_in_us * 2 / 100;
@ -4036,17 +4013,14 @@ smu7_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
{ {
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
bool is_update_required = false; bool is_update_required = false;
struct cgs_display_info info = {0, 0, NULL};
cgs_get_active_displays_info(hwmgr->device, &info); if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
if (data->display_timing.num_existing_displays != info.display_count)
is_update_required = true; is_update_required = true;
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) { if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
if (data->display_timing.min_clock_in_sr != hwmgr->display_config.min_core_set_clock_in_sr && if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr &&
(data->display_timing.min_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK || (data->display_timing.min_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK ||
hwmgr->display_config.min_core_set_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK)) hwmgr->display_config->min_core_set_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK))
is_update_required = true; is_update_required = true;
} }
return is_update_required; return is_update_required;

14
drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
View File

@ -693,7 +693,7 @@ static int smu8_update_sclk_limit(struct pp_hwmgr *hwmgr)
else else
data->sclk_dpm.soft_max_clk = table->entries[table->count - 1].clk; data->sclk_dpm.soft_max_clk = table->entries[table->count - 1].clk;
clock = hwmgr->display_config.min_core_set_clock; clock = hwmgr->display_config->min_core_set_clock;
if (clock == 0) if (clock == 0)
pr_debug("min_core_set_clock not set\n"); pr_debug("min_core_set_clock not set\n");
@ -748,7 +748,7 @@ static int smu8_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr)
{ {
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SclkDeepSleep)) { PHM_PlatformCaps_SclkDeepSleep)) {
uint32_t clks = hwmgr->display_config.min_core_set_clock_in_sr; uint32_t clks = hwmgr->display_config->min_core_set_clock_in_sr;
if (clks == 0) if (clks == 0)
clks = SMU8_MIN_DEEP_SLEEP_SCLK; clks = SMU8_MIN_DEEP_SLEEP_SCLK;
@ -1040,25 +1040,21 @@ static int smu8_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
struct smu8_hwmgr *data = hwmgr->backend; struct smu8_hwmgr *data = hwmgr->backend;
struct PP_Clocks clocks = {0, 0, 0, 0}; struct PP_Clocks clocks = {0, 0, 0, 0};
bool force_high; bool force_high;
uint32_t num_of_active_displays = 0;
struct cgs_display_info info = {0};
smu8_ps->need_dfs_bypass = true; smu8_ps->need_dfs_bypass = true;
data->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label); data->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label);
clocks.memoryClock = hwmgr->display_config.min_mem_set_clock != 0 ? clocks.memoryClock = hwmgr->display_config->min_mem_set_clock != 0 ?
hwmgr->display_config.min_mem_set_clock : hwmgr->display_config->min_mem_set_clock :
data->sys_info.nbp_memory_clock[1]; data->sys_info.nbp_memory_clock[1];
cgs_get_active_displays_info(hwmgr->device, &info);
num_of_active_displays = info.display_count;
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
clocks.memoryClock = hwmgr->dyn_state.max_clock_voltage_on_ac.mclk; clocks.memoryClock = hwmgr->dyn_state.max_clock_voltage_on_ac.mclk;
force_high = (clocks.memoryClock > data->sys_info.nbp_memory_clock[SMU8_NUM_NBPMEMORYCLOCK - 1]) force_high = (clocks.memoryClock > data->sys_info.nbp_memory_clock[SMU8_NUM_NBPMEMORYCLOCK - 1])
|| (num_of_active_displays >= 3); || (hwmgr->display_config->num_display >= 3);
smu8_ps->action = smu8_current_ps->action; smu8_ps->action = smu8_current_ps->action;

51
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
View File

@ -3028,7 +3028,6 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
bool disable_mclk_switching_for_frame_lock; bool disable_mclk_switching_for_frame_lock;
bool disable_mclk_switching_for_vr; bool disable_mclk_switching_for_vr;
bool force_mclk_high; bool force_mclk_high;
struct cgs_display_info info = {0};
const struct phm_clock_and_voltage_limits *max_limits; const struct phm_clock_and_voltage_limits *max_limits;
uint32_t i; uint32_t i;
struct vega10_hwmgr *data = hwmgr->backend; struct vega10_hwmgr *data = hwmgr->backend;
@ -3063,11 +3062,9 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
} }
} }
cgs_get_active_displays_info(hwmgr->device, &info);
/* result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/ /* result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
minimum_clocks.engineClock = hwmgr->display_config.min_core_set_clock; minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock;
minimum_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock; minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
if (PP_CAP(PHM_PlatformCaps_StablePState)) { if (PP_CAP(PHM_PlatformCaps_StablePState)) {
stable_pstate_sclk_dpm_percentage = stable_pstate_sclk_dpm_percentage =
@ -3107,10 +3104,10 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
PP_CAP(PHM_PlatformCaps_DisableMclkSwitchForVR); PP_CAP(PHM_PlatformCaps_DisableMclkSwitchForVR);
force_mclk_high = PP_CAP(PHM_PlatformCaps_ForceMclkHigh); force_mclk_high = PP_CAP(PHM_PlatformCaps_ForceMclkHigh);
if (info.display_count == 0) if (hwmgr->display_config->num_display == 0)
disable_mclk_switching = false; disable_mclk_switching = false;
else else
disable_mclk_switching = (info.display_count > 1) || disable_mclk_switching = (hwmgr->display_config->num_display > 1) ||
disable_mclk_switching_for_frame_lock || disable_mclk_switching_for_frame_lock ||
disable_mclk_switching_for_vr || disable_mclk_switching_for_vr ||
force_mclk_high; force_mclk_high;
@ -3186,7 +3183,6 @@ static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, co
[vega10_ps->performance_level_count - 1].mem_clock; [vega10_ps->performance_level_count - 1].mem_clock;
struct PP_Clocks min_clocks = {0}; struct PP_Clocks min_clocks = {0};
uint32_t i; uint32_t i;
struct cgs_display_info info = {0};
data->need_update_dpm_table = 0; data->need_update_dpm_table = 0;
@ -3211,10 +3207,8 @@ static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, co
data->need_update_dpm_table |= DPMTABLE_UPDATE_SCLK; data->need_update_dpm_table |= DPMTABLE_UPDATE_SCLK;
} }
cgs_get_active_displays_info(hwmgr->device, &info);
if (data->display_timing.num_existing_displays != if (data->display_timing.num_existing_displays !=
info.display_count) hwmgr->display_config->num_display)
data->need_update_dpm_table |= DPMTABLE_UPDATE_MCLK; data->need_update_dpm_table |= DPMTABLE_UPDATE_MCLK;
} else { } else {
for (i = 0; i < sclk_table->count; i++) { for (i = 0; i < sclk_table->count; i++) {
@ -3242,13 +3236,11 @@ static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, co
break; break;
} }
cgs_get_active_displays_info(hwmgr->device, &info);
if (i >= mclk_table->count) if (i >= mclk_table->count)
data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
if (data->display_timing.num_existing_displays != if (data->display_timing.num_existing_displays !=
info.display_count || hwmgr->display_config->num_display ||
i >= mclk_table->count) i >= mclk_table->count)
data->need_update_dpm_table |= DPMTABLE_UPDATE_MCLK; data->need_update_dpm_table |= DPMTABLE_UPDATE_MCLK;
} }
@ -3956,26 +3948,18 @@ static int vega10_notify_smc_display_config_after_ps_adjustment(
(struct phm_ppt_v2_information *)hwmgr->pptable; (struct phm_ppt_v2_information *)hwmgr->pptable;
struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = table_info->vdd_dep_on_mclk; struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = table_info->vdd_dep_on_mclk;
uint32_t idx; uint32_t idx;
uint32_t num_active_disps = 0;
struct cgs_display_info info = {0};
struct PP_Clocks min_clocks = {0}; struct PP_Clocks min_clocks = {0};
uint32_t i; uint32_t i;
struct pp_display_clock_request clock_req; struct pp_display_clock_request clock_req;
info.mode_info = NULL; if (hwmgr->display_config->num_display > 1)
cgs_get_active_displays_info(hwmgr->device, &info);
num_active_disps = info.display_count;
if (num_active_disps > 1)
vega10_notify_smc_display_change(hwmgr, false); vega10_notify_smc_display_change(hwmgr, false);
else else
vega10_notify_smc_display_change(hwmgr, true); vega10_notify_smc_display_change(hwmgr, true);
min_clocks.dcefClock = hwmgr->display_config.min_dcef_set_clk; min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
min_clocks.dcefClockInSR = hwmgr->display_config.min_dcef_deep_sleep_set_clk; min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
min_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock; min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
for (i = 0; i < dpm_table->count; i++) { for (i = 0; i < dpm_table->count; i++) {
if (dpm_table->dpm_levels[i].value == min_clocks.dcefClock) if (dpm_table->dpm_levels[i].value == min_clocks.dcefClock)
@ -4501,10 +4485,8 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr) static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
{ {
struct vega10_hwmgr *data = hwmgr->backend; struct vega10_hwmgr *data = hwmgr->backend;
int result = 0;
uint32_t num_turned_on_displays = 1;
Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
struct cgs_display_info info = {0}; int result = 0;
if ((data->water_marks_bitmap & WaterMarksExist) && if ((data->water_marks_bitmap & WaterMarksExist) &&
!(data->water_marks_bitmap & WaterMarksLoaded)) { !(data->water_marks_bitmap & WaterMarksLoaded)) {
@ -4514,10 +4496,8 @@ static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
} }
if (data->water_marks_bitmap & WaterMarksLoaded) { if (data->water_marks_bitmap & WaterMarksLoaded) {
cgs_get_active_displays_info(hwmgr->device, &info);
num_turned_on_displays = info.display_count;
smum_send_msg_to_smc_with_parameter(hwmgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_NumOfDisplays, num_turned_on_displays); PPSMC_MSG_NumOfDisplays, hwmgr->display_config->num_display);
} }
return result; return result;
@ -4603,15 +4583,12 @@ vega10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmg
{ {
struct vega10_hwmgr *data = hwmgr->backend; struct vega10_hwmgr *data = hwmgr->backend;
bool is_update_required = false; bool is_update_required = false;
struct cgs_display_info info = {0, 0, NULL};
cgs_get_active_displays_info(hwmgr->device, &info); if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
if (data->display_timing.num_existing_displays != info.display_count)
is_update_required = true; is_update_required = true;
if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep)) { if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep)) {
if (data->display_timing.min_clock_in_sr != hwmgr->display_config.min_core_set_clock_in_sr) if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr)
is_update_required = true; is_update_required = true;
} }

29
drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
View File

@ -1260,23 +1260,18 @@ static int vega12_notify_smc_display_config_after_ps_adjustment(
{ {
struct vega12_hwmgr *data = struct vega12_hwmgr *data =
(struct vega12_hwmgr *)(hwmgr->backend); (struct vega12_hwmgr *)(hwmgr->backend);
uint32_t num_active_disps = 0;
struct cgs_display_info info = {0};
struct PP_Clocks min_clocks = {0}; struct PP_Clocks min_clocks = {0};
struct pp_display_clock_request clock_req; struct pp_display_clock_request clock_req;
uint32_t clk_request; uint32_t clk_request;
info.mode_info = NULL; if (hwmgr->display_config->num_display > 1)
cgs_get_active_displays_info(hwmgr->device, &info);
num_active_disps = info.display_count;
if (num_active_disps > 1)
vega12_notify_smc_display_change(hwmgr, false); vega12_notify_smc_display_change(hwmgr, false);
else else
vega12_notify_smc_display_change(hwmgr, true); vega12_notify_smc_display_change(hwmgr, true);
min_clocks.dcefClock = hwmgr->display_config.min_dcef_set_clk; min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
min_clocks.dcefClockInSR = hwmgr->display_config.min_dcef_deep_sleep_set_clk; min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
min_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock; min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
if (data->smu_features[GNLD_DPM_DCEFCLK].supported) { if (data->smu_features[GNLD_DPM_DCEFCLK].supported) {
clock_req.clock_type = amd_pp_dcef_clock; clock_req.clock_type = amd_pp_dcef_clock;
@ -1832,9 +1827,7 @@ static int vega12_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
{ {
struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
int result = 0; int result = 0;
uint32_t num_turned_on_displays = 1;
Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
struct cgs_display_info info = {0};
if ((data->water_marks_bitmap & WaterMarksExist) && if ((data->water_marks_bitmap & WaterMarksExist) &&
!(data->water_marks_bitmap & WaterMarksLoaded)) { !(data->water_marks_bitmap & WaterMarksLoaded)) {
@ -1846,12 +1839,9 @@ static int vega12_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
if ((data->water_marks_bitmap & WaterMarksExist) && if ((data->water_marks_bitmap & WaterMarksExist) &&
data->smu_features[GNLD_DPM_DCEFCLK].supported && data->smu_features[GNLD_DPM_DCEFCLK].supported &&
data->smu_features[GNLD_DPM_SOCCLK].supported) { data->smu_features[GNLD_DPM_SOCCLK].supported)
cgs_get_active_displays_info(hwmgr->device, &info);
num_turned_on_displays = info.display_count;
smum_send_msg_to_smc_with_parameter(hwmgr, smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_NumOfDisplays, num_turned_on_displays); PPSMC_MSG_NumOfDisplays, hwmgr->display_config->num_display);
}
return result; return result;
} }
@ -1894,15 +1884,12 @@ vega12_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmg
{ {
struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
bool is_update_required = false; bool is_update_required = false;
struct cgs_display_info info = {0, 0, NULL};
cgs_get_active_displays_info(hwmgr->device, &info); if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
if (data->display_timing.num_existing_displays != info.display_count)
is_update_required = true; is_update_required = true;
if (data->registry_data.gfx_clk_deep_sleep_support) { if (data->registry_data.gfx_clk_deep_sleep_support) {
if (data->display_timing.min_clock_in_sr != hwmgr->display_config.min_core_set_clock_in_sr) if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr)
is_update_required = true; is_update_required = true;
} }

2
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
View File

@ -765,7 +765,7 @@ struct pp_hwmgr {
struct pp_power_state *request_ps; struct pp_power_state *request_ps;
struct pp_power_state *boot_ps; struct pp_power_state *boot_ps;
struct pp_power_state *uvd_ps; struct pp_power_state *uvd_ps;
struct amd_pp_display_configuration display_config; const struct amd_pp_display_configuration *display_config;
uint32_t feature_mask; uint32_t feature_mask;
bool avfs_supported; bool avfs_supported;
/* UMD Pstate */ /* UMD Pstate */

4
drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
View File

@ -1182,7 +1182,6 @@ static int ci_populate_single_memory_level(
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
int result = 0; int result = 0;
bool dll_state_on; bool dll_state_on;
struct cgs_display_info info = {0};
uint32_t mclk_edc_wr_enable_threshold = 40000; uint32_t mclk_edc_wr_enable_threshold = 40000;
uint32_t mclk_edc_enable_threshold = 40000; uint32_t mclk_edc_enable_threshold = 40000;
uint32_t mclk_strobe_mode_threshold = 40000; uint32_t mclk_strobe_mode_threshold = 40000;
@ -1236,8 +1235,7 @@ static int ci_populate_single_memory_level(
/* default set to low watermark. Highest level will be set to high later.*/ /* default set to low watermark. Highest level will be set to high later.*/
memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
cgs_get_active_displays_info(hwmgr->device, &info); data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
data->display_timing.num_existing_displays = info.display_count;
/* stutter mode not support on ci */ /* stutter mode not support on ci */

4
drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
View File

@ -988,11 +988,11 @@ static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
threshold = clock * data->fast_watermark_threshold / 100; threshold = clock * data->fast_watermark_threshold / 100;
data->display_timing.min_clock_in_sr = hwmgr->display_config.min_core_set_clock_in_sr; data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr;
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
level->DeepSleepDivId = smu7_get_sleep_divider_id_from_clock(clock, level->DeepSleepDivId = smu7_get_sleep_divider_id_from_clock(clock,
hwmgr->display_config.min_core_set_clock_in_sr); hwmgr->display_config->min_core_set_clock_in_sr);
/* Default to slow, highest DPM level will be /* Default to slow, highest DPM level will be

6
drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
View File

@ -932,7 +932,7 @@ static int iceland_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
graphic_level->PowerThrottle = 0; graphic_level->PowerThrottle = 0;
data->display_timing.min_clock_in_sr = data->display_timing.min_clock_in_sr =
hwmgr->display_config.min_core_set_clock_in_sr; hwmgr->display_config->min_core_set_clock_in_sr;
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SclkDeepSleep)) PHM_PlatformCaps_SclkDeepSleep))
@ -1236,7 +1236,6 @@ static int iceland_populate_single_memory_level(
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
int result = 0; int result = 0;
bool dll_state_on; bool dll_state_on;
struct cgs_display_info info = {0};
uint32_t mclk_edc_wr_enable_threshold = 40000; uint32_t mclk_edc_wr_enable_threshold = 40000;
uint32_t mclk_edc_enable_threshold = 40000; uint32_t mclk_edc_enable_threshold = 40000;
uint32_t mclk_strobe_mode_threshold = 40000; uint32_t mclk_strobe_mode_threshold = 40000;
@ -1283,8 +1282,7 @@ static int iceland_populate_single_memory_level(
/* default set to low watermark. Highest level will be set to high later.*/ /* default set to low watermark. Highest level will be set to high later.*/
memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
cgs_get_active_displays_info(hwmgr->device, &info); data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
data->display_timing.num_existing_displays = info.display_count;
/* stutter mode not support on iceland */ /* stutter mode not support on iceland */

8
drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
View File

@ -942,11 +942,11 @@ static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
level->DownHyst = data->current_profile_setting.sclk_down_hyst; level->DownHyst = data->current_profile_setting.sclk_down_hyst;
level->VoltageDownHyst = 0; level->VoltageDownHyst = 0;
level->PowerThrottle = 0; level->PowerThrottle = 0;
data->display_timing.min_clock_in_sr = hwmgr->display_config.min_core_set_clock_in_sr; data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr;
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
level->DeepSleepDivId = smu7_get_sleep_divider_id_from_clock(clock, level->DeepSleepDivId = smu7_get_sleep_divider_id_from_clock(clock,
hwmgr->display_config.min_core_set_clock_in_sr); hwmgr->display_config->min_core_set_clock_in_sr);
/* Default to slow, highest DPM level will be /* Default to slow, highest DPM level will be
* set to PPSMC_DISPLAY_WATERMARK_LOW later. * set to PPSMC_DISPLAY_WATERMARK_LOW later.
@ -1076,11 +1076,9 @@ static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
struct phm_ppt_v1_information *table_info = struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable); (struct phm_ppt_v1_information *)(hwmgr->pptable);
int result = 0; int result = 0;
struct cgs_display_info info = {0, 0, NULL};
uint32_t mclk_stutter_mode_threshold = 40000; uint32_t mclk_stutter_mode_threshold = 40000;
phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL; phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
cgs_get_active_displays_info(hwmgr->device, &info);
if (hwmgr->od_enabled) if (hwmgr->od_enabled)
vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_mclk; vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_mclk;
@ -1106,7 +1104,7 @@ static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
mem_level->StutterEnable = false; mem_level->StutterEnable = false;
mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
data->display_timing.num_existing_displays = info.display_count; data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
if (mclk_stutter_mode_threshold && if (mclk_stutter_mode_threshold &&
(clock <= mclk_stutter_mode_threshold) && (clock <= mclk_stutter_mode_threshold) &&

12
drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
View File

@ -650,7 +650,7 @@ static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
graphic_level->PowerThrottle = 0; graphic_level->PowerThrottle = 0;
data->display_timing.min_clock_in_sr = data->display_timing.min_clock_in_sr =
hwmgr->display_config.min_core_set_clock_in_sr; hwmgr->display_config->min_core_set_clock_in_sr;
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SclkDeepSleep)) PHM_PlatformCaps_SclkDeepSleep))
@ -956,18 +956,17 @@ static int tonga_populate_single_memory_level(
SMU72_Discrete_MemoryLevel *memory_level SMU72_Discrete_MemoryLevel *memory_level
) )
{ {
uint32_t mvdd = 0;
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
struct phm_ppt_v1_information *pptable_info = struct phm_ppt_v1_information *pptable_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable); (struct phm_ppt_v1_information *)(hwmgr->pptable);
int result = 0;
bool dll_state_on;
struct cgs_display_info info = {0};
uint32_t mclk_edc_wr_enable_threshold = 40000; uint32_t mclk_edc_wr_enable_threshold = 40000;
uint32_t mclk_stutter_mode_threshold = 30000; uint32_t mclk_stutter_mode_threshold = 30000;
uint32_t mclk_edc_enable_threshold = 40000; uint32_t mclk_edc_enable_threshold = 40000;
uint32_t mclk_strobe_mode_threshold = 40000; uint32_t mclk_strobe_mode_threshold = 40000;
phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL; phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
int result = 0;
bool dll_state_on;
uint32_t mvdd = 0;
if (hwmgr->od_enabled) if (hwmgr->od_enabled)
vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_mclk; vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_mclk;
@ -1008,8 +1007,7 @@ static int tonga_populate_single_memory_level(
/* default set to low watermark. Highest level will be set to high later.*/ /* default set to low watermark. Highest level will be set to high later.*/
memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
cgs_get_active_displays_info(hwmgr->device, &info); data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
data->display_timing.num_existing_displays = info.display_count;
if ((mclk_stutter_mode_threshold != 0) && if ((mclk_stutter_mode_threshold != 0) &&
(memory_clock <= mclk_stutter_mode_threshold) && (memory_clock <= mclk_stutter_mode_threshold) &&