forked from Minki/linux
[POWERPC] Merge asm-ppc/pci-bridge.h into asm-power/pci-bridge.h
Moved bits need for ppc32 from asm-ppc/pci-bridge.h into asm-powerpc/pci-bridge.h. Removed ARCH=powerpc specific bits (and comments related to ARCH=ppc) from asm-ppc/pci-bridge.h as its only used on ARCH=ppc. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala
parent
20243c72a8
commit
5531e41bf4
@ -3,7 +3,103 @@
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#ifdef __KERNEL__
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#ifndef CONFIG_PPC64
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#include <asm-ppc/pci-bridge.h>
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#include <linux/ioport.h>
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#include <linux/pci.h>
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struct device_node;
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struct pci_controller;
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/*
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* pci_io_base returns the memory address at which you can access
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* the I/O space for PCI bus number `bus' (or NULL on error).
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*/
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extern void __iomem *pci_bus_io_base(unsigned int bus);
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extern unsigned long pci_bus_io_base_phys(unsigned int bus);
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extern unsigned long pci_bus_mem_base_phys(unsigned int bus);
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/* Allocate a new PCI host bridge structure */
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extern struct pci_controller* pcibios_alloc_controller(void);
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/* Helper function for setting up resources */
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extern void pci_init_resource(struct resource *res, resource_size_t start,
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resource_size_t end, int flags, char *name);
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/* Get the PCI host controller for a bus */
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extern struct pci_controller* pci_bus_to_hose(int bus);
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/*
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* Structure of a PCI controller (host bridge)
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*/
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struct pci_controller {
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struct pci_bus *bus;
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void *arch_data;
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int index; /* PCI domain number */
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struct pci_controller *next;
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struct device *parent;
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int first_busno;
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int last_busno;
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int self_busno;
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void __iomem *io_base_virt;
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resource_size_t io_base_phys;
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/* Some machines (PReP) have a non 1:1 mapping of
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* the PCI memory space in the CPU bus space
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*/
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resource_size_t pci_mem_offset;
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struct pci_ops *ops;
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volatile unsigned int __iomem *cfg_addr;
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volatile void __iomem *cfg_data;
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/*
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* Used for variants of PCI indirect handling and possible quirks:
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* SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
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* EXT_REG - provides access to PCI-e extended registers
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* SURPRESS_PRIMARY_BUS - we surpress the setting of PCI_PRIMARY_BUS
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* on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
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* to determine which bus number to match on when generating type0
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* config cycles
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*/
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#define PPC_INDIRECT_TYPE_SET_CFG_TYPE (0x00000001)
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#define PPC_INDIRECT_TYPE_EXT_REG (0x00000002)
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#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS (0x00000004)
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u32 indirect_type;
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/* Currently, we limit ourselves to 1 IO range and 3 mem
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* ranges since the common pci_bus structure can't handle more
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*/
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struct resource io_resource;
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struct resource mem_resources[3];
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};
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static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
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{
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return bus->sysdata;
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}
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/* These are used for config access before all the PCI probing
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has been done. */
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int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn,
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int where, u8 *val);
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int early_read_config_word(struct pci_controller *hose, int bus, int dev_fn,
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int where, u16 *val);
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int early_read_config_dword(struct pci_controller *hose, int bus, int dev_fn,
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int where, u32 *val);
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int early_write_config_byte(struct pci_controller *hose, int bus, int dev_fn,
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int where, u8 val);
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int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn,
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int where, u16 val);
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int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn,
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int where, u32 val);
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extern void setup_indirect_pci_nomap(struct pci_controller* hose,
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void __iomem *cfg_addr, void __iomem *cfg_data);
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extern void setup_indirect_pci(struct pci_controller* hose,
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u32 cfg_addr, u32 cfg_data);
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extern void setup_grackle(struct pci_controller *hose);
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#else
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#include <linux/pci.h>
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@ -49,8 +145,8 @@ struct pci_controller {
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*/
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struct resource io_resource;
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struct resource mem_resources[3];
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int global_number;
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int local_number;
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int global_number;
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int local_number;
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unsigned long buid;
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unsigned long dma_window_base_cur;
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unsigned long dma_window_size;
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@ -132,9 +228,6 @@ static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
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/** Find the bus corresponding to the indicated device node */
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struct pci_bus * pcibios_find_pci_bus(struct device_node *dn);
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extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
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struct device_node *dev, int primary);
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/** Remove all of the PCI devices under this bus */
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void pcibios_remove_pci_devices(struct pci_bus *bus);
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@ -152,22 +245,10 @@ static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
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return PCI_DN(busdn)->phb;
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}
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extern struct pci_controller*
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pci_find_hose_for_OF_device(struct device_node* node);
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extern struct pci_controller *
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pcibios_alloc_controller(struct device_node *dev);
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extern void pcibios_free_controller(struct pci_controller *phb);
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#ifdef CONFIG_PCI
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extern unsigned long pci_address_to_pio(phys_addr_t address);
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#else
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static inline unsigned long pci_address_to_pio(phys_addr_t address)
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{
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return (unsigned long)-1;
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}
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#endif
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extern void isa_bridge_find_early(struct pci_controller *hose);
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extern int pcibios_unmap_io_space(struct pci_bus *bus);
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@ -185,5 +266,26 @@ extern int pcibios_map_io_space(struct pci_bus *bus);
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#endif
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#endif /* CONFIG_PPC64 */
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/* Get the PCI host controller for an OF device */
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extern struct pci_controller*
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pci_find_hose_for_OF_device(struct device_node* node);
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/* Fill up host controller resources from the OF node */
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extern void
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pci_process_bridge_OF_ranges(struct pci_controller *hose,
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struct device_node *dev, int primary);
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#ifdef CONFIG_PCI
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extern unsigned long pci_address_to_pio(phys_addr_t address);
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#else
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static inline unsigned long pci_address_to_pio(phys_addr_t address)
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{
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return (unsigned long)-1;
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}
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#endif
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#endif /* __KERNEL__ */
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#endif
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@ -47,8 +47,6 @@ struct pci_controller {
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int first_busno;
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int last_busno;
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int self_busno;
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/* bus_offset is only used by ARCH=ppc */
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int bus_offset;
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void __iomem *io_base_virt;
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@ -65,24 +63,9 @@ struct pci_controller {
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/*
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* If set, indirect method will set the cfg_type bit as
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* needed to generate type 1 configuration transactions.
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* use only on ARCH=ppc
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*/
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int set_cfg_type;
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/*
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* Used for variants of PCI indirect handling and possible quirks:
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* SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
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* EXT_REG - provides access to PCI-e extended registers
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* SURPRESS_PRIMARY_BUS - we surpress the setting of PCI_PRIMARY_BUS
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* on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
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* to determine which bus number to match on when generating type0
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* config cycles
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*/
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#define PPC_INDIRECT_TYPE_SET_CFG_TYPE (0x00000001)
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#define PPC_INDIRECT_TYPE_EXT_REG (0x00000002)
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#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS (0x00000004)
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u32 indirect_type;
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/* Currently, we limit ourselves to 1 IO range and 3 mem
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* ranges since the common pci_bus structure can't handle more
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*/
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