leandrof/linux
1
0
Fork 0
forked from Minki/linux
Code Issues Pull Requests Packages Projects Releases Wiki Activity

drm/nouveau/mc: convert to new-style nvkm_subdev

Browse Source 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2015-08-20 14:54:21 +10:00
parent 70bc7182cb
commit 54dcadd5b6
28 changed files with 265 additions and 381 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

31
drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h
View File

@ -3,26 +3,23 @@
#include <core/subdev.h>
struct nvkm_mc {
const struct nvkm_mc_func *func;
struct nvkm_subdev subdev;
bool use_msi;
unsigned int irq;
void (*unk260)(struct nvkm_mc *, u32);
bool use_msi;
};
static inline struct nvkm_mc *
nvkm_mc(void *obj)
{
return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_MC);
}
void nvkm_mc_unk260(struct nvkm_mc *, u32 data);
extern struct nvkm_oclass *nv04_mc_oclass;
extern struct nvkm_oclass *nv40_mc_oclass;
extern struct nvkm_oclass *nv44_mc_oclass;
extern struct nvkm_oclass *nv4c_mc_oclass;
extern struct nvkm_oclass *nv50_mc_oclass;
extern struct nvkm_oclass *g94_mc_oclass;
extern struct nvkm_oclass *g98_mc_oclass;
extern struct nvkm_oclass *gf100_mc_oclass;
extern struct nvkm_oclass *gf106_mc_oclass;
extern struct nvkm_oclass *gk20a_mc_oclass;
int nv04_mc_new(struct nvkm_device *, int, struct nvkm_mc **);
int nv40_mc_new(struct nvkm_device *, int, struct nvkm_mc **);
int nv44_mc_new(struct nvkm_device *, int, struct nvkm_mc **);
int nv4c_mc_new(struct nvkm_device *, int, struct nvkm_mc **);
int nv50_mc_new(struct nvkm_device *, int, struct nvkm_mc **);
int g94_mc_new(struct nvkm_device *, int, struct nvkm_mc **);
int g98_mc_new(struct nvkm_device *, int, struct nvkm_mc **);
int gf100_mc_new(struct nvkm_device *, int, struct nvkm_mc **);
int gf106_mc_new(struct nvkm_device *, int, struct nvkm_mc **);
int gk20a_mc_new(struct nvkm_device *, int, struct nvkm_mc **);
#endif

138
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View File

@ -83,7 +83,7 @@ nv4_chipset = {
.fb = nv04_fb_new,
.i2c = nv04_i2c_new,
.imem = nv04_instmem_new,
// .mc = nv04_mc_new,
.mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
@ -103,7 +103,7 @@ nv5_chipset = {
.fb = nv04_fb_new,
.i2c = nv04_i2c_new,
.imem = nv04_instmem_new,
// .mc = nv04_mc_new,
.mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
@ -124,7 +124,7 @@ nv10_chipset = {
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
.imem = nv04_instmem_new,
// .mc = nv04_mc_new,
.mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
@ -143,7 +143,7 @@ nv11_chipset = {
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
.imem = nv04_instmem_new,
// .mc = nv04_mc_new,
.mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
@ -164,7 +164,7 @@ nv15_chipset = {
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
.imem = nv04_instmem_new,
// .mc = nv04_mc_new,
.mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
@ -185,7 +185,7 @@ nv17_chipset = {
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
.imem = nv04_instmem_new,
// .mc = nv04_mc_new,
.mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
@ -206,7 +206,7 @@ nv18_chipset = {
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
.imem = nv04_instmem_new,
// .mc = nv04_mc_new,
.mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
@ -227,7 +227,7 @@ nv1a_chipset = {
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
.imem = nv04_instmem_new,
// .mc = nv04_mc_new,
.mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
@ -248,7 +248,7 @@ nv1f_chipset = {
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
.imem = nv04_instmem_new,
// .mc = nv04_mc_new,
.mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
@ -269,7 +269,7 @@ nv20_chipset = {
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
.imem = nv04_instmem_new,
// .mc = nv04_mc_new,
.mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
@ -290,7 +290,7 @@ nv25_chipset = {
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
.imem = nv04_instmem_new,
// .mc = nv04_mc_new,
.mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
@ -311,7 +311,7 @@ nv28_chipset = {
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
.imem = nv04_instmem_new,
// .mc = nv04_mc_new,
.mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
@ -332,7 +332,7 @@ nv2a_chipset = {
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
.imem = nv04_instmem_new,
// .mc = nv04_mc_new,
.mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
@ -353,7 +353,7 @@ nv30_chipset = {
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
.imem = nv04_instmem_new,
// .mc = nv04_mc_new,
.mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
@ -374,7 +374,7 @@ nv31_chipset = {
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
.imem = nv04_instmem_new,
// .mc = nv04_mc_new,
.mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
@ -396,7 +396,7 @@ nv34_chipset = {
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
.imem = nv04_instmem_new,
// .mc = nv04_mc_new,
.mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
@ -418,7 +418,7 @@ nv35_chipset = {
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
.imem = nv04_instmem_new,
// .mc = nv04_mc_new,
.mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
@ -439,7 +439,7 @@ nv36_chipset = {
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
.imem = nv04_instmem_new,
// .mc = nv04_mc_new,
.mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
@ -461,7 +461,7 @@ nv40_chipset = {
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
.imem = nv40_instmem_new,
// .mc = nv40_mc_new,
.mc = nv40_mc_new,
// .mmu = nv04_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
@ -486,7 +486,7 @@ nv41_chipset = {
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
.imem = nv40_instmem_new,
// .mc = nv40_mc_new,
.mc = nv40_mc_new,
// .mmu = nv41_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
@ -511,7 +511,7 @@ nv42_chipset = {
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
.imem = nv40_instmem_new,
// .mc = nv40_mc_new,
.mc = nv40_mc_new,
// .mmu = nv41_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
@ -536,7 +536,7 @@ nv43_chipset = {
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
.imem = nv40_instmem_new,
// .mc = nv40_mc_new,
.mc = nv40_mc_new,
// .mmu = nv41_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
@ -561,7 +561,7 @@ nv44_chipset = {
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
.imem = nv40_instmem_new,
// .mc = nv44_mc_new,
.mc = nv44_mc_new,
// .mmu = nv44_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
@ -586,7 +586,7 @@ nv45_chipset = {
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
.imem = nv40_instmem_new,
// .mc = nv40_mc_new,
.mc = nv40_mc_new,
// .mmu = nv04_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
@ -611,7 +611,7 @@ nv46_chipset = {
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
.imem = nv40_instmem_new,
// .mc = nv44_mc_new,
.mc = nv44_mc_new,
// .mmu = nv44_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
@ -636,7 +636,7 @@ nv47_chipset = {
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
.imem = nv40_instmem_new,
// .mc = nv40_mc_new,
.mc = nv40_mc_new,
// .mmu = nv41_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
@ -661,7 +661,7 @@ nv49_chipset = {
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
.imem = nv40_instmem_new,
// .mc = nv40_mc_new,
.mc = nv40_mc_new,
// .mmu = nv41_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
@ -686,7 +686,7 @@ nv4a_chipset = {
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
.imem = nv40_instmem_new,
// .mc = nv44_mc_new,
.mc = nv44_mc_new,
// .mmu = nv44_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
@ -711,7 +711,7 @@ nv4b_chipset = {
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
.imem = nv40_instmem_new,
// .mc = nv40_mc_new,
.mc = nv40_mc_new,
// .mmu = nv41_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
@ -736,7 +736,7 @@ nv4c_chipset = {
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
.imem = nv40_instmem_new,
// .mc = nv4c_mc_new,
.mc = nv4c_mc_new,
// .mmu = nv44_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
@ -761,7 +761,7 @@ nv4e_chipset = {
.gpio = nv10_gpio_new,
.i2c = nv4e_i2c_new,
.imem = nv40_instmem_new,
// .mc = nv4c_mc_new,
.mc = nv4c_mc_new,
// .mmu = nv44_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
@ -788,7 +788,7 @@ nv50_chipset = {
.gpio = nv50_gpio_new,
.i2c = nv50_i2c_new,
.imem = nv50_instmem_new,
// .mc = nv50_mc_new,
.mc = nv50_mc_new,
// .mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
// .therm = nv50_therm_new,
@ -814,7 +814,7 @@ nv63_chipset = {
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
.imem = nv40_instmem_new,
// .mc = nv4c_mc_new,
.mc = nv4c_mc_new,
// .mmu = nv44_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
@ -839,7 +839,7 @@ nv67_chipset = {
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
.imem = nv40_instmem_new,
// .mc = nv4c_mc_new,
.mc = nv4c_mc_new,
// .mmu = nv44_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
@ -864,7 +864,7 @@ nv68_chipset = {
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
.imem = nv40_instmem_new,
// .mc = nv4c_mc_new,
.mc = nv4c_mc_new,
// .mmu = nv44_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
@ -891,7 +891,7 @@ nv84_chipset = {
.gpio = nv50_gpio_new,
.i2c = nv50_i2c_new,
.imem = nv50_instmem_new,
// .mc = nv50_mc_new,
.mc = nv50_mc_new,
// .mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
// .therm = g84_therm_new,
@ -922,7 +922,7 @@ nv86_chipset = {
.gpio = nv50_gpio_new,
.i2c = nv50_i2c_new,
.imem = nv50_instmem_new,
// .mc = nv50_mc_new,
.mc = nv50_mc_new,
// .mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
// .therm = g84_therm_new,
@ -953,7 +953,7 @@ nv92_chipset = {
.gpio = nv50_gpio_new,
.i2c = nv50_i2c_new,
.imem = nv50_instmem_new,
// .mc = nv50_mc_new,
.mc = nv50_mc_new,
// .mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
// .therm = g84_therm_new,
@ -984,7 +984,7 @@ nv94_chipset = {
.gpio = g94_gpio_new,
.i2c = g94_i2c_new,
.imem = nv50_instmem_new,
// .mc = g94_mc_new,
.mc = g94_mc_new,
// .mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
// .therm = g84_therm_new,
@ -1013,7 +1013,7 @@ nv96_chipset = {
// .therm = g84_therm_new,
// .mxm = nv50_mxm_new,
.devinit = g84_devinit_new,
// .mc = g94_mc_new,
.mc = g94_mc_new,
.bus = g94_bus_new,
// .timer = nv04_timer_new,
.fb = g84_fb_new,
@ -1044,7 +1044,7 @@ nv98_chipset = {
// .therm = g84_therm_new,
// .mxm = nv50_mxm_new,
.devinit = g98_devinit_new,
// .mc = g98_mc_new,
.mc = g98_mc_new,
.bus = g94_bus_new,
// .timer = nv04_timer_new,
.fb = g84_fb_new,
@ -1077,7 +1077,7 @@ nva0_chipset = {
.gpio = g94_gpio_new,
.i2c = nv50_i2c_new,
.imem = nv50_instmem_new,
// .mc = g98_mc_new,
.mc = g98_mc_new,
// .mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
// .therm = g84_therm_new,
@ -1108,7 +1108,7 @@ nva3_chipset = {
.gpio = g94_gpio_new,
.i2c = g94_i2c_new,
.imem = nv50_instmem_new,
// .mc = g98_mc_new,
.mc = g98_mc_new,
// .mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gt215_pmu_new,
@ -1141,7 +1141,7 @@ nva5_chipset = {
.gpio = g94_gpio_new,
.i2c = g94_i2c_new,
.imem = nv50_instmem_new,
// .mc = g98_mc_new,
.mc = g98_mc_new,
// .mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gt215_pmu_new,
@ -1173,7 +1173,7 @@ nva8_chipset = {
.gpio = g94_gpio_new,
.i2c = g94_i2c_new,
.imem = nv50_instmem_new,
// .mc = g98_mc_new,
.mc = g98_mc_new,
// .mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gt215_pmu_new,
@ -1205,7 +1205,7 @@ nvaa_chipset = {
.gpio = g94_gpio_new,
.i2c = g94_i2c_new,
.imem = nv50_instmem_new,
// .mc = g98_mc_new,
.mc = g98_mc_new,
// .mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
// .therm = g84_therm_new,
@ -1236,7 +1236,7 @@ nvac_chipset = {
.gpio = g94_gpio_new,
.i2c = g94_i2c_new,
.imem = nv50_instmem_new,
// .mc = g98_mc_new,
.mc = g98_mc_new,
// .mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
// .therm = g84_therm_new,
@ -1267,7 +1267,7 @@ nvaf_chipset = {
.gpio = g94_gpio_new,
.i2c = g94_i2c_new,
.imem = nv50_instmem_new,
// .mc = g98_mc_new,
.mc = g98_mc_new,
// .mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gt215_pmu_new,
@ -1301,7 +1301,7 @@ nvc0_chipset = {
.ibus = gf100_ibus_new,
.imem = nv50_instmem_new,
.ltc = gf100_ltc_new,
// .mc = gf100_mc_new,
.mc = gf100_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gf100_pmu_new,
@ -1336,7 +1336,7 @@ nvc1_chipset = {
.ibus = gf100_ibus_new,
.imem = nv50_instmem_new,
.ltc = gf100_ltc_new,
// .mc = gf106_mc_new,
.mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gf100_pmu_new,
@ -1370,7 +1370,7 @@ nvc3_chipset = {
.ibus = gf100_ibus_new,
.imem = nv50_instmem_new,
.ltc = gf100_ltc_new,
// .mc = gf106_mc_new,
.mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gf100_pmu_new,
@ -1404,7 +1404,7 @@ nvc4_chipset = {
.ibus = gf100_ibus_new,
.imem = nv50_instmem_new,
.ltc = gf100_ltc_new,
// .mc = gf100_mc_new,
.mc = gf100_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gf100_pmu_new,
@ -1439,7 +1439,7 @@ nvc8_chipset = {
.ibus = gf100_ibus_new,
.imem = nv50_instmem_new,
.ltc = gf100_ltc_new,
// .mc = gf100_mc_new,
.mc = gf100_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gf100_pmu_new,
@ -1474,7 +1474,7 @@ nvce_chipset = {
.ibus = gf100_ibus_new,
.imem = nv50_instmem_new,
.ltc = gf100_ltc_new,
// .mc = gf100_mc_new,
.mc = gf100_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gf100_pmu_new,
@ -1509,7 +1509,7 @@ nvcf_chipset = {
.ibus = gf100_ibus_new,
.imem = nv50_instmem_new,
.ltc = gf100_ltc_new,
// .mc = gf106_mc_new,
.mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gf100_pmu_new,
@ -1543,7 +1543,7 @@ nvd7_chipset = {
.ibus = gf100_ibus_new,
.imem = nv50_instmem_new,
.ltc = gf100_ltc_new,
// .mc = gf106_mc_new,
.mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .therm = gf110_therm_new,
@ -1575,7 +1575,7 @@ nvd9_chipset = {
.ibus = gf100_ibus_new,
.imem = nv50_instmem_new,
.ltc = gf100_ltc_new,
// .mc = gf106_mc_new,
.mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gf110_pmu_new,
@ -1609,7 +1609,7 @@ nve4_chipset = {
.ibus = gk104_ibus_new,
.imem = nv50_instmem_new,
.ltc = gk104_ltc_new,
// .mc = gf106_mc_new,
.mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gk104_pmu_new,
@ -1645,7 +1645,7 @@ nve6_chipset = {
.ibus = gk104_ibus_new,
.imem = nv50_instmem_new,
.ltc = gk104_ltc_new,
// .mc = gf106_mc_new,
.mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gk104_pmu_new,
@ -1681,7 +1681,7 @@ nve7_chipset = {
.ibus = gk104_ibus_new,
.imem = nv50_instmem_new,
.ltc = gk104_ltc_new,
// .mc = gf106_mc_new,
.mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gf110_pmu_new,
@ -1713,7 +1713,7 @@ nvea_chipset = {
.ibus = gk20a_ibus_new,
.imem = gk20a_instmem_new,
.ltc = gk104_ltc_new,
// .mc = gk20a_mc_new,
.mc = gk20a_mc_new,
// .mmu = gf100_mmu_new,
// .pmu = gk20a_pmu_new,
// .timer = gk20a_timer_new,
@ -1741,7 +1741,7 @@ nvf0_chipset = {
.ibus = gk104_ibus_new,
.imem = nv50_instmem_new,
.ltc = gk104_ltc_new,
// .mc = gf106_mc_new,
.mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gk110_pmu_new,
@ -1777,7 +1777,7 @@ nvf1_chipset = {
.ibus = gk104_ibus_new,
.imem = nv50_instmem_new,
.ltc = gk104_ltc_new,
// .mc = gf106_mc_new,
.mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gk110_pmu_new,
@ -1813,7 +1813,7 @@ nv106_chipset = {
.ibus = gk104_ibus_new,
.imem = nv50_instmem_new,
.ltc = gk104_ltc_new,
// .mc = gk20a_mc_new,
.mc = gk20a_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gk208_pmu_new,
@ -1848,7 +1848,7 @@ nv108_chipset = {
.ibus = gk104_ibus_new,
.imem = nv50_instmem_new,
.ltc = gk104_ltc_new,
// .mc = gk20a_mc_new,
.mc = gk20a_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gk208_pmu_new,
@ -1883,7 +1883,7 @@ nv117_chipset = {
.ibus = gk104_ibus_new,
.imem = nv50_instmem_new,
.ltc = gm107_ltc_new,
// .mc = gk20a_mc_new,
.mc = gk20a_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gk208_pmu_new,
@ -1912,7 +1912,7 @@ nv124_chipset = {
.ibus = gk104_ibus_new,
.imem = nv50_instmem_new,
.ltc = gm107_ltc_new,
// .mc = gk20a_mc_new,
.mc = gk20a_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gk208_pmu_new,
@ -1941,7 +1941,7 @@ nv126_chipset = {
.ibus = gk104_ibus_new,
.imem = nv50_instmem_new,
.ltc = gm107_ltc_new,
// .mc = gk20a_mc_new,
.mc = gk20a_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gk208_pmu_new,
@ -1966,7 +1966,7 @@ nv12b_chipset = {
.ibus = gk20a_ibus_new,
.imem = gk20a_instmem_new,
.ltc = gm107_ltc_new,
// .mc = gk20a_mc_new,
.mc = gk20a_mc_new,
// .mmu = gf100_mmu_new,
// .mmu = gf100_mmu_new,
// .timer = gk20a_timer_new,

9
drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
View File

@ -30,7 +30,6 @@ gf100_identify(struct nvkm_device *device)
case 0xc0:
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
@ -50,7 +49,6 @@ gf100_identify(struct nvkm_device *device)
case 0xc4:
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
@ -70,7 +68,6 @@ gf100_identify(struct nvkm_device *device)
case 0xc3:
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
@ -89,7 +86,6 @@ gf100_identify(struct nvkm_device *device)
case 0xce:
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
@ -109,7 +105,6 @@ gf100_identify(struct nvkm_device *device)
case 0xcf:
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
@ -128,7 +123,6 @@ gf100_identify(struct nvkm_device *device)
case 0xc1:
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
@ -147,7 +141,6 @@ gf100_identify(struct nvkm_device *device)
case 0xc8:
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
@ -167,7 +160,6 @@ gf100_identify(struct nvkm_device *device)
case 0xd9:
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
@ -186,7 +178,6 @@ gf100_identify(struct nvkm_device *device)
case 0xd7:
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;

8
drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
View File

@ -30,7 +30,6 @@ gk104_identify(struct nvkm_device *device)
case 0xe4:
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass;
@ -51,7 +50,6 @@ gk104_identify(struct nvkm_device *device)
case 0xe7:
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
@ -72,7 +70,6 @@ gk104_identify(struct nvkm_device *device)
case 0xe6:
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass;
@ -91,7 +88,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
break;
case 0xea:
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
@ -106,7 +102,6 @@ gk104_identify(struct nvkm_device *device)
case 0xf0:
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass;
@ -127,7 +122,6 @@ gk104_identify(struct nvkm_device *device)
case 0xf1:
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass;
@ -148,7 +142,6 @@ gk104_identify(struct nvkm_device *device)
case 0x106:
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
@ -168,7 +161,6 @@ gk104_identify(struct nvkm_device *device)
case 0x108:
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;

4
drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
View File

@ -30,7 +30,6 @@ gm100_identify(struct nvkm_device *device)
case 0x117:
device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
@ -61,7 +60,6 @@ gm100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass;
#endif
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
@ -89,7 +87,6 @@ gm100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass;
#endif
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
@ -112,7 +109,6 @@ gm100_identify(struct nvkm_device *device)
break;
case 0x12b:
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;

2
drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
View File

@ -28,7 +28,6 @@ nv04_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x04:
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -38,7 +37,6 @@ nv04_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x05:
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;

8
drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
View File

@ -28,7 +28,6 @@ nv10_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x10:
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -36,7 +35,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x15:
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -46,7 +44,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x16:
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -56,7 +53,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x1a:
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -66,7 +62,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x11:
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -76,7 +71,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x17:
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -86,7 +80,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x1f:
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -96,7 +89,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x18:
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;

4
drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
View File

@ -28,7 +28,6 @@ nv20_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x20:
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -38,7 +37,6 @@ nv20_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x25:
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -48,7 +46,6 @@ nv20_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x28:
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -58,7 +55,6 @@ nv20_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x2a:
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;

5
drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
View File

@ -28,7 +28,6 @@ nv30_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x30:
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -38,7 +37,6 @@ nv30_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x35:
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -48,7 +46,6 @@ nv30_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x31:
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -59,7 +56,6 @@ nv30_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x36:
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -70,7 +66,6 @@ nv30_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x34:
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;

16
drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
View File

@ -29,7 +29,6 @@ nv40_identify(struct nvkm_device *device)
switch (device->chipset) {
case 0x40:
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -43,7 +42,6 @@ nv40_identify(struct nvkm_device *device)
break;
case 0x41:
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -57,7 +55,6 @@ nv40_identify(struct nvkm_device *device)
break;
case 0x42:
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -71,7 +68,6 @@ nv40_identify(struct nvkm_device *device)
break;
case 0x43:
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -85,7 +81,6 @@ nv40_identify(struct nvkm_device *device)
break;
case 0x45:
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -99,7 +94,6 @@ nv40_identify(struct nvkm_device *device)
break;
case 0x47:
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -113,7 +107,6 @@ nv40_identify(struct nvkm_device *device)
break;
case 0x49:
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -127,7 +120,6 @@ nv40_identify(struct nvkm_device *device)
break;
case 0x4b:
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -141,7 +133,6 @@ nv40_identify(struct nvkm_device *device)
break;
case 0x44:
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -155,7 +146,6 @@ nv40_identify(struct nvkm_device *device)
break;
case 0x46:
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -169,7 +159,6 @@ nv40_identify(struct nvkm_device *device)
break;
case 0x4a:
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -183,7 +172,6 @@ nv40_identify(struct nvkm_device *device)
break;
case 0x4c:
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -197,7 +185,6 @@ nv40_identify(struct nvkm_device *device)
break;
case 0x4e:
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -211,7 +198,6 @@ nv40_identify(struct nvkm_device *device)
break;
case 0x63:
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -225,7 +211,6 @@ nv40_identify(struct nvkm_device *device)
break;
case 0x67:
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -239,7 +224,6 @@ nv40_identify(struct nvkm_device *device)
break;
case 0x68:
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;

14
drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
View File

@ -30,7 +30,6 @@ nv50_identify(struct nvkm_device *device)
case 0x50:
device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -45,7 +44,6 @@ nv50_identify(struct nvkm_device *device)
case 0x84:
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -63,7 +61,6 @@ nv50_identify(struct nvkm_device *device)
case 0x86:
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -81,7 +78,6 @@ nv50_identify(struct nvkm_device *device)
case 0x92:
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -99,7 +95,6 @@ nv50_identify(struct nvkm_device *device)
case 0x94:
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g94_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -117,7 +112,6 @@ nv50_identify(struct nvkm_device *device)
case 0x96:
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g94_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -135,7 +129,6 @@ nv50_identify(struct nvkm_device *device)
case 0x98:
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -153,7 +146,6 @@ nv50_identify(struct nvkm_device *device)
case 0xa0:
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -171,7 +163,6 @@ nv50_identify(struct nvkm_device *device)
case 0xaa:
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -189,7 +180,6 @@ nv50_identify(struct nvkm_device *device)
case 0xac:
device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -207,7 +197,6 @@ nv50_identify(struct nvkm_device *device)
case 0xa3:
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
@ -227,7 +216,6 @@ nv50_identify(struct nvkm_device *device)
case 0xa5:
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
@ -246,7 +234,6 @@ nv50_identify(struct nvkm_device *device)
case 0xa8:
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
@ -265,7 +252,6 @@ nv50_identify(struct nvkm_device *device)
case 0xaf:
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c
View File

@ -1239,7 +1239,7 @@ gf100_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
struct nvkm_device *device = gr->base.engine.subdev.device;
const struct gf100_grctx_func *grctx = gr->func->grctx;
nvkm_mc(gr)->unk260(nvkm_mc(gr), 0);
nvkm_mc_unk260(device->mc, 0);
gf100_gr_mmio(gr, grctx->hub);
gf100_gr_mmio(gr, grctx->gpc);
@ -1263,7 +1263,7 @@ gf100_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
gf100_gr_icmd(gr, grctx->icmd);
nvkm_wr32(device, 0x404154, 0x00000400);
gf100_gr_mthd(gr, grctx->mthd);
nvkm_mc(gr)->unk260(nvkm_mc(gr), 1);
nvkm_mc_unk260(device->mc, 1);
}
int

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c
View File

@ -223,7 +223,7 @@ gf117_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
const struct gf100_grctx_func *grctx = gr->func->grctx;
int i;
nvkm_mc(gr)->unk260(nvkm_mc(gr), 0);
nvkm_mc_unk260(device->mc, 0);
gf100_gr_mmio(gr, grctx->hub);
gf100_gr_mmio(gr, grctx->gpc);
@ -250,7 +250,7 @@ gf117_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
gf100_gr_icmd(gr, grctx->icmd);
nvkm_wr32(device, 0x404154, 0x00000400);
gf100_gr_mthd(gr, grctx->mthd);
nvkm_mc(gr)->unk260(nvkm_mc(gr), 1);
nvkm_mc_unk260(device->mc, 1);
}
const struct gf100_grctx_func

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c
View File

@ -958,7 +958,7 @@ gk104_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
const struct gf100_grctx_func *grctx = gr->func->grctx;
int i;
nvkm_mc(gr)->unk260(nvkm_mc(gr), 0);
nvkm_mc_unk260(device->mc, 0);
gf100_gr_mmio(gr, grctx->hub);
gf100_gr_mmio(gr, grctx->gpc);
@ -988,7 +988,7 @@ gk104_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
gf100_gr_icmd(gr, grctx->icmd);
nvkm_wr32(device, 0x404154, 0x00000400);
gf100_gr_mthd(gr, grctx->mthd);
nvkm_mc(gr)->unk260(nvkm_mc(gr), 1);
nvkm_mc_unk260(device->mc, 1);
nvkm_mask(device, 0x418800, 0x00200000, 0x00200000);
nvkm_mask(device, 0x41be10, 0x00800000, 0x00800000);

8
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
View File

@ -1339,12 +1339,12 @@ gf100_gr_init_ctxctl(struct gf100_gr *gr)
if (gr->firmware) {
/* load fuc microcode */
nvkm_mc(gr)->unk260(nvkm_mc(gr), 0);
nvkm_mc_unk260(device->mc, 0);
gf100_gr_init_fw(gr, 0x409000, &gr->fuc409c,
&gr->fuc409d);
gf100_gr_init_fw(gr, 0x41a000, &gr->fuc41ac,
&gr->fuc41ad);
nvkm_mc(gr)->unk260(nvkm_mc(gr), 1);
nvkm_mc_unk260(device->mc, 1);
/* start both of them running */
nvkm_wr32(device, 0x409840, 0xffffffff);
@ -1439,7 +1439,7 @@ gf100_gr_init_ctxctl(struct gf100_gr *gr)
}
/* load HUB microcode */
nvkm_mc(gr)->unk260(nvkm_mc(gr), 0);
nvkm_mc_unk260(device->mc, 0);
nvkm_wr32(device, 0x4091c0, 0x01000000);
for (i = 0; i < oclass->fecs.ucode->data.size / 4; i++)
nvkm_wr32(device, 0x4091c4, oclass->fecs.ucode->data.data[i]);
@ -1462,7 +1462,7 @@ gf100_gr_init_ctxctl(struct gf100_gr *gr)
nvkm_wr32(device, 0x41a188, i >> 6);
nvkm_wr32(device, 0x41a184, oclass->gpccs.ucode->code.data[i]);
}
nvkm_mc(gr)->unk260(nvkm_mc(gr), 1);
nvkm_mc_unk260(device->mc, 1);
/* load register lists */
gf100_gr_init_csdata(gr, grctx->hub, 0x409000, 0x000, 0x000000);

83
drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c
View File

@ -25,12 +25,11 @@
#include <core/option.h>
static inline void
void
nvkm_mc_unk260(struct nvkm_mc *mc, u32 data)
{
const struct nvkm_mc_oclass *impl = (void *)nv_oclass(mc);
if (impl->unk260)
impl->unk260(mc, data);
if (mc->func->unk260)
mc->func->unk260(mc, data);
}
static inline u32
@ -49,8 +48,7 @@ nvkm_mc_intr(int irq, void *arg)
struct nvkm_mc *mc = arg;
struct nvkm_subdev *subdev = &mc->subdev;
struct nvkm_device *device = subdev->device;
const struct nvkm_mc_oclass *oclass = (void *)nv_object(mc)->oclass;
const struct nvkm_mc_intr *map = oclass->intr;
const struct nvkm_mc_intr *map = mc->func->intr;
struct nvkm_subdev *unit;
u32 intr;
@ -58,13 +56,13 @@ nvkm_mc_intr(int irq, void *arg)
nvkm_rd32(device, 0x000140);
intr = nvkm_mc_intr_mask(mc);
if (mc->use_msi)
oclass->msi_rearm(mc);
mc->func->msi_rearm(mc);
if (intr) {
u32 stat = intr = nvkm_mc_intr_mask(mc);
while (map->stat) {
if (intr & map->stat) {
unit = nvkm_subdev(mc, map->unit);
unit = nvkm_device_subdev(device, map->unit);
if (unit)
nvkm_subdev_intr(unit);
stat &= ~map->stat;
@ -80,54 +78,62 @@ nvkm_mc_intr(int irq, void *arg)
return intr ? IRQ_HANDLED : IRQ_NONE;
}
int
_nvkm_mc_fini(struct nvkm_object *object, bool suspend)
static int
nvkm_mc_fini(struct nvkm_subdev *subdev, bool suspend)
{
struct nvkm_mc *mc = (void *)object;
struct nvkm_device *device = mc->subdev.device;
nvkm_wr32(device, 0x000140, 0x00000000);
return nvkm_subdev_fini_old(&mc->subdev, suspend);
nvkm_wr32(subdev->device, 0x000140, 0x00000000);
return 0;
}
int
_nvkm_mc_init(struct nvkm_object *object)
static int
nvkm_mc_oneinit(struct nvkm_subdev *subdev)
{
struct nvkm_mc *mc = (void *)object;
struct nvkm_mc *mc = nvkm_mc(subdev);
return request_irq(mc->irq, nvkm_mc_intr, IRQF_SHARED, "nvkm", mc);
}
static int
nvkm_mc_init(struct nvkm_subdev *subdev)
{
struct nvkm_mc *mc = nvkm_mc(subdev);
struct nvkm_device *device = mc->subdev.device;
int ret = nvkm_subdev_init_old(&mc->subdev);
if (ret)
return ret;
if (mc->func->init)
mc->func->init(mc);
nvkm_wr32(device, 0x000140, 0x00000001);
return 0;
}
void
_nvkm_mc_dtor(struct nvkm_object *object)
static void *
nvkm_mc_dtor(struct nvkm_subdev *subdev)
{
struct nvkm_mc *mc = (void *)object;
struct nvkm_mc *mc = nvkm_mc(subdev);
struct nvkm_device *device = mc->subdev.device;
free_irq(mc->irq, mc);
if (mc->use_msi)
pci_disable_msi(device->pdev);
nvkm_subdev_destroy(&mc->subdev);
return mc;
}
static const struct nvkm_subdev_func
nvkm_mc = {
.dtor = nvkm_mc_dtor,
.oneinit = nvkm_mc_oneinit,
.init = nvkm_mc_init,
.fini = nvkm_mc_fini,
};
int
nvkm_mc_create_(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *bclass, int length, void **pobject)
nvkm_mc_new_(const struct nvkm_mc_func *func, struct nvkm_device *device,
int index, struct nvkm_mc **pmc)
{
const struct nvkm_mc_oclass *oclass = (void *)bclass;
struct nvkm_device *device = (void *)parent;
struct nvkm_mc *mc;
int ret;
ret = nvkm_subdev_create_(parent, engine, bclass, 0, "PMC",
"master", length, pobject);
mc = *pobject;
if (ret)
return ret;
if (!(mc = *pmc = kzalloc(sizeof(*mc), GFP_KERNEL)))
return -ENOMEM;
mc->unk260 = nvkm_mc_unk260;
nvkm_subdev_ctor(&nvkm_mc, device, index, 0, &mc->subdev);
mc->func = func;
if (nv_device_is_pci(device)) {
switch (device->pdev->device & 0x0ff0) {
@ -149,11 +155,11 @@ nvkm_mc_create_(struct nvkm_object *parent, struct nvkm_object *engine,
mc->use_msi = nvkm_boolopt(device->cfgopt, "NvMSI",
mc->use_msi);
if (mc->use_msi && oclass->msi_rearm) {
if (mc->use_msi && mc->func->msi_rearm) {
mc->use_msi = pci_enable_msi(device->pdev) == 0;
if (mc->use_msi) {
nvkm_debug(&mc->subdev, "MSI enabled\n");
oclass->msi_rearm(mc);
mc->func->msi_rearm(mc);
}
} else {
mc->use_msi = false;
@ -164,10 +170,5 @@ nvkm_mc_create_(struct nvkm_object *parent, struct nvkm_object *engine,
if (ret < 0)
return ret;
mc->irq = ret;
ret = request_irq(mc->irq, nvkm_mc_intr, IRQF_SHARED, "nvkm", mc);
if (ret < 0)
return ret;
return 0;
}

22
drivers/gpu/drm/nouveau/nvkm/subdev/mc/g94.c
View File

@ -21,17 +21,17 @@
*
* Authors: Ben Skeggs
*/
#include "nv04.h"
#include "priv.h"
struct nvkm_oclass *
g94_mc_oclass = &(struct nvkm_mc_oclass) {
.base.handle = NV_SUBDEV(MC, 0x94),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_mc_ctor,
.dtor = _nvkm_mc_dtor,
.init = nv50_mc_init,
.fini = _nvkm_mc_fini,
},
static const struct nvkm_mc_func
g94_mc = {
.init = nv50_mc_init,
.intr = nv50_mc_intr,
.msi_rearm = nv40_mc_msi_rearm,
}.base;
};
int
g94_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc)
{
return nvkm_mc_new_(&g94_mc, device, index, pmc);
}

22
drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.c
View File

@ -21,7 +21,7 @@
*
* Authors: Ben Skeggs
*/
#include "nv04.h"
#include "priv.h"
static const struct nvkm_mc_intr
g98_mc_intr[] = {
@ -44,15 +44,15 @@ g98_mc_intr[] = {
{},
};
struct nvkm_oclass *
g98_mc_oclass = &(struct nvkm_mc_oclass) {
.base.handle = NV_SUBDEV(MC, 0x98),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_mc_ctor,
.dtor = _nvkm_mc_dtor,
.init = nv50_mc_init,
.fini = _nvkm_mc_fini,
},
static const struct nvkm_mc_func
g98_mc = {
.init = nv50_mc_init,
.intr = g98_mc_intr,
.msi_rearm = nv40_mc_msi_rearm,
}.base;
};
int
g98_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc)
{
return nvkm_mc_new_(&g98_mc, device, index, pmc);
}

22
drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c
View File

@ -21,7 +21,7 @@
*
* Authors: Ben Skeggs
*/
#include "nv04.h"
#include "priv.h"
const struct nvkm_mc_intr
gf100_mc_intr[] = {
@ -60,16 +60,16 @@ gf100_mc_unk260(struct nvkm_mc *mc, u32 data)
nvkm_wr32(mc->subdev.device, 0x000260, data);
}
struct nvkm_oclass *
gf100_mc_oclass = &(struct nvkm_mc_oclass) {
.base.handle = NV_SUBDEV(MC, 0xc0),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_mc_ctor,
.dtor = _nvkm_mc_dtor,
.init = nv50_mc_init,
.fini = _nvkm_mc_fini,
},
static const struct nvkm_mc_func
gf100_mc = {
.init = nv50_mc_init,
.intr = gf100_mc_intr,
.msi_rearm = gf100_mc_msi_rearm,
.unk260 = gf100_mc_unk260,
}.base;
};
int
gf100_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc)
{
return nvkm_mc_new_(&gf100_mc, device, index, pmc);
}

22
drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf106.c
View File

@ -21,18 +21,18 @@
*
* Authors: Ben Skeggs
*/
#include "nv04.h"
#include "priv.h"
struct nvkm_oclass *
gf106_mc_oclass = &(struct nvkm_mc_oclass) {
.base.handle = NV_SUBDEV(MC, 0xc3),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_mc_ctor,
.dtor = _nvkm_mc_dtor,
.init = nv50_mc_init,
.fini = _nvkm_mc_fini,
},
static const struct nvkm_mc_func
gf106_mc = {
.init = nv50_mc_init,
.intr = gf100_mc_intr,
.msi_rearm = nv40_mc_msi_rearm,
.unk260 = gf100_mc_unk260,
}.base;
};
int
gf106_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc)
{
return nvkm_mc_new_(&gf106_mc, device, index, pmc);
}

22
drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk20a.c
View File

@ -21,17 +21,17 @@
*
* Authors: Ben Skeggs
*/
#include "nv04.h"
#include "priv.h"
struct nvkm_oclass *
gk20a_mc_oclass = &(struct nvkm_mc_oclass) {
.base.handle = NV_SUBDEV(MC, 0xea),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_mc_ctor,
.dtor = _nvkm_mc_dtor,
.init = nv50_mc_init,
.fini = _nvkm_mc_fini,
},
static const struct nvkm_mc_func
gk20a_mc = {
.init = nv50_mc_init,
.intr = gf100_mc_intr,
.msi_rearm = nv40_mc_msi_rearm,
}.base;
};
int
gk20a_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc)
{
return nvkm_mc_new_(&gk20a_mc, device, index, pmc);
}

42
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c
View File

@ -21,7 +21,7 @@
*
* Authors: Ben Skeggs
*/
#include "nv04.h"
#include "priv.h"
const struct nvkm_mc_intr
nv04_mc_intr[] = {
@ -38,42 +38,22 @@ nv04_mc_intr[] = {
{}
};
int
nv04_mc_init(struct nvkm_object *object)
void
nv04_mc_init(struct nvkm_mc *mc)
{
struct nvkm_mc *mc = (void *)object;
struct nvkm_device *device = mc->subdev.device;
nvkm_wr32(device, 0x000200, 0xffffffff); /* everything enabled */
nvkm_wr32(device, 0x001850, 0x00000001); /* disable rom access */
return nvkm_mc_init(mc);
}
static const struct nvkm_mc_func
nv04_mc = {
.init = nv04_mc_init,
.intr = nv04_mc_intr,
};
int
nv04_mc_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
nv04_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc)
{
struct nvkm_mc *mc;
int ret;
ret = nvkm_mc_create(parent, engine, oclass, &mc);
*pobject = nv_object(mc);
if (ret)
return ret;
return 0;
return nvkm_mc_new_(&nv04_mc, device, index, pmc);
}
struct nvkm_oclass *
nv04_mc_oclass = &(struct nvkm_mc_oclass) {
.base.handle = NV_SUBDEV(MC, 0x04),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_mc_ctor,
.dtor = _nvkm_mc_dtor,
.init = nv04_mc_init,
.fini = _nvkm_mc_fini,
},
.intr = nv04_mc_intr,
}.base;

16
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.h
View File

@ -1,16 +0,0 @@
#ifndef __NVKM_MC_NV04_H__
#define __NVKM_MC_NV04_H__
#include "priv.h"
int nv04_mc_ctor(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, void *, u32,
struct nvkm_object **);
extern const struct nvkm_mc_intr nv04_mc_intr[];
int nv04_mc_init(struct nvkm_object *);
void nv40_mc_msi_rearm(struct nvkm_mc *);
int nv44_mc_init(struct nvkm_object *object);
int nv50_mc_init(struct nvkm_object *);
extern const struct nvkm_mc_intr nv50_mc_intr[];
extern const struct nvkm_mc_intr gf100_mc_intr[];
#endif

22
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv40.c
View File

@ -21,7 +21,7 @@
*
* Authors: Ben Skeggs
*/
#include "nv04.h"
#include "priv.h"
void
nv40_mc_msi_rearm(struct nvkm_mc *mc)
@ -29,15 +29,15 @@ nv40_mc_msi_rearm(struct nvkm_mc *mc)
nvkm_wr08(mc->subdev.device, 0x088068, 0xff);
}
struct nvkm_oclass *
nv40_mc_oclass = &(struct nvkm_mc_oclass) {
.base.handle = NV_SUBDEV(MC, 0x40),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_mc_ctor,
.dtor = _nvkm_mc_dtor,
.init = nv04_mc_init,
.fini = _nvkm_mc_fini,
},
static const struct nvkm_mc_func
nv40_mc = {
.init = nv04_mc_init,
.intr = nv04_mc_intr,
.msi_rearm = nv40_mc_msi_rearm,
}.base;
};
int
nv40_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc)
{
return nvkm_mc_new_(&nv40_mc, device, index, pmc);
}

29
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.c
View File

@ -21,12 +21,11 @@
*
* Authors: Ben Skeggs
*/
#include "nv04.h"
#include "priv.h"
int
nv44_mc_init(struct nvkm_object *object)
void
nv44_mc_init(struct nvkm_mc *mc)
{
struct nvkm_mc *mc = (void *)object;
struct nvkm_device *device = mc->subdev.device;
u32 tmp = nvkm_rd32(device, 0x10020c);
@ -36,19 +35,17 @@ nv44_mc_init(struct nvkm_object *object)
nvkm_wr32(device, 0x001704, 0);
nvkm_wr32(device, 0x001708, 0);
nvkm_wr32(device, 0x00170c, tmp);
return nvkm_mc_init(mc);
}
struct nvkm_oclass *
nv44_mc_oclass = &(struct nvkm_mc_oclass) {
.base.handle = NV_SUBDEV(MC, 0x44),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_mc_ctor,
.dtor = _nvkm_mc_dtor,
.init = nv44_mc_init,
.fini = _nvkm_mc_fini,
},
static const struct nvkm_mc_func
nv44_mc = {
.init = nv44_mc_init,
.intr = nv04_mc_intr,
.msi_rearm = nv40_mc_msi_rearm,
}.base;
};
int
nv44_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc)
{
return nvkm_mc_new_(&nv44_mc, device, index, pmc);
}

22
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv4c.c
View File

@ -21,16 +21,16 @@
*
* Authors: Ilia Mirkin
*/
#include "nv04.h"
#include "priv.h"
struct nvkm_oclass *
nv4c_mc_oclass = &(struct nvkm_mc_oclass) {
.base.handle = NV_SUBDEV(MC, 0x4c),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_mc_ctor,
.dtor = _nvkm_mc_dtor,
.init = nv44_mc_init,
.fini = _nvkm_mc_fini,
},
static const struct nvkm_mc_func
nv4c_mc = {
.init = nv44_mc_init,
.intr = nv04_mc_intr,
}.base;
};
int
nv4c_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc)
{
return nvkm_mc_new_(&nv4c_mc, device, index, pmc);
}

28
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c
View File

@ -21,7 +21,7 @@
*
* Authors: Ben Skeggs
*/
#include "nv04.h"
#include "priv.h"
const struct nvkm_mc_intr
nv50_mc_intr[] = {
@ -48,24 +48,22 @@ nv50_mc_msi_rearm(struct nvkm_mc *mc)
pci_write_config_byte(device->pdev, 0x68, 0xff);
}
int
nv50_mc_init(struct nvkm_object *object)
void
nv50_mc_init(struct nvkm_mc *mc)
{
struct nvkm_mc *mc = (void *)object;
struct nvkm_device *device = mc->subdev.device;
nvkm_wr32(device, 0x000200, 0xffffffff); /* everything on */
return nvkm_mc_init(mc);
}
struct nvkm_oclass *
nv50_mc_oclass = &(struct nvkm_mc_oclass) {
.base.handle = NV_SUBDEV(MC, 0x50),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_mc_ctor,
.dtor = _nvkm_mc_dtor,
.init = nv50_mc_init,
.fini = _nvkm_mc_fini,
},
static const struct nvkm_mc_func
nv50_mc = {
.init = nv50_mc_init,
.intr = nv50_mc_intr,
.msi_rearm = nv50_mc_msi_rearm,
}.base;
};
int
nv50_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc)
{
return nvkm_mc_new_(&nv50_mc, device, index, pmc);
}

35
drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h
View File

@ -1,36 +1,33 @@
#ifndef __NVKM_MC_PRIV_H__
#define __NVKM_MC_PRIV_H__
#define nvkm_mc(p) container_of((p), struct nvkm_mc, subdev)
#include <subdev/mc.h>
#define nvkm_mc_create(p,e,o,d) \
nvkm_mc_create_((p), (e), (o), sizeof(**d), (void **)d)
#define nvkm_mc_destroy(p) ({ \
struct nvkm_mc *pmc = (p); _nvkm_mc_dtor(nv_object(pmc)); \
})
#define nvkm_mc_init(p) ({ \
struct nvkm_mc *pmc = (p); _nvkm_mc_init(nv_object(pmc)); \
})
#define nvkm_mc_fini(p,s) ({ \
struct nvkm_mc *pmc = (p); _nvkm_mc_fini(nv_object(pmc), (s)); \
})
int nvkm_mc_create_(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, int, void **);
void _nvkm_mc_dtor(struct nvkm_object *);
int _nvkm_mc_init(struct nvkm_object *);
int _nvkm_mc_fini(struct nvkm_object *, bool);
int nvkm_mc_new_(const struct nvkm_mc_func *, struct nvkm_device *,
int index, struct nvkm_mc **);
struct nvkm_mc_intr {
u32 stat;
u32 unit;
};
struct nvkm_mc_oclass {
struct nvkm_oclass base;
struct nvkm_mc_func {
void (*init)(struct nvkm_mc *);
const struct nvkm_mc_intr *intr;
void (*msi_rearm)(struct nvkm_mc *);
void (*unk260)(struct nvkm_mc *, u32);
};
void nv04_mc_init(struct nvkm_mc *);
extern const struct nvkm_mc_intr nv04_mc_intr[];
void nv40_mc_msi_rearm(struct nvkm_mc *);
void nv44_mc_init(struct nvkm_mc *);
void nv50_mc_init(struct nvkm_mc *);
extern const struct nvkm_mc_intr nv50_mc_intr[];
extern const struct nvkm_mc_intr gf100_mc_intr[];
void gf100_mc_unk260(struct nvkm_mc *, u32);
#endif