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Merge tag 'amd-drm-next-5.20-2022-07-29' of https://gitlab.freedesktop.org/agd5f/linux into drm-next

Browse Source 
amd-drm-next-5.20-2022-07-29:

amdgpu:
- Misc spelling and grammar fixes
- DC whitespace cleanups
- ACP smatch fix
- GFX 11.0 updates
- PSP 13.0 updates
- VCN 4.0 updates
- DC FP fix for PPC64
- Misc bug fixes

amdkfd:
- SVM fixes

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220729202742.6636-1-alexander.deucher@amd.com
This commit is contained in:
Dave Airlie 2022-08-03 14:00:18 +10:00
commit 5493ee1919
62 changed files with 2176 additions and 372 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/drm/amd/amdgpu/Makefile
View File

@ -115,7 +115,8 @@ amdgpu-y += \
psp_v11_0.o \
psp_v11_0_8.o \
psp_v12_0.o \
psp_v13_0.o
psp_v13_0.o \
psp_v13_0_4.o
# add DCE block
amdgpu-y += \

2
drivers/gpu/drm/amd/amdgpu/amdgpu.h
View File

@ -1020,7 +1020,7 @@ struct amdgpu_device {
bool psp_sysfs_en;
/* Chip product information */
char product_number[16];
char product_number[20];
char product_name[AMDGPU_PRODUCT_NAME_LEN];
char serial[20];

8
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
View File

@ -390,14 +390,6 @@ static int acp_hw_init(void *handle)
i2s_pdata[2].i2s_reg_comp1 = ACP_BT_COMP1_REG_OFFSET;
i2s_pdata[2].i2s_reg_comp2 = ACP_BT_COMP2_REG_OFFSET;
i2s_pdata[3].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
switch (adev->asic_type) {
case CHIP_STONEY:
i2s_pdata[3].quirks |= DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
break;
default:
break;
}
adev->acp.acp_res[0].name = "acp2x_dma";
adev->acp.acp_res[0].flags = IORESOURCE_MEM;
adev->acp.acp_res[0].start = acp_base;

7
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
View File

@ -172,6 +172,9 @@ int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev,
struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context,
struct mm_struct *mm,
struct svm_range_bo *svm_bo);
#if defined(CONFIG_DEBUG_FS)
int kfd_debugfs_kfd_mem_limits(struct seq_file *m, void *data);
#endif
#if IS_ENABLED(CONFIG_HSA_AMD)
bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm);
struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f);
@ -305,6 +308,10 @@ bool amdgpu_amdkfd_bo_mapped_to_dev(struct amdgpu_device *adev, struct kgd_mem *
void amdgpu_amdkfd_block_mmu_notifications(void *p);
int amdgpu_amdkfd_criu_resume(void *p);
bool amdgpu_amdkfd_ras_query_utcl2_poison_status(struct amdgpu_device *adev);
int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
uint64_t size, u32 alloc_flag);
void amdgpu_amdkfd_unreserve_mem_limit(struct amdgpu_device *adev,
uint64_t size, u32 alloc_flag);
#if IS_ENABLED(CONFIG_HSA_AMD)
void amdgpu_amdkfd_gpuvm_init_mem_limits(void);

9
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
View File

@ -159,11 +159,14 @@ static void amdkfd_fence_release(struct dma_fence *f)
}
/**
* amdkfd_fence_check_mm - Check if @mm is same as that of the fence @f
* if same return TRUE else return FALSE.
* amdkfd_fence_check_mm - Check whether to prevent eviction of @f by @mm
*
* @f: [IN] fence
* @mm: [IN] mm that needs to be verified
*
* Check if @mm is same as that of the fence @f, if same return TRUE else
* return FALSE.
* For svm bo, which support vram overcommitment, always return FALSE.
*/
bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm)
{
@ -171,7 +174,7 @@ bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm)
if (!fence)
return false;
else if (fence->mm == mm)
else if (fence->mm == mm && !fence->svm_bo)
return true;
return false;

51
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
View File

@ -129,7 +129,7 @@ void amdgpu_amdkfd_reserve_system_mem(uint64_t size)
*
* Return: returns -ENOMEM in case of error, ZERO otherwise
*/
static int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
uint64_t size, u32 alloc_flag)
{
uint64_t reserved_for_pt =
@ -169,7 +169,7 @@ static int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
kfd_mem_limit.max_system_mem_limit && !no_system_mem_limit) ||
(kfd_mem_limit.ttm_mem_used + ttm_mem_needed >
kfd_mem_limit.max_ttm_mem_limit) ||
(adev->kfd.vram_used + vram_needed >
(adev && adev->kfd.vram_used + vram_needed >
adev->gmc.real_vram_size -
atomic64_read(&adev->vram_pin_size) -
reserved_for_pt)) {
@ -180,7 +180,10 @@ static int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
/* Update memory accounting by decreasing available system
* memory, TTM memory and GPU memory as computed above
*/
adev->kfd.vram_used += vram_needed;
WARN_ONCE(vram_needed && !adev,
"adev reference can't be null when vram is used");
if (adev)
adev->kfd.vram_used += vram_needed;
kfd_mem_limit.system_mem_used += system_mem_needed;
kfd_mem_limit.ttm_mem_used += ttm_mem_needed;
@ -189,7 +192,7 @@ release:
return ret;
}
static void unreserve_mem_limit(struct amdgpu_device *adev,
void amdgpu_amdkfd_unreserve_mem_limit(struct amdgpu_device *adev,
uint64_t size, u32 alloc_flag)
{
spin_lock(&kfd_mem_limit.mem_limit_lock);
@ -198,7 +201,10 @@ static void unreserve_mem_limit(struct amdgpu_device *adev,
kfd_mem_limit.system_mem_used -= size;
kfd_mem_limit.ttm_mem_used -= size;
} else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
adev->kfd.vram_used -= ALIGN(size, VRAM_ALLOCATION_ALIGN);
WARN_ONCE(!adev,
"adev reference can't be null when alloc mem flags vram is set");
if (adev)
adev->kfd.vram_used -= ALIGN(size, VRAM_ALLOCATION_ALIGN);
} else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
kfd_mem_limit.system_mem_used -= size;
} else if (!(alloc_flag &
@ -207,8 +213,7 @@ static void unreserve_mem_limit(struct amdgpu_device *adev,
pr_err("%s: Invalid BO type %#x\n", __func__, alloc_flag);
goto release;
}
WARN_ONCE(adev->kfd.vram_used < 0,
WARN_ONCE(adev && adev->kfd.vram_used < 0,
"KFD VRAM memory accounting unbalanced");
WARN_ONCE(kfd_mem_limit.ttm_mem_used < 0,
"KFD TTM memory accounting unbalanced");
@ -225,7 +230,7 @@ void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo)
u32 alloc_flags = bo->kfd_bo->alloc_flags;
u64 size = amdgpu_bo_size(bo);
unreserve_mem_limit(adev, size, alloc_flags);
amdgpu_amdkfd_unreserve_mem_limit(adev, size, alloc_flags);
kfree(bo->kfd_bo);
}
@ -773,7 +778,6 @@ kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem,
*bo = gem_to_amdgpu_bo(gobj);
(*bo)->flags |= AMDGPU_GEM_CREATE_PREEMPTIBLE;
(*bo)->parent = amdgpu_bo_ref(mem->bo);
return 0;
}
@ -1749,7 +1753,7 @@ err_node_allow:
/* Don't unreserve system mem limit twice */
goto err_reserve_limit;
err_bo_create:
unreserve_mem_limit(adev, size, flags);
amdgpu_amdkfd_unreserve_mem_limit(adev, size, flags);
err_reserve_limit:
mutex_destroy(&(*mem)->lock);
if (gobj)
@ -1770,6 +1774,7 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
{
struct amdkfd_process_info *process_info = mem->process_info;
unsigned long bo_size = mem->bo->tbo.base.size;
bool use_release_notifier = (mem->bo->kfd_bo == mem);
struct kfd_mem_attachment *entry, *tmp;
struct bo_vm_reservation_context ctx;
struct ttm_validate_buffer *bo_list_entry;
@ -1861,6 +1866,13 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
*/
drm_gem_object_put(&mem->bo->tbo.base);
/*
* For kgd_mem allocated in amdgpu_amdkfd_gpuvm_import_dmabuf(),
* explicitly free it here.
*/
if (!use_release_notifier)
kfree(mem);
return ret;
}
@ -2883,3 +2895,22 @@ bool amdgpu_amdkfd_bo_mapped_to_dev(struct amdgpu_device *adev, struct kgd_mem *
}
return false;
}
#if defined(CONFIG_DEBUG_FS)
int kfd_debugfs_kfd_mem_limits(struct seq_file *m, void *data)
{
spin_lock(&kfd_mem_limit.mem_limit_lock);
seq_printf(m, "System mem used %lldM out of %lluM\n",
(kfd_mem_limit.system_mem_used >> 20),
(kfd_mem_limit.max_system_mem_limit >> 20));
seq_printf(m, "TTM mem used %lldM out of %lluM\n",
(kfd_mem_limit.ttm_mem_used >> 20),
(kfd_mem_limit.max_ttm_mem_limit >> 20));
spin_unlock(&kfd_mem_limit.mem_limit_lock);
return 0;
}
#endif

4
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
View File

@ -4668,7 +4668,6 @@ static int amdgpu_reset_reg_dumps(struct amdgpu_device *adev)
int i;
lockdep_assert_held(&adev->reset_domain->sem);
dump_stack();
for (i = 0; i < adev->num_regs; i++) {
adev->reset_dump_reg_value[i] = RREG32(adev->reset_dump_reg_list[i]);
@ -5300,6 +5299,9 @@ skip_hw_reset:
drm_sched_start(&ring->sched, !tmp_adev->asic_reset_res);
}
if (adev->enable_mes)
amdgpu_mes_self_test(tmp_adev);
if (!drm_drv_uses_atomic_modeset(adev_to_drm(tmp_adev)) && !job_signaled) {
drm_helper_resume_force_mode(adev_to_drm(tmp_adev));
}

4
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
View File

@ -1630,12 +1630,14 @@ static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev)
case IP_VERSION(13, 0, 1):
case IP_VERSION(13, 0, 2):
case IP_VERSION(13, 0, 3):
case IP_VERSION(13, 0, 4):
case IP_VERSION(13, 0, 5):
case IP_VERSION(13, 0, 7):
case IP_VERSION(13, 0, 8):
amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
break;
case IP_VERSION(13, 0, 4):
amdgpu_device_ip_block_add(adev, &psp_v13_0_4_ip_block);
break;
default:
dev_err(adev->dev,
"Failed to add psp ip block(MP0_HWIP:0x%x)\n",

15
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
View File

@ -37,6 +37,7 @@
#include "psp_v11_0_8.h"
#include "psp_v12_0.h"
#include "psp_v13_0.h"
#include "psp_v13_0_4.h"
#include "amdgpu_ras.h"
#include "amdgpu_securedisplay.h"
@ -151,6 +152,10 @@ static int psp_early_init(void *handle)
psp_v13_0_set_psp_funcs(psp);
psp->autoload_supported = true;
break;
case IP_VERSION(13, 0, 4):
psp_v13_0_4_set_psp_funcs(psp);
psp->autoload_supported = true;
break;
default:
return -EINVAL;
}
@ -1292,6 +1297,8 @@ static void psp_xgmi_reflect_topology_info(struct psp_context *psp,
break;
}
amdgpu_put_xgmi_hive(hive);
}
int psp_xgmi_get_topology_info(struct psp_context *psp,
@ -3692,3 +3699,11 @@ const struct amdgpu_ip_block_version psp_v13_0_ip_block = {
.rev = 0,
.funcs = &psp_ip_funcs,
};
const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = {
.type = AMD_IP_BLOCK_TYPE_PSP,
.major = 13,
.minor = 0,
.rev = 4,
.funcs = &psp_ip_funcs,
};

1
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
View File

@ -439,6 +439,7 @@ extern const struct amdgpu_ip_block_version psp_v11_0_ip_block;
extern const struct amdgpu_ip_block_version psp_v11_0_8_ip_block;
extern const struct amdgpu_ip_block_version psp_v12_0_ip_block;
extern const struct amdgpu_ip_block_version psp_v13_0_ip_block;
extern const struct amdgpu_ip_block_version psp_v13_0_4_ip_block;
extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
uint32_t field_val, uint32_t mask, bool check_changed);

8
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
View File

@ -54,6 +54,7 @@
#define FIRMWARE_YELLOW_CARP "amdgpu/yellow_carp_vcn.bin"
#define FIRMWARE_VCN_3_1_2 "amdgpu/vcn_3_1_2.bin"
#define FIRMWARE_VCN4_0_0 "amdgpu/vcn_4_0_0.bin"
#define FIRMWARE_VCN4_0_2 "amdgpu/vcn_4_0_2.bin"
#define FIRMWARE_VCN4_0_4 "amdgpu/vcn_4_0_4.bin"
MODULE_FIRMWARE(FIRMWARE_RAVEN);
@ -74,6 +75,7 @@ MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY);
MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP);
MODULE_FIRMWARE(FIRMWARE_VCN_3_1_2);
MODULE_FIRMWARE(FIRMWARE_VCN4_0_0);
MODULE_FIRMWARE(FIRMWARE_VCN4_0_2);
MODULE_FIRMWARE(FIRMWARE_VCN4_0_4);
static void amdgpu_vcn_idle_work_handler(struct work_struct *work);
@ -185,6 +187,12 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
(adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
adev->vcn.indirect_sram = true;
break;
case IP_VERSION(4, 0, 2):
fw_name = FIRMWARE_VCN4_0_2;
if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
(adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
adev->vcn.indirect_sram = false;
break;
case IP_VERSION(4, 0, 4):
fw_name = FIRMWARE_VCN4_0_4;
if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&

10
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
View File

@ -56,6 +56,8 @@
#define regCGTT_WD_CLK_CTRL 0x5086
#define regCGTT_WD_CLK_CTRL_BASE_IDX 1
#define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1 0x4e7e
#define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1_BASE_IDX 1
MODULE_FIRMWARE("amdgpu/gc_11_0_0_pfp.bin");
MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin");
@ -2765,7 +2767,13 @@ static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
for (i = 0; i < adev->usec_timeout; i++) {
cp_status = RREG32_SOC15(GC, 0, regCP_STAT);
bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS);
if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 1))
bootload_status = RREG32_SOC15(GC, 0,
regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1);
else
bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS);
if ((cp_status == 0) &&
(REG_GET_FIELD(bootload_status,
RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {

32
drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c
View File

@ -26,13 +26,10 @@
#include "gc/gc_11_0_0_offset.h"
#include "gc/gc_11_0_0_sh_mask.h"
#include "gc/gc_11_0_0_default.h"
#include "navi10_enum.h"
#include "soc15_common.h"
#define regGCVM_L2_CNTL3_DEFAULT 0x80100007
#define regGCVM_L2_CNTL4_DEFAULT 0x000000c1
#define regGCVM_L2_CNTL5_DEFAULT 0x00003fe0
static const char *gfxhub_client_ids[] = {
"CB/DB",
"Reserved",
@ -414,12 +411,39 @@ static void gfxhub_v3_0_set_fault_enable_default(struct amdgpu_device *adev,
{
u32 tmp;
/* NO halt CP when page fault */
tmp = RREG32_SOC15(GC, 0, regCP_DEBUG);
tmp = REG_SET_FIELD(tmp, CP_DEBUG, CPG_UTCL1_ERROR_HALT_DISABLE, 1);
WREG32_SOC15(GC, 0, regCP_DEBUG, tmp);
/**
* Set GRBM_GFX_INDEX in broad cast mode
* before programming GL1C_UTCL0_CNTL1 and SQG_CONFIG
*/
WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, regGRBM_GFX_INDEX_DEFAULT);
/**
* Retry respond mode: RETRY
* Error (no retry) respond mode: SUCCESS
*/
tmp = RREG32_SOC15(GC, 0, regGL1C_UTCL0_CNTL1);
tmp = REG_SET_FIELD(tmp, GL1C_UTCL0_CNTL1, RESP_MODE, 0);
tmp = REG_SET_FIELD(tmp, GL1C_UTCL0_CNTL1, RESP_FAULT_MODE, 0x2);
WREG32_SOC15(GC, 0, regGL1C_UTCL0_CNTL1, tmp);
/* These registers are not accessible to VF-SRIOV.
* The PF will program them instead.
*/
if (amdgpu_sriov_vf(adev))
return;
/* Disable SQ XNACK interrupt for all VMIDs */
tmp = RREG32_SOC15(GC, 0, regSQG_CONFIG);
tmp = REG_SET_FIELD(tmp, SQG_CONFIG, XNACK_INTR_MASK,
SQG_CONFIG__XNACK_INTR_MASK_MASK >>
SQG_CONFIG__XNACK_INTR_MASK__SHIFT);
WREG32_SOC15(GC, 0, regSQG_CONFIG, tmp);
tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL);
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);

3
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
View File

@ -1233,7 +1233,8 @@ static int mes_v10_0_late_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
amdgpu_mes_self_test(adev);
if (!amdgpu_in_reset(adev))
amdgpu_mes_self_test(adev);
return 0;
}

3
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
View File

@ -1280,7 +1280,8 @@ static int mes_v11_0_late_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
amdgpu_mes_self_test(adev);
if (!amdgpu_in_reset(adev))
amdgpu_mes_self_test(adev);
return 0;
}

21
drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c
View File

@ -83,6 +83,26 @@ static void nbio_v7_7_sdma_doorbell_range(struct amdgpu_device *adev, int instan
WREG32_PCIE_PORT(reg, doorbell_range);
}
static void nbio_v7_7_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
int doorbell_index, int instance)
{
u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VCN0_DOORBELL_RANGE);
u32 doorbell_range = RREG32_PCIE_PORT(reg);
if (use_doorbell) {
doorbell_range = REG_SET_FIELD(doorbell_range,
GDC0_BIF_VCN0_DOORBELL_RANGE, OFFSET,
doorbell_index);
doorbell_range = REG_SET_FIELD(doorbell_range,
GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 8);
} else {
doorbell_range = REG_SET_FIELD(doorbell_range,
GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 0);
}
WREG32_PCIE_PORT(reg, doorbell_range);
}
static void nbio_v7_7_enable_doorbell_aperture(struct amdgpu_device *adev,
bool enable)
{
@ -238,6 +258,7 @@ const struct amdgpu_nbio_funcs nbio_v7_7_funcs = {
.mc_access_enable = nbio_v7_7_mc_access_enable,
.get_memsize = nbio_v7_7_get_memsize,
.sdma_doorbell_range = nbio_v7_7_sdma_doorbell_range,
.vcn_doorbell_range = nbio_v7_7_vcn_doorbell_range,
.enable_doorbell_aperture = nbio_v7_7_enable_doorbell_aperture,
.enable_doorbell_selfring_aperture = nbio_v7_7_enable_doorbell_selfring_aperture,
.ih_doorbell_range = nbio_v7_7_ih_doorbell_range,

159
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
View File

@ -20,6 +20,8 @@
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include <linux/dev_printk.h>
#include <drm/drm_drv.h>
#include "amdgpu.h"
#include "amdgpu_psp.h"
#include "amdgpu_ucode.h"
@ -58,6 +60,9 @@ MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin");
#define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3
#define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4
/* memory training timeout define */
#define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000
static int psp_v13_0_init_microcode(struct psp_context *psp)
{
struct amdgpu_device *adev = psp->adev;
@ -419,6 +424,159 @@ static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value);
}
static int psp_v13_0_memory_training_send_msg(struct psp_context *psp, int msg)
{
int ret;
int i;
uint32_t data_32;
int max_wait;
struct amdgpu_device *adev = psp->adev;
data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);
WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, data_32);
WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, msg);
max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
for (i = 0; i < max_wait; i++) {
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
0x80000000, 0x80000000, false);
if (ret == 0)
break;
}
if (i < max_wait)
ret = 0;
else
ret = -ETIME;
dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n",
(msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",
(ret == 0) ? "succeed" : "failed",
i, adev->usec_timeout/1000);
return ret;
}
static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t ops)
{
struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
uint32_t *pcache = (uint32_t *)ctx->sys_cache;
struct amdgpu_device *adev = psp->adev;
uint32_t p2c_header[4];
uint32_t sz;
void *buf;
int ret, idx;
if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {
dev_dbg(adev->dev, "Memory training is not supported.\n");
return 0;
} else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) {
dev_err(adev->dev, "Memory training initialization failure.\n");
return -EINVAL;
}
if (psp_v13_0_is_sos_alive(psp)) {
dev_dbg(adev->dev, "SOS is alive, skip memory training.\n");
return 0;
}
amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
dev_dbg(adev->dev, "sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",
pcache[0], pcache[1], pcache[2], pcache[3],
p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]);
if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
dev_dbg(adev->dev, "Short training depends on restore.\n");
ops |= PSP_MEM_TRAIN_RESTORE;
}
if ((ops & PSP_MEM_TRAIN_RESTORE) &&
pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on save.\n");
ops |= PSP_MEM_TRAIN_SAVE;
}
if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
!(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
pcache[3] == p2c_header[3])) {
dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n");
ops |= PSP_MEM_TRAIN_SAVE;
}
if ((ops & PSP_MEM_TRAIN_SAVE) &&
p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n");
ops |= PSP_MEM_TRAIN_SEND_LONG_MSG;
}
if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG;
ops |= PSP_MEM_TRAIN_SAVE;
}
dev_dbg(adev->dev, "Memory training ops:%x.\n", ops);
if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
/*
* Long training will encroach a certain amount on the bottom of VRAM;
* save the content from the bottom of VRAM to system memory
* before training, and restore it after training to avoid
* VRAM corruption.
*/
sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE;
if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) {
dev_err(adev->dev, "visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n",
adev->gmc.visible_vram_size,
adev->mman.aper_base_kaddr);
return -EINVAL;
}
buf = vmalloc(sz);
if (!buf) {
dev_err(adev->dev, "failed to allocate system memory.\n");
return -ENOMEM;
}
if (drm_dev_enter(adev_to_drm(adev), &idx)) {
memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz);
ret = psp_v13_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);
if (ret) {
DRM_ERROR("Send long training msg failed.\n");
vfree(buf);
drm_dev_exit(idx);
return ret;
}
memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
adev->hdp.funcs->flush_hdp(adev, NULL);
vfree(buf);
drm_dev_exit(idx);
} else {
vfree(buf);
return -ENODEV;
}
}
if (ops & PSP_MEM_TRAIN_SAVE) {
amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
}
if (ops & PSP_MEM_TRAIN_RESTORE) {
amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);
}
if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
ret = psp_v13_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ?
PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN);
if (ret) {
dev_err(adev->dev, "send training msg failed.\n");
return ret;
}
}
ctx->training_cnt++;
return 0;
}
static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr)
{
struct amdgpu_device *adev = psp->adev;
@ -567,6 +725,7 @@ static const struct psp_funcs psp_v13_0_funcs = {
.ring_destroy = psp_v13_0_ring_destroy,
.ring_get_wptr = psp_v13_0_ring_get_wptr,
.ring_set_wptr = psp_v13_0_ring_set_wptr,
.mem_training = psp_v13_0_memory_training,
.load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw,
.read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw,
.update_spirom = psp_v13_0_update_spirom,

387
drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c Normal file
View File

@ -0,0 +1,387 @@
/*
* Copyright 2020 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "amdgpu.h"
#include "amdgpu_psp.h"
#include "amdgpu_ucode.h"
#include "soc15_common.h"
#include "psp_v13_0_4.h"
#include "mp/mp_13_0_4_offset.h"
#include "mp/mp_13_0_4_sh_mask.h"
MODULE_FIRMWARE("amdgpu/psp_13_0_4_toc.bin");
MODULE_FIRMWARE("amdgpu/psp_13_0_4_ta.bin");
static int psp_v13_0_4_init_microcode(struct psp_context *psp)
{
struct amdgpu_device *adev = psp->adev;
const char *chip_name;
char ucode_prefix[30];
int err = 0;
switch (adev->ip_versions[MP0_HWIP][0]) {
case IP_VERSION(13, 0, 4):
amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
chip_name = ucode_prefix;
break;
default:
BUG();
}
switch (adev->ip_versions[MP0_HWIP][0]) {
case IP_VERSION(13, 0, 4):
err = psp_init_toc_microcode(psp, chip_name);
if (err)
return err;
err = psp_init_ta_microcode(psp, chip_name);
if (err)
return err;
break;
default:
BUG();
}
return 0;
}
static bool psp_v13_0_4_is_sos_alive(struct psp_context *psp)
{
struct amdgpu_device *adev = psp->adev;
uint32_t sol_reg;
sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
return sol_reg != 0x0;
}
static int psp_v13_0_4_wait_for_bootloader(struct psp_context *psp)
{
struct amdgpu_device *adev = psp->adev;
int ret;
int retry_loop;
for (retry_loop = 0; retry_loop < 10; retry_loop++) {
/* Wait for bootloader to signify that is
ready having bit 31 of C2PMSG_35 set to 1 */
ret = psp_wait_for(psp,
SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
0x80000000,
0x80000000,
false);
if (ret == 0)
return 0;
}
return ret;
}
static int psp_v13_0_4_bootloader_load_component(struct psp_context *psp,
struct psp_bin_desc *bin_desc,
enum psp_bootloader_cmd bl_cmd)
{
int ret;
uint32_t psp_gfxdrv_command_reg = 0;
struct amdgpu_device *adev = psp->adev;
/* Check tOS sign of life register to confirm sys driver and sOS
* are already been loaded.
*/
if (psp_v13_0_4_is_sos_alive(psp))
return 0;
ret = psp_v13_0_4_wait_for_bootloader(psp);
if (ret)
return ret;
memset(psp->fw_pri_buf, 0, PSP_1_MEG);
/* Copy PSP KDB binary to memory */
memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes);
/* Provide the PSP KDB to bootloader */
WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
(uint32_t)(psp->fw_pri_mc_addr >> 20));
psp_gfxdrv_command_reg = bl_cmd;
WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
psp_gfxdrv_command_reg);
ret = psp_v13_0_4_wait_for_bootloader(psp);
return ret;
}
static int psp_v13_0_4_bootloader_load_kdb(struct psp_context *psp)
{
return psp_v13_0_4_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
}
static int psp_v13_0_4_bootloader_load_spl(struct psp_context *psp)
{
return psp_v13_0_4_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE);
}
static int psp_v13_0_4_bootloader_load_sysdrv(struct psp_context *psp)
{
return psp_v13_0_4_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
}
static int psp_v13_0_4_bootloader_load_soc_drv(struct psp_context *psp)
{
return psp_v13_0_4_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV);
}
static int psp_v13_0_4_bootloader_load_intf_drv(struct psp_context *psp)
{
return psp_v13_0_4_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV);
}
static int psp_v13_0_4_bootloader_load_dbg_drv(struct psp_context *psp)
{
return psp_v13_0_4_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV);
}
static int psp_v13_0_4_bootloader_load_sos(struct psp_context *psp)
{
int ret;
unsigned int psp_gfxdrv_command_reg = 0;
struct amdgpu_device *adev = psp->adev;
/* Check sOS sign of life register to confirm sys driver and sOS
* are already been loaded.
*/
if (psp_v13_0_4_is_sos_alive(psp))
return 0;
ret = psp_v13_0_4_wait_for_bootloader(psp);
if (ret)
return ret;
memset(psp->fw_pri_buf, 0, PSP_1_MEG);
/* Copy Secure OS binary to PSP memory */
memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes);
/* Provide the PSP secure OS to bootloader */
WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
(uint32_t)(psp->fw_pri_mc_addr >> 20));
psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
psp_gfxdrv_command_reg);
/* there might be handshake issue with hardware which needs delay */
mdelay(20);
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81),
RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81),
0, true);
return ret;
}
static int psp_v13_0_4_ring_init(struct psp_context *psp,
enum psp_ring_type ring_type)
{
int ret = 0;
struct psp_ring *ring;
struct amdgpu_device *adev = psp->adev;
ring = &psp->km_ring;
ring->ring_type = ring_type;
/* allocate 4k Page of Local Frame Buffer memory for ring */
ring->ring_size = 0x1000;
ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM,
&adev->firmware.rbuf,
&ring->ring_mem_mc_addr,
(void **)&ring->ring_mem);
if (ret) {
ring->ring_size = 0;
return ret;
}
return 0;
}
static int psp_v13_0_4_ring_stop(struct psp_context *psp,
enum psp_ring_type ring_type)
{
int ret = 0;
struct amdgpu_device *adev = psp->adev;
if (amdgpu_sriov_vf(adev)) {
/* Write the ring destroy command*/
WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
/* there might be handshake issue with hardware which needs delay */
mdelay(20);
/* Wait for response flag (bit 31) */
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
0x80000000, 0x80000000, false);
} else {
/* Write the ring destroy command*/
WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,
GFX_CTRL_CMD_ID_DESTROY_RINGS);
/* there might be handshake issue with hardware which needs delay */
mdelay(20);
/* Wait for response flag (bit 31) */
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
0x80000000, 0x80000000, false);
}
return ret;
}
static int psp_v13_0_4_ring_create(struct psp_context *psp,
enum psp_ring_type ring_type)
{
int ret = 0;
unsigned int psp_ring_reg = 0;
struct psp_ring *ring = &psp->km_ring;
struct amdgpu_device *adev = psp->adev;
if (amdgpu_sriov_vf(adev)) {
ret = psp_v13_0_4_ring_stop(psp, ring_type);
if (ret) {
DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n");
return ret;
}
/* Write low address of the ring to C2PMSG_102 */
psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg);
/* Write high address of the ring to C2PMSG_103 */
psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg);
/* Write the ring initialization command to C2PMSG_101 */
WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
/* there might be handshake issue with hardware which needs delay */
mdelay(20);
/* Wait for response flag (bit 31) in C2PMSG_101 */
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
0x80000000, 0x8000FFFF, false);
} else {
/* Wait for sOS ready for ring creation */
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
0x80000000, 0x80000000, false);
if (ret) {
DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
return ret;
}
/* Write low address of the ring to C2PMSG_69 */
psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg);
/* Write high address of the ring to C2PMSG_70 */
psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg);
/* Write size of ring to C2PMSG_71 */
psp_ring_reg = ring->ring_size;
WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg);
/* Write the ring initialization command to C2PMSG_64 */
psp_ring_reg = ring_type;
psp_ring_reg = psp_ring_reg << 16;
WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg);
/* there might be handshake issue with hardware which needs delay */
mdelay(20);
/* Wait for response flag (bit 31) in C2PMSG_64 */
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
0x80000000, 0x8000FFFF, false);
}
return ret;
}
static int psp_v13_0_4_ring_destroy(struct psp_context *psp,
enum psp_ring_type ring_type)
{
int ret = 0;
struct psp_ring *ring = &psp->km_ring;
struct amdgpu_device *adev = psp->adev;
ret = psp_v13_0_4_ring_stop(psp, ring_type);
if (ret)
DRM_ERROR("Fail to stop psp ring\n");
amdgpu_bo_free_kernel(&adev->firmware.rbuf,
&ring->ring_mem_mc_addr,
(void **)&ring->ring_mem);
return ret;
}
static uint32_t psp_v13_0_4_ring_get_wptr(struct psp_context *psp)
{
uint32_t data;
struct amdgpu_device *adev = psp->adev;
if (amdgpu_sriov_vf(adev))
data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102);
else
data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
return data;
}
static void psp_v13_0_4_ring_set_wptr(struct psp_context *psp, uint32_t value)
{
struct amdgpu_device *adev = psp->adev;
if (amdgpu_sriov_vf(adev)) {
WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value);
WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
GFX_CTRL_CMD_ID_CONSUME_CMD);
} else
WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value);
}
static const struct psp_funcs psp_v13_0_4_funcs = {
.init_microcode = psp_v13_0_4_init_microcode,
.bootloader_load_kdb = psp_v13_0_4_bootloader_load_kdb,
.bootloader_load_spl = psp_v13_0_4_bootloader_load_spl,
.bootloader_load_sysdrv = psp_v13_0_4_bootloader_load_sysdrv,
.bootloader_load_soc_drv = psp_v13_0_4_bootloader_load_soc_drv,
.bootloader_load_intf_drv = psp_v13_0_4_bootloader_load_intf_drv,
.bootloader_load_dbg_drv = psp_v13_0_4_bootloader_load_dbg_drv,
.bootloader_load_sos = psp_v13_0_4_bootloader_load_sos,
.ring_init = psp_v13_0_4_ring_init,
.ring_create = psp_v13_0_4_ring_create,
.ring_stop = psp_v13_0_4_ring_stop,
.ring_destroy = psp_v13_0_4_ring_destroy,
.ring_get_wptr = psp_v13_0_4_ring_get_wptr,
.ring_set_wptr = psp_v13_0_4_ring_set_wptr,
};
void psp_v13_0_4_set_psp_funcs(struct psp_context *psp)
{
psp->funcs = &psp_v13_0_4_funcs;
}

30
drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.h Normal file
View File

@ -0,0 +1,30 @@
/*
* Copyright 2020 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __PSP_V13_0_4_H__
#define __PSP_V13_0_4_H__
#include "amdgpu_psp.h"
void psp_v13_0_4_set_psp_funcs(struct psp_context *psp);
#endif

8
drivers/gpu/drm/amd/amdgpu/soc21.c
View File

@ -80,6 +80,7 @@ static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode,
switch (adev->ip_versions[UVD_HWIP][0]) {
case IP_VERSION(4, 0, 0):
case IP_VERSION(4, 0, 2):
if (encode)
*codecs = &vcn_4_0_0_video_codecs_encode;
else
@ -584,8 +585,11 @@ static int soc21_common_early_init(void *handle)
adev->external_rev_id = adev->rev_id + 0x10;
break;
case IP_VERSION(11, 0, 1):
adev->cg_flags = 0;
adev->pg_flags = 0;
adev->cg_flags =
AMD_CG_SUPPORT_VCN_MGCG |
AMD_CG_SUPPORT_JPEG_MGCG;
adev->pg_flags =
AMD_PG_SUPPORT_JPEG;
adev->external_rev_id = adev->rev_id + 0x1;
break;
default:

3
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
View File

@ -154,7 +154,7 @@ static int vcn_v4_0_sw_fini(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int i, r, idx;
if (drm_dev_enter(&adev->ddev, &idx)) {
if (drm_dev_enter(adev_to_drm(adev), &idx)) {
for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
volatile struct amdgpu_vcn4_fw_shared *fw_shared;
@ -1041,6 +1041,7 @@ static int vcn_v4_0_start(struct amdgpu_device *adev)
}
if (amdgpu_emu_mode==1) {
r = -1;
if (status & 2) {
r = 0;
break;

2
drivers/gpu/drm/amd/amdkfd/kfd_debugfs.c
View File

@ -101,6 +101,8 @@ void kfd_debugfs_init(void)
kfd_debugfs_rls_by_device, &kfd_debugfs_fops);
debugfs_create_file("hang_hws", S_IFREG | 0200, debugfs_root,
kfd_debugfs_hang_hws_read, &kfd_debugfs_hang_hws_fops);
debugfs_create_file("mem_limit", S_IFREG | 0200, debugfs_root,
kfd_debugfs_kfd_mem_limits, &kfd_debugfs_fops);
}
void kfd_debugfs_fini(void)

4
drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c
View File

@ -146,7 +146,7 @@ static void interrupt_wq(struct work_struct *work)
struct kfd_dev *dev = container_of(work, struct kfd_dev,
interrupt_work);
uint32_t ih_ring_entry[KFD_MAX_RING_ENTRY_SIZE];
long start_jiffies = jiffies;
unsigned long start_jiffies = jiffies;
if (dev->device_info.ih_ring_entry_size > sizeof(ih_ring_entry)) {
dev_err_once(dev->adev->dev, "Ring entry too small\n");
@ -156,7 +156,7 @@ static void interrupt_wq(struct work_struct *work)
while (dequeue_ih_ring_entry(dev, ih_ring_entry)) {
dev->device_info.event_interrupt_class->interrupt_wq(dev,
ih_ring_entry);
if (jiffies - start_jiffies > HZ) {
if (time_is_before_jiffies(start_jiffies + HZ)) {
/* If we spent more than a second processing signals,
* reschedule the worker to avoid soft-lockup warnings
*/

2
drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
View File

@ -1019,6 +1019,8 @@ int svm_migrate_init(struct amdgpu_device *adev)
amdgpu_amdkfd_reserve_system_mem(SVM_HMM_PAGE_STRUCT_SIZE(size));
svm_range_set_max_pages(adev);
pr_info("HMM registered %ldMB device memory\n", size >> 20);
return 0;

122
drivers/gpu/drm/amd/amdkfd/kfd_svm.c
View File

@ -46,6 +46,12 @@
*/
#define AMDGPU_SVM_RANGE_RETRY_FAULT_PENDING (2UL * NSEC_PER_MSEC)
/* Giant svm range split into smaller ranges based on this, it is decided using
* minimum of all dGPU/APU 1/32 VRAM size, between 2MB to 1GB and alignment to
* power of 2MB.
*/
static uint64_t max_svm_range_pages;
struct criu_svm_metadata {
struct list_head list;
struct kfd_criu_svm_range_priv_data data;
@ -260,13 +266,22 @@ void svm_range_free_dma_mappings(struct svm_range *prange)
}
}
static void svm_range_free(struct svm_range *prange)
static void svm_range_free(struct svm_range *prange, bool update_mem_usage)
{
uint64_t size = (prange->last - prange->start + 1) << PAGE_SHIFT;
struct kfd_process *p = container_of(prange->svms, struct kfd_process, svms);
pr_debug("svms 0x%p prange 0x%p [0x%lx 0x%lx]\n", prange->svms, prange,
prange->start, prange->last);
svm_range_vram_node_free(prange);
svm_range_free_dma_mappings(prange);
if (update_mem_usage && !p->xnack_enabled) {
pr_debug("unreserve mem limit: %lld\n", size);
amdgpu_amdkfd_unreserve_mem_limit(NULL, size,
KFD_IOC_ALLOC_MEM_FLAGS_USERPTR);
}
mutex_destroy(&prange->lock);
mutex_destroy(&prange->migrate_mutex);
kfree(prange);
@ -285,7 +300,7 @@ svm_range_set_default_attributes(int32_t *location, int32_t *prefetch_loc,
static struct
svm_range *svm_range_new(struct svm_range_list *svms, uint64_t start,
uint64_t last)
uint64_t last, bool update_mem_usage)
{
uint64_t size = last - start + 1;
struct svm_range *prange;
@ -294,6 +309,15 @@ svm_range *svm_range_new(struct svm_range_list *svms, uint64_t start,
prange = kzalloc(sizeof(*prange), GFP_KERNEL);
if (!prange)
return NULL;
p = container_of(svms, struct kfd_process, svms);
if (!p->xnack_enabled && update_mem_usage &&
amdgpu_amdkfd_reserve_mem_limit(NULL, size << PAGE_SHIFT,
KFD_IOC_ALLOC_MEM_FLAGS_USERPTR)) {
pr_info("SVM mapping failed, exceeds resident system memory limit\n");
kfree(prange);
return NULL;
}
prange->npages = size;
prange->svms = svms;
prange->start = start;
@ -308,7 +332,6 @@ svm_range *svm_range_new(struct svm_range_list *svms, uint64_t start,
mutex_init(&prange->migrate_mutex);
mutex_init(&prange->lock);
p = container_of(svms, struct kfd_process, svms);
if (p->xnack_enabled)
bitmap_copy(prange->bitmap_access, svms->bitmap_supported,
MAX_GPU_INSTANCE);
@ -1001,9 +1024,9 @@ svm_range_split(struct svm_range *prange, uint64_t start, uint64_t last,
svms = prange->svms;
if (old_start == start)
*new = svm_range_new(svms, last + 1, old_last);
*new = svm_range_new(svms, last + 1, old_last, false);
else
*new = svm_range_new(svms, old_start, start - 1);
*new = svm_range_new(svms, old_start, start - 1, false);
if (!*new)
return -ENOMEM;
@ -1011,7 +1034,7 @@ svm_range_split(struct svm_range *prange, uint64_t start, uint64_t last,
if (r) {
pr_debug("failed %d split [0x%llx 0x%llx] to [0x%llx 0x%llx]\n",
r, old_start, old_last, start, last);
svm_range_free(*new);
svm_range_free(*new, false);
*new = NULL;
}
@ -1846,7 +1869,7 @@ static struct svm_range *svm_range_clone(struct svm_range *old)
{
struct svm_range *new;
new = svm_range_new(old->svms, old->start, old->last);
new = svm_range_new(old->svms, old->start, old->last, false);
if (!new)
return NULL;
@ -1870,6 +1893,46 @@ static struct svm_range *svm_range_clone(struct svm_range *old)
return new;
}
void svm_range_set_max_pages(struct amdgpu_device *adev)
{
uint64_t max_pages;
uint64_t pages, _pages;
/* 1/32 VRAM size in pages */
pages = adev->gmc.real_vram_size >> 17;
pages = clamp(pages, 1ULL << 9, 1ULL << 18);
pages = rounddown_pow_of_two(pages);
do {
max_pages = READ_ONCE(max_svm_range_pages);
_pages = min_not_zero(max_pages, pages);
} while (cmpxchg(&max_svm_range_pages, max_pages, _pages) != max_pages);
}
static int
svm_range_split_new(struct svm_range_list *svms, uint64_t start, uint64_t last,
uint64_t max_pages, struct list_head *insert_list,
struct list_head *update_list)
{
struct svm_range *prange;
uint64_t l;
pr_debug("max_svm_range_pages 0x%llx adding [0x%llx 0x%llx]\n",
max_pages, start, last);
while (last >= start) {
l = min(last, ALIGN_DOWN(start + max_pages, max_pages) - 1);
prange = svm_range_new(svms, start, l, true);
if (!prange)
return -ENOMEM;
list_add(&prange->list, insert_list);
list_add(&prange->update_list, update_list);
start = l + 1;
}
return 0;
}
/**
* svm_range_add - add svm range and handle overlap
* @p: the range add to this process svms
@ -1910,6 +1973,7 @@ svm_range_add(struct kfd_process *p, uint64_t start, uint64_t size,
struct interval_tree_node *node;
struct svm_range *prange;
struct svm_range *tmp;
struct list_head new_list;
int r = 0;
pr_debug("svms 0x%p [0x%llx 0x%lx]\n", &p->svms, start, last);
@ -1917,6 +1981,7 @@ svm_range_add(struct kfd_process *p, uint64_t start, uint64_t size,
INIT_LIST_HEAD(update_list);
INIT_LIST_HEAD(insert_list);
INIT_LIST_HEAD(remove_list);
INIT_LIST_HEAD(&new_list);
node = interval_tree_iter_first(&svms->objects, start, last);
while (node) {
@ -1972,14 +2037,11 @@ svm_range_add(struct kfd_process *p, uint64_t start, uint64_t size,
/* insert a new node if needed */
if (node->start > start) {
prange = svm_range_new(svms, start, node->start - 1);
if (!prange) {
r = -ENOMEM;
r = svm_range_split_new(svms, start, node->start - 1,
READ_ONCE(max_svm_range_pages),
&new_list, update_list);
if (r)
goto out;
}
list_add(&prange->list, insert_list);
list_add(&prange->update_list, update_list);
}
node = next;
@ -1987,20 +2049,20 @@ svm_range_add(struct kfd_process *p, uint64_t start, uint64_t size,
}
/* add a final range at the end if needed */
if (start <= last) {
prange = svm_range_new(svms, start, last);
if (!prange) {
r = -ENOMEM;
goto out;
}
list_add(&prange->list, insert_list);
list_add(&prange->update_list, update_list);
}
if (start <= last)
r = svm_range_split_new(svms, start, last,
READ_ONCE(max_svm_range_pages),
&new_list, update_list);
out:
if (r)
if (r) {
list_for_each_entry_safe(prange, tmp, insert_list, list)
svm_range_free(prange);
svm_range_free(prange, false);
list_for_each_entry_safe(prange, tmp, &new_list, list)
svm_range_free(prange, true);
} else {
list_splice(&new_list, insert_list);
}
return r;
}
@ -2047,7 +2109,7 @@ svm_range_handle_list_op(struct svm_range_list *svms, struct svm_range *prange,
svms, prange, prange->start, prange->last);
svm_range_unlink(prange);
svm_range_remove_notifier(prange);
svm_range_free(prange);
svm_range_free(prange, true);
break;
case SVM_OP_UPDATE_RANGE_NOTIFIER:
pr_debug("update notifier 0x%p prange 0x%p [0x%lx 0x%lx]\n",
@ -2610,14 +2672,14 @@ svm_range *svm_range_create_unregistered_range(struct amdgpu_device *adev,
last = addr;
}
prange = svm_range_new(&p->svms, start, last);
prange = svm_range_new(&p->svms, start, last, true);
if (!prange) {
pr_debug("Failed to create prange in address [0x%llx]\n", addr);
return NULL;
}
if (kfd_process_gpuid_from_adev(p, adev, &gpuid, &gpuidx)) {
pr_debug("failed to get gpuid from kgd\n");
svm_range_free(prange);
svm_range_free(prange, true);
return NULL;
}
@ -2917,7 +2979,7 @@ void svm_range_list_fini(struct kfd_process *p)
list_for_each_entry_safe(prange, next, &p->svms.list, list) {
svm_range_unlink(prange);
svm_range_remove_notifier(prange);
svm_range_free(prange);
svm_range_free(prange, true);
}
mutex_destroy(&p->svms.lock);
@ -3333,7 +3395,7 @@ svm_range_set_attr(struct kfd_process *p, struct mm_struct *mm,
prange->last);
svm_range_unlink(prange);
svm_range_remove_notifier(prange);
svm_range_free(prange);
svm_range_free(prange, false);
}
mmap_write_downgrade(mm);

3
drivers/gpu/drm/amd/amdkfd/kfd_svm.h
View File

@ -204,6 +204,9 @@ void svm_range_list_lock_and_flush_work(struct svm_range_list *svms, struct mm_s
#define KFD_IS_SVM_API_SUPPORTED(dev) ((dev)->pgmap.type != 0)
void svm_range_bo_unref_async(struct svm_range_bo *svm_bo);
void svm_range_set_max_pages(struct amdgpu_device *adev);
#else
struct kfd_process;

72
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
View File

@ -1369,9 +1369,9 @@ static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf,
for (i = 0; i < MAX_PIPES; i++) {
pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
if (pipe_ctx && pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link)
break;
if (pipe_ctx && pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link)
break;
}
if (!pipe_ctx) {
@ -1475,9 +1475,9 @@ static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf,
for (i = 0; i < MAX_PIPES; i++) {
pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
if (pipe_ctx && pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link)
break;
if (pipe_ctx && pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link)
break;
}
if (!pipe_ctx || !pipe_ctx->stream)
@ -1560,9 +1560,9 @@ static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf,
for (i = 0; i < MAX_PIPES; i++) {
pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
if (pipe_ctx && pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link)
break;
if (pipe_ctx && pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link)
break;
}
if (!pipe_ctx) {
@ -1664,9 +1664,9 @@ static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf,
for (i = 0; i < MAX_PIPES; i++) {
pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
if (pipe_ctx && pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link)
break;
if (pipe_ctx && pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link)
break;
}
if (!pipe_ctx || !pipe_ctx->stream)
@ -1749,9 +1749,9 @@ static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf,
for (i = 0; i < MAX_PIPES; i++) {
pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
if (pipe_ctx && pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link)
break;
if (pipe_ctx && pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link)
break;
}
if (!pipe_ctx) {
@ -1853,9 +1853,9 @@ static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf,
for (i = 0; i < MAX_PIPES; i++) {
pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
if (pipe_ctx && pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link)
break;
if (pipe_ctx && pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link)
break;
}
if (!pipe_ctx || !pipe_ctx->stream)
@ -1934,9 +1934,9 @@ static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf,
for (i = 0; i < MAX_PIPES; i++) {
pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
if (pipe_ctx && pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link)
break;
if (pipe_ctx && pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link)
break;
}
if (!pipe_ctx) {
@ -2035,9 +2035,9 @@ static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *bu
for (i = 0; i < MAX_PIPES; i++) {
pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
if (pipe_ctx && pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link)
break;
if (pipe_ctx && pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link)
break;
}
if (!pipe_ctx || !pipe_ctx->stream)
@ -2114,9 +2114,9 @@ static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf,
for (i = 0; i < MAX_PIPES; i++) {
pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
if (pipe_ctx && pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link)
break;
if (pipe_ctx && pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link)
break;
}
if (!pipe_ctx) {
@ -2175,9 +2175,9 @@ static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf,
for (i = 0; i < MAX_PIPES; i++) {
pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
if (pipe_ctx && pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link)
break;
if (pipe_ctx && pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link)
break;
}
if (!pipe_ctx) {
@ -2251,9 +2251,9 @@ static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf,
for (i = 0; i < MAX_PIPES; i++) {
pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
if (pipe_ctx && pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link)
break;
if (pipe_ctx && pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link)
break;
}
if (!pipe_ctx) {
@ -2327,9 +2327,9 @@ static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf,
for (i = 0; i < MAX_PIPES; i++) {
pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
if (pipe_ctx && pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link)
break;
if (pipe_ctx && pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link)
break;
}
if (!pipe_ctx) {

2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
View File

@ -569,7 +569,7 @@ static bool execute_synaptics_rc_command(struct drm_dp_aux *aux,
unsigned char rc_cmd = 0;
unsigned char rc_result = 0xFF;
unsigned char i = 0;
uint8_t ret = 0;
int ret;
if (is_write_cmd) {
// write rc data

4
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c
View File

@ -101,8 +101,8 @@ static void dcn201_update_clocks(struct clk_mgr *clk_mgr_base,
return;
if (clk_mgr_base->clks.dispclk_khz == 0 ||
dc->debug.force_clock_mode & 0x1) {
force_reset = true;
dc->debug.force_clock_mode & 0x1) {
force_reset = true;
dcn2_read_clocks_from_hw_dentist(clk_mgr_base);
}

3
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
View File

@ -723,7 +723,8 @@ void dcn31_clk_mgr_construct(
dcn31_bw_params.wm_table = ddr5_wm_table;
}
/* Saved clocks configured at boot for debug purposes */
dcn31_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info);
dcn31_dump_clk_registers(&clk_mgr->base.base.boot_snapshot,
&clk_mgr->base.base, &log_info);
}

3
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
View File

@ -713,7 +713,8 @@ void dcn314_clk_mgr_construct(
dcn314_bw_params.wm_table = ddr5_wm_table;
/* Saved clocks configured at boot for debug purposes */
dcn314_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info);
dcn314_dump_clk_registers(&clk_mgr->base.base.boot_snapshot,
&clk_mgr->base.base, &log_info);
}

3
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
View File

@ -652,7 +652,8 @@ void dcn315_clk_mgr_construct(
dcn315_bw_params.wm_table = ddr5_wm_table;
}
/* Saved clocks configured at boot for debug purposes */
dcn315_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info);
dcn315_dump_clk_registers(&clk_mgr->base.base.boot_snapshot,
&clk_mgr->base.base, &log_info);
}

3
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
View File

@ -680,7 +680,8 @@ void dcn316_clk_mgr_construct(
dcn316_bw_params.wm_table = ddr4_wm_table;
}
/* Saved clocks configured at boot for debug purposes */
dcn316_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info);
dcn316_dump_clk_registers(&clk_mgr->base.base.boot_snapshot,
&clk_mgr->base.base, &log_info);
}

8
drivers/gpu/drm/amd/display/dc/dc_stream.h
View File

@ -48,11 +48,6 @@ struct dc_stream_status {
bool is_abm_supported;
};
// TODO: References to this needs to be removed..
struct freesync_context {
bool dummy;
};
enum hubp_dmdata_mode {
DMDATA_SW_MODE,
DMDATA_HW_MODE
@ -184,9 +179,6 @@ struct dc_stream_state {
struct rect src; /* composition area */
struct rect dst; /* stream addressable area */
// TODO: References to this needs to be removed..
struct freesync_context freesync_ctx;
struct audio_info audio_info;
struct dc_info_packet hdr_static_metadata;

2
drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
View File

@ -320,7 +320,7 @@ static void set_video_latency(
value);
}
/* set audio latency in in ms/2+1 */
/* set audio latency in ms/2+1 */
static void set_audio_latency(
struct audio *audio,
int latency_in_ms)

68
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c
View File

@ -444,24 +444,24 @@ static enum dc_lut_mode dpp20_get_blndgam_current(struct dpp *dpp_base)
uint32_t state_mode;
struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
REG_GET(CM_BLNDGAM_LUT_WRITE_EN_MASK,
CM_BLNDGAM_CONFIG_STATUS, &state_mode);
REG_GET(CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_CONFIG_STATUS, &state_mode);
switch (state_mode) {
case 0:
mode = LUT_BYPASS;
break;
case 1:
mode = LUT_RAM_A;
break;
case 2:
mode = LUT_RAM_B;
break;
default:
mode = LUT_BYPASS;
break;
}
return mode;
switch (state_mode) {
case 0:
mode = LUT_BYPASS;
break;
case 1:
mode = LUT_RAM_A;
break;
case 2:
mode = LUT_RAM_B;
break;
default:
mode = LUT_BYPASS;
break;
}
return mode;
}
bool dpp20_program_blnd_lut(
@ -537,24 +537,24 @@ static enum dc_lut_mode dpp20_get_shaper_current(struct dpp *dpp_base)
uint32_t state_mode;
struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
REG_GET(CM_SHAPER_LUT_WRITE_EN_MASK,
CM_SHAPER_CONFIG_STATUS, &state_mode);
REG_GET(CM_SHAPER_LUT_WRITE_EN_MASK, CM_SHAPER_CONFIG_STATUS, &state_mode);
switch (state_mode) {
case 0:
mode = LUT_BYPASS;
break;
case 1:
mode = LUT_RAM_A;
break;
case 2:
mode = LUT_RAM_B;
break;
default:
mode = LUT_BYPASS;
break;
}
return mode;
switch (state_mode) {
case 0:
mode = LUT_BYPASS;
break;
case 1:
mode = LUT_RAM_A;
break;
case 2:
mode = LUT_RAM_B;
break;
default:
mode = LUT_BYPASS;
break;
}
return mode;
}
static void dpp20_configure_shaper_lut(

4
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c
View File

@ -101,8 +101,8 @@ static bool dwb2_enable(struct dwbc *dwbc, struct dc_dwb_params *params)
struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
/* Only chroma scaling (sub-sampling) is supported in DCN2 */
if ((params->cnv_params.src_width != params->dest_width) ||
(params->cnv_params.src_height != params->dest_height)) {
if ((params->cnv_params.src_width != params->dest_width) ||
(params->cnv_params.src_height != params->dest_height)) {
DC_LOG_DWB("%s inst = %d, FAILED!LUMA SCALING NOT SUPPORTED", __func__, dwbc20->base.inst);
return false;

14
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
View File

@ -1716,15 +1716,13 @@ void dcn20_program_front_end_for_ctx(
DC_LOGGER_INIT(dc->ctx->logger);
/* Carry over GSL groups in case the context is changing. */
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
struct pipe_ctx *old_pipe_ctx =
&dc->current_state->res_ctx.pipe_ctx[i];
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
if (pipe_ctx->stream == old_pipe_ctx->stream)
pipe_ctx->stream_res.gsl_group =
old_pipe_ctx->stream_res.gsl_group;
}
if (pipe_ctx->stream == old_pipe_ctx->stream)
pipe_ctx->stream_res.gsl_group = old_pipe_ctx->stream_res.gsl_group;
}
if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
for (i = 0; i < dc->res_pool->pipe_count; i++) {

34
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
View File

@ -299,24 +299,24 @@ static enum dc_lut_mode mpc20_get_ogam_current(struct mpc *mpc, int mpcc_id)
uint32_t state_mode;
struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
REG_GET(MPCC_OGAM_LUT_RAM_CONTROL[mpcc_id],
MPCC_OGAM_CONFIG_STATUS, &state_mode);
REG_GET(MPCC_OGAM_LUT_RAM_CONTROL[mpcc_id], MPCC_OGAM_CONFIG_STATUS, &state_mode);
switch (state_mode) {
case 0:
mode = LUT_BYPASS;
break;
case 1:
mode = LUT_RAM_A;
break;
case 2:
mode = LUT_RAM_B;
break;
default:
mode = LUT_BYPASS;
break;
}
return mode;
switch (state_mode) {
case 0:
mode = LUT_BYPASS;
break;
case 1:
mode = LUT_RAM_A;
break;
case 2:
mode = LUT_RAM_B;
break;
default:
mode = LUT_BYPASS;
break;
}
return mode;
}
static void mpc2_program_lutb(struct mpc *mpc, int mpcc_id,

73
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
View File

@ -716,28 +716,27 @@ static enum dc_lut_mode dpp3_get_blndgam_current(struct dpp *dpp_base)
struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
REG_GET(CM_BLNDGAM_CONTROL,
CM_BLNDGAM_MODE_CURRENT, &mode_current);
REG_GET(CM_BLNDGAM_CONTROL,
CM_BLNDGAM_SELECT_CURRENT, &in_use);
REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_MODE_CURRENT, &mode_current);
REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_SELECT_CURRENT, &in_use);
switch (mode_current) {
case 0:
case 1:
mode = LUT_BYPASS;
break;
switch (mode_current) {
case 0:
case 1:
mode = LUT_BYPASS;
break;
case 2:
if (in_use == 0)
mode = LUT_RAM_A;
else
mode = LUT_RAM_B;
break;
default:
mode = LUT_BYPASS;
break;
}
return mode;
case 2:
if (in_use == 0)
mode = LUT_RAM_A;
else
mode = LUT_RAM_B;
break;
default:
mode = LUT_BYPASS;
break;
}
return mode;
}
static bool dpp3_program_blnd_lut(struct dpp *dpp_base,
@ -817,24 +816,24 @@ static enum dc_lut_mode dpp3_get_shaper_current(struct dpp *dpp_base)
uint32_t state_mode;
struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
REG_GET(CM_SHAPER_CONTROL,
CM_SHAPER_MODE_CURRENT, &state_mode);
REG_GET(CM_SHAPER_CONTROL, CM_SHAPER_MODE_CURRENT, &state_mode);
switch (state_mode) {
case 0:
mode = LUT_BYPASS;
break;
case 1:
mode = LUT_RAM_A;
break;
case 2:
mode = LUT_RAM_B;
break;
default:
mode = LUT_BYPASS;
break;
}
return mode;
switch (state_mode) {
case 0:
mode = LUT_BYPASS;
break;
case 1:
mode = LUT_RAM_A;
break;
case 2:
mode = LUT_RAM_B;
break;
default:
mode = LUT_BYPASS;
break;
}
return mode;
}
static void dpp3_configure_shaper_lut(

25
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp_cm.c
View File

@ -61,23 +61,20 @@ static enum dc_lut_mode dpp30_get_gamcor_current(struct dpp *dpp_base)
uint32_t lut_mode;
struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
REG_GET(CM_GAMCOR_CONTROL,
CM_GAMCOR_MODE_CURRENT, &state_mode);
REG_GET(CM_GAMCOR_CONTROL, CM_GAMCOR_MODE_CURRENT, &state_mode);
if (state_mode == 0)
mode = LUT_BYPASS;
if (state_mode == 0)
mode = LUT_BYPASS;
if (state_mode == 2) {//Programmable RAM LUT
REG_GET(CM_GAMCOR_CONTROL,
CM_GAMCOR_SELECT_CURRENT, &lut_mode);
if (state_mode == 2) {//Programmable RAM LUT
REG_GET(CM_GAMCOR_CONTROL, CM_GAMCOR_SELECT_CURRENT, &lut_mode);
if (lut_mode == 0)
mode = LUT_RAM_A;
else
mode = LUT_RAM_B;
}
if (lut_mode == 0)
mode = LUT_RAM_A;
else
mode = LUT_RAM_B;
}
return mode;
return mode;
}
static void dpp3_program_gammcor_lut(

70
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
View File

@ -109,32 +109,32 @@ enum dc_lut_mode mpc3_get_ogam_current(struct mpc *mpc, int mpcc_id)
uint32_t state_ram_lut_in_use;
struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
REG_GET_2(MPCC_OGAM_CONTROL[mpcc_id],
MPCC_OGAM_MODE_CURRENT, &state_mode,
MPCC_OGAM_SELECT_CURRENT, &state_ram_lut_in_use);
REG_GET_2(MPCC_OGAM_CONTROL[mpcc_id], MPCC_OGAM_MODE_CURRENT, &state_mode,
MPCC_OGAM_SELECT_CURRENT, &state_ram_lut_in_use);
switch (state_mode) {
switch (state_mode) {
case 0:
mode = LUT_BYPASS;
break;
case 2:
switch (state_ram_lut_in_use) {
case 0:
mode = LUT_BYPASS;
mode = LUT_RAM_A;
break;
case 2:
switch (state_ram_lut_in_use) {
case 0:
mode = LUT_RAM_A;
break;
case 1:
mode = LUT_RAM_B;
break;
default:
mode = LUT_BYPASS;
break;
}
case 1:
mode = LUT_RAM_B;
break;
default:
mode = LUT_BYPASS;
break;
}
return mode;
break;
default:
mode = LUT_BYPASS;
break;
}
return mode;
}
void mpc3_power_on_ogam_lut(
@ -439,24 +439,24 @@ static enum dc_lut_mode mpc3_get_shaper_current(struct mpc *mpc, uint32_t rmu_id
uint32_t state_mode;
struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
REG_GET(SHAPER_CONTROL[rmu_idx],
MPC_RMU_SHAPER_LUT_MODE_CURRENT, &state_mode);
REG_GET(SHAPER_CONTROL[rmu_idx], MPC_RMU_SHAPER_LUT_MODE_CURRENT, &state_mode);
switch (state_mode) {
case 0:
mode = LUT_BYPASS;
break;
case 1:
mode = LUT_RAM_A;
break;
case 2:
mode = LUT_RAM_B;
break;
default:
mode = LUT_BYPASS;
break;
}
return mode;
switch (state_mode) {
case 0:
mode = LUT_BYPASS;
break;
case 1:
mode = LUT_RAM_A;
break;
case 2:
mode = LUT_RAM_B;
break;
default:
mode = LUT_BYPASS;
break;
}
return mode;
}
static void mpc3_configure_shaper_lut(

15
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
View File

@ -180,19 +180,8 @@ void optc3_set_dsc_config(struct timing_generator *optc,
{
struct optc *optc1 = DCN10TG_FROM_TG(optc);
optc2_set_dsc_config(optc, dsc_mode, dsc_bytes_per_pixel,
dsc_slice_width);
REG_UPDATE(OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, 0);
}
void optc3_set_vrr_m_const(struct timing_generator *optc,
double vtotal_avg)
{
DC_FP_START();
optc3_fpu_set_vrr_m_const(optc, vtotal_avg);
DC_FP_END();
optc2_set_dsc_config(optc, dsc_mode, dsc_bytes_per_pixel, dsc_slice_width);
REG_UPDATE(OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, 0);
}
void optc3_set_odm_bypass(struct timing_generator *optc,

3
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h
View File

@ -329,9 +329,6 @@ void optc3_lock_doublebuffer_enable(struct timing_generator *optc);
void optc3_lock_doublebuffer_disable(struct timing_generator *optc);
void optc3_set_vrr_m_const(struct timing_generator *optc,
double vtotal_avg);
void optc3_set_drr_trigger_window(struct timing_generator *optc,
uint32_t window_start, uint32_t window_end);

8
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
View File

@ -909,10 +909,10 @@ void dcn32_init_hw(struct dc *dc)
dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
// Get DMCUB capabilities
if (dc->ctx->dmub_srv) {
dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv->dmub);
dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
}
if (dc->ctx->dmub_srv) {
dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv->dmub);
dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
}
}
static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream,

34
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c
View File

@ -300,24 +300,24 @@ static enum dc_lut_mode mpc32_get_shaper_current(struct mpc *mpc, uint32_t mpcc_
uint32_t state_mode;
struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
REG_GET(MPCC_MCM_SHAPER_CONTROL[mpcc_id],
MPCC_MCM_SHAPER_MODE_CURRENT, &state_mode);
REG_GET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], MPCC_MCM_SHAPER_MODE_CURRENT, &state_mode);
switch (state_mode) {
case 0:
mode = LUT_BYPASS;
break;
case 1:
mode = LUT_RAM_A;
break;
case 2:
mode = LUT_RAM_B;
break;
default:
mode = LUT_BYPASS;
break;
}
return mode;
switch (state_mode) {
case 0:
mode = LUT_BYPASS;
break;
case 1:
mode = LUT_RAM_A;
break;
case 2:
mode = LUT_RAM_B;
break;
default:
mode = LUT_BYPASS;
break;
}
return mode;
}

1
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
View File

@ -281,7 +281,6 @@ static struct timing_generator_funcs dcn32_tg_funcs = {
.lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
.lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
.enable_optc_clock = optc1_enable_optc_clock,
.set_vrr_m_const = optc3_set_vrr_m_const,
.set_drr = optc31_set_drr, // TODO: Update to optc32_set_drr once FW headers are promoted
.get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
.set_vtotal_min_max = optc3_set_vtotal_min_max,

2
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
View File

@ -2341,7 +2341,7 @@ void dcn201_populate_dml_writeback_from_context_fpu(struct dc *dc,
dout_wb.wb_dst_width = wb_info->dwb_params.dest_width;
dout_wb.wb_dst_height = wb_info->dwb_params.dest_height;
dout_wb.wb_htaps_luma = wb_info->dwb_params.scaler_taps.h_taps;
dout_wb.wb_vtaps_luma = wb_info->dwb_params.scaler_taps.v_taps;;
dout_wb.wb_vtaps_luma = wb_info->dwb_params.scaler_taps.v_taps;
dout_wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c;
dout_wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c;
dout_wb.wb_hratio = wb_info->dwb_params.cnv_params.crop_en ?

18
drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
View File

@ -181,7 +181,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_0_soc = {
void optc3_fpu_set_vrr_m_const(struct timing_generator *optc,
double vtotal_avg)
{
struct optc *optc1 = DCN10TG_FROM_TG(optc);
struct optc *optc1 = DCN10TG_FROM_TG(optc);
double vtotal_min, vtotal_max;
double ratio, modulo, phase;
uint32_t vblank_start;
@ -350,24 +350,24 @@ void dcn30_fpu_set_mcif_arb_params(struct mcif_arb_params *wb_arb_params,
int pipe_cnt,
int cur_pipe)
{
int i;
int i;
dc_assert_fp_enabled();
for (i = 0; i < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); i++) {
for (i = 0; i < ARRAY_SIZE(wb_arb_params->cli_watermark); i++) {
wb_arb_params->cli_watermark[i] = get_wm_writeback_urgent(dml, pipes, pipe_cnt) * 1000;
wb_arb_params->pstate_watermark[i] = get_wm_writeback_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
}
}
wb_arb_params->dram_speed_change_duration = dml->vba.WritebackAllowDRAMClockChangeEndPosition[cur_pipe] * pipes[0].clks_cfg.refclk_mhz; /* num_clock_cycles = us * MHz */
wb_arb_params->dram_speed_change_duration = dml->vba.WritebackAllowDRAMClockChangeEndPosition[cur_pipe] * pipes[0].clks_cfg.refclk_mhz; /* num_clock_cycles = us * MHz */
}
void dcn30_fpu_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
{
dc_assert_fp_enabled();
dc_assert_fp_enabled();
if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) {
if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) {
context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us;
context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us;
@ -380,12 +380,12 @@ void dcn30_fpu_calculate_wm_and_dlg(
int pipe_cnt,
int vlevel)
{
int maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;
int maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;
int i, pipe_idx;
double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][maxMpcComb];
bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] != dm_dram_clock_change_unsupported;
dc_assert_fp_enabled();
dc_assert_fp_enabled();
if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk)
dcfclk = context->bw_ctx.dml.soc.min_dcfclk;

15
drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c
View File

@ -202,7 +202,7 @@ void dcn303_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_p
unsigned int num_dcfclk_sta_targets = 4;
unsigned int num_uclk_states;
dc_assert_fp_enabled();
dc_assert_fp_enabled();
if (dc->ctx->dc_bios->vram_info.num_chans)
dcn3_03_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;
@ -349,14 +349,11 @@ void dcn303_fpu_init_soc_bounding_box(struct bp_soc_bb_info bb_info)
dc_assert_fp_enabled();
if (bb_info.dram_clock_change_latency_100ns > 0)
dcn3_03_soc.dram_clock_change_latency_us =
bb_info.dram_clock_change_latency_100ns * 10;
dcn3_03_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10;
if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
dcn3_03_soc.sr_enter_plus_exit_time_us =
bb_info.dram_sr_enter_exit_latency_100ns * 10;
if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
dcn3_03_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10;
if (bb_info.dram_sr_exit_latency_100ns > 0)
dcn3_03_soc.sr_exit_time_us =
bb_info.dram_sr_exit_latency_100ns * 10;
if (bb_info.dram_sr_exit_latency_100ns > 0)
dcn3_03_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10;
}

8
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
View File

@ -710,10 +710,10 @@ void dml32_CalculateSwathWidth(
unsigned int k, j;
enum odm_combine_mode MainSurfaceODMMode;
unsigned int surface_width_ub_l;
unsigned int surface_height_ub_l;
unsigned int surface_width_ub_c;
unsigned int surface_height_ub_c;
unsigned int surface_width_ub_l;
unsigned int surface_height_ub_l;
unsigned int surface_width_ub_c;
unsigned int surface_height_ub_c;
#ifdef __DML_VBA_DEBUG__
dml_print("DML::%s: ForceSingleDPP = %d\n", __func__, ForceSingleDPP);

81
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
View File

@ -48,9 +48,9 @@ void dml32_rq_dlg_get_rq_reg(display_rq_regs_st *rq_regs,
{
const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src;
bool dual_plane = is_dual_plane((enum source_format_class) (src->source_format));
double stored_swath_l_bytes;
double stored_swath_c_bytes;
bool is_phantom_pipe;
double stored_swath_l_bytes;
double stored_swath_c_bytes;
bool is_phantom_pipe;
uint32_t pixel_chunk_bytes = 0;
uint32_t min_pixel_chunk_bytes = 0;
uint32_t meta_chunk_bytes = 0;
@ -65,9 +65,9 @@ void dml32_rq_dlg_get_rq_reg(display_rq_regs_st *rq_regs,
uint32_t p1_dpte_group_bytes = 0;
uint32_t p1_mpte_group_bytes = 0;
unsigned int detile_buf_size_in_bytes;
unsigned int detile_buf_plane1_addr;
unsigned int pte_row_height_linear;
unsigned int detile_buf_size_in_bytes;
unsigned int detile_buf_plane1_addr;
unsigned int pte_row_height_linear;
memset(rq_regs, 0, sizeof(*rq_regs));
@ -217,52 +217,51 @@ void dml32_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib,
double refcyc_per_req_delivery_cur0 = 0.;
double refcyc_per_req_delivery_pre_c = 0.;
double refcyc_per_req_delivery_c = 0.;
double refcyc_per_req_delivery_pre_l;
double refcyc_per_req_delivery_l;
double refcyc_per_req_delivery_pre_l;
double refcyc_per_req_delivery_l;
double refcyc_per_line_delivery_pre_c = 0.;
double refcyc_per_line_delivery_c = 0.;
double refcyc_per_line_delivery_pre_l;
double refcyc_per_line_delivery_l;
double min_ttu_vblank;
double vratio_pre_l;
double vratio_pre_c;
unsigned int min_dst_y_next_start;
double refcyc_per_line_delivery_pre_l;
double refcyc_per_line_delivery_l;
double min_ttu_vblank;
double vratio_pre_l;
double vratio_pre_c;
unsigned int min_dst_y_next_start;
unsigned int htotal = dst->htotal;
unsigned int hblank_end = dst->hblank_end;
unsigned int vblank_end = dst->vblank_end;
bool interlaced = dst->interlaced;
double pclk_freq_in_mhz = dst->pixel_rate_mhz;
unsigned int vready_after_vcount0;
unsigned int vready_after_vcount0;
double refclk_freq_in_mhz = clks->refclk_mhz;
double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz;
bool dual_plane = 0;
unsigned int pipe_index_in_combine[DC__NUM_PIPES__MAX];
int unsigned dst_x_after_scaler;
int unsigned dst_y_after_scaler;
double dst_y_prefetch;
double dst_y_per_vm_vblank;
double dst_y_per_row_vblank;
double dst_y_per_vm_flip;
double dst_y_per_row_flip;
double max_dst_y_per_vm_vblank = 32.0;
double max_dst_y_per_row_vblank = 16.0;
double dst_y_per_pte_row_nom_l;
double dst_y_per_pte_row_nom_c;
double dst_y_per_meta_row_nom_l;
double dst_y_per_meta_row_nom_c;
double refcyc_per_pte_group_nom_l;
double refcyc_per_pte_group_nom_c;
double refcyc_per_pte_group_vblank_l;
double refcyc_per_pte_group_vblank_c;
double refcyc_per_pte_group_flip_l;
double refcyc_per_pte_group_flip_c;
double refcyc_per_meta_chunk_nom_l;
double refcyc_per_meta_chunk_nom_c;
double refcyc_per_meta_chunk_vblank_l;
double refcyc_per_meta_chunk_vblank_c;
double refcyc_per_meta_chunk_flip_l;
double refcyc_per_meta_chunk_flip_c;
unsigned int dst_x_after_scaler;
unsigned int dst_y_after_scaler;
double dst_y_prefetch;
double dst_y_per_vm_vblank;
double dst_y_per_row_vblank;
double dst_y_per_vm_flip;
double dst_y_per_row_flip;
double max_dst_y_per_vm_vblank = 32.0;
double max_dst_y_per_row_vblank = 16.0;
double dst_y_per_pte_row_nom_l;
double dst_y_per_pte_row_nom_c;
double dst_y_per_meta_row_nom_l;
double dst_y_per_meta_row_nom_c;
double refcyc_per_pte_group_nom_l;
double refcyc_per_pte_group_nom_c;
double refcyc_per_pte_group_vblank_l;
double refcyc_per_pte_group_vblank_c;
double refcyc_per_pte_group_flip_l;
double refcyc_per_pte_group_flip_c;
double refcyc_per_meta_chunk_nom_l;
double refcyc_per_meta_chunk_nom_c;
double refcyc_per_meta_chunk_vblank_l;
double refcyc_per_meta_chunk_vblank_c;
double refcyc_per_meta_chunk_flip_l;
double refcyc_per_meta_chunk_flip_c;
memset(dlg_regs, 0, sizeof(*dlg_regs));
memset(ttu_regs, 0, sizeof(*ttu_regs));

2
drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
View File

@ -302,8 +302,6 @@ struct timing_generator_funcs {
int group_idx,
uint32_t gsl_ready_signal);
void (*set_out_mux)(struct timing_generator *tg, enum otg_out_mux_dest dest);
void (*set_vrr_m_const)(struct timing_generator *optc,
double vtotal_avg);
void (*set_drr_trigger_window)(struct timing_generator *optc,
uint32_t window_start, uint32_t window_end);
void (*set_vtotal_change_limit)(struct timing_generator *optc,

3
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
View File

@ -4221,6 +4221,7 @@
#define regCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX 0
#define regGB_EDC_MODE 0x1e1e
#define regGB_EDC_MODE_BASE_IDX 0
#define regCP_DEBUG 0x1e1f
#define regCP_DEBUG_BASE_IDX 0
#define regCP_CPC_DEBUG 0x1e21
#define regCP_CPC_DEBUG_BASE_IDX 0
@ -8306,6 +8307,8 @@
#define regGL1I_GL1R_REP_FGCG_OVERRIDE_BASE_IDX 1
#define regGL1C_STATUS 0x2d41
#define regGL1C_STATUS_BASE_IDX 1
#define regGL1C_UTCL0_CNTL1 0x2d42
#define regGL1C_UTCL0_CNTL1_BASE_IDX 1
#define regGL1C_UTCL0_CNTL2 0x2d43
#define regGL1C_UTCL0_CNTL2_BASE_IDX 1
#define regGL1C_UTCL0_STATUS 0x2d44

25
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h
View File

@ -29424,6 +29424,31 @@
#define GL1C_STATUS__TAG_EVICT_MASK 0x04000000L
#define GL1C_STATUS__TAG_REQUEST_STATE_OPERATION_MASK 0x78000000L
#define GL1C_STATUS__TRACKER_LAST_SET_MATCHES_CURRENT_SET_MASK 0x80000000L
//GL1C_UTCL0_CNTL1
#define GL1C_UTCL0_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
#define GL1C_UTCL0_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
#define GL1C_UTCL0_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
#define GL1C_UTCL0_CNTL1__RESP_MODE__SHIFT 0x3
#define GL1C_UTCL0_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
#define GL1C_UTCL0_CNTL1__CLIENTID__SHIFT 0x7
#define GL1C_UTCL0_CNTL1__REG_INV_VMID__SHIFT 0x13
#define GL1C_UTCL0_CNTL1__REG_INV_TOGGLE__SHIFT 0x18
#define GL1C_UTCL0_CNTL1__FORCE_MISS__SHIFT 0x1a
#define GL1C_UTCL0_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
#define GL1C_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
#define GL1C_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
#define GL1C_UTCL0_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
#define GL1C_UTCL0_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
#define GL1C_UTCL0_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
#define GL1C_UTCL0_CNTL1__RESP_MODE_MASK 0x00000018L
#define GL1C_UTCL0_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
#define GL1C_UTCL0_CNTL1__CLIENTID_MASK 0x0000FF80L
#define GL1C_UTCL0_CNTL1__REG_INV_VMID_MASK 0x00780000L
#define GL1C_UTCL0_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L
#define GL1C_UTCL0_CNTL1__FORCE_MISS_MASK 0x04000000L
#define GL1C_UTCL0_CNTL1__FORCE_IN_ORDER_MASK 0x06000000L
#define GL1C_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
#define GL1C_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
//GL1C_UTCL0_CNTL2
#define GL1C_UTCL0_CNTL2__SPARE__SHIFT 0x0
#define GL1C_UTCL0_CNTL2__COMP_SYNC_DISABLE__SHIFT 0x8

402
drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_4_offset.h Normal file
View File

@ -0,0 +1,402 @@
/*
* Copyright 2020 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*
*/
#ifndef _mp_13_0_4_OFFSET_HEADER
#define _mp_13_0_4_OFFSET_HEADER
// addressBlock: mp_SmuMp0_SmnDec
// base address: 0x0
#define regMP0_SMN_C2PMSG_32 0x0060
#define regMP0_SMN_C2PMSG_32_BASE_IDX 1
#define regMP0_SMN_C2PMSG_33 0x0061
#define regMP0_SMN_C2PMSG_33_BASE_IDX 1
#define regMP0_SMN_C2PMSG_34 0x0062
#define regMP0_SMN_C2PMSG_34_BASE_IDX 1
#define regMP0_SMN_C2PMSG_35 0x0063
#define regMP0_SMN_C2PMSG_35_BASE_IDX 1
#define regMP0_SMN_C2PMSG_36 0x0064
#define regMP0_SMN_C2PMSG_36_BASE_IDX 1
#define regMP0_SMN_C2PMSG_37 0x0065
#define regMP0_SMN_C2PMSG_37_BASE_IDX 1
#define regMP0_SMN_C2PMSG_38 0x0066
#define regMP0_SMN_C2PMSG_38_BASE_IDX 1
#define regMP0_SMN_C2PMSG_39 0x0067
#define regMP0_SMN_C2PMSG_39_BASE_IDX 1
#define regMP0_SMN_C2PMSG_40 0x0068
#define regMP0_SMN_C2PMSG_40_BASE_IDX 1
#define regMP0_SMN_C2PMSG_41 0x0069
#define regMP0_SMN_C2PMSG_41_BASE_IDX 1
#define regMP0_SMN_C2PMSG_42 0x006a
#define regMP0_SMN_C2PMSG_42_BASE_IDX 1
#define regMP0_SMN_C2PMSG_43 0x006b
#define regMP0_SMN_C2PMSG_43_BASE_IDX 1
#define regMP0_SMN_C2PMSG_44 0x006c
#define regMP0_SMN_C2PMSG_44_BASE_IDX 1
#define regMP0_SMN_C2PMSG_45 0x006d
#define regMP0_SMN_C2PMSG_45_BASE_IDX 1
#define regMP0_SMN_C2PMSG_46 0x006e
#define regMP0_SMN_C2PMSG_46_BASE_IDX 1
#define regMP0_SMN_C2PMSG_47 0x006f
#define regMP0_SMN_C2PMSG_47_BASE_IDX 1
#define regMP0_SMN_C2PMSG_48 0x0070
#define regMP0_SMN_C2PMSG_48_BASE_IDX 1
#define regMP0_SMN_C2PMSG_49 0x0071
#define regMP0_SMN_C2PMSG_49_BASE_IDX 1
#define regMP0_SMN_C2PMSG_50 0x0072
#define regMP0_SMN_C2PMSG_50_BASE_IDX 1
#define regMP0_SMN_C2PMSG_51 0x0073
#define regMP0_SMN_C2PMSG_51_BASE_IDX 1
#define regMP0_SMN_C2PMSG_52 0x0074
#define regMP0_SMN_C2PMSG_52_BASE_IDX 1
#define regMP0_SMN_C2PMSG_53 0x0075
#define regMP0_SMN_C2PMSG_53_BASE_IDX 1
#define regMP0_SMN_C2PMSG_54 0x0076
#define regMP0_SMN_C2PMSG_54_BASE_IDX 1
#define regMP0_SMN_C2PMSG_55 0x0077
#define regMP0_SMN_C2PMSG_55_BASE_IDX 1
#define regMP0_SMN_C2PMSG_56 0x0078
#define regMP0_SMN_C2PMSG_56_BASE_IDX 1
#define regMP0_SMN_C2PMSG_57 0x0079
#define regMP0_SMN_C2PMSG_57_BASE_IDX 1
#define regMP0_SMN_C2PMSG_58 0x007a
#define regMP0_SMN_C2PMSG_58_BASE_IDX 1
#define regMP0_SMN_C2PMSG_59 0x007b
#define regMP0_SMN_C2PMSG_59_BASE_IDX 1
#define regMP0_SMN_C2PMSG_60 0x007c
#define regMP0_SMN_C2PMSG_60_BASE_IDX 1
#define regMP0_SMN_C2PMSG_61 0x007d
#define regMP0_SMN_C2PMSG_61_BASE_IDX 1
#define regMP0_SMN_C2PMSG_62 0x007e
#define regMP0_SMN_C2PMSG_62_BASE_IDX 1
#define regMP0_SMN_C2PMSG_63 0x007f
#define regMP0_SMN_C2PMSG_63_BASE_IDX 1
#define regMP0_SMN_C2PMSG_64 0x0080
#define regMP0_SMN_C2PMSG_64_BASE_IDX 1
#define regMP0_SMN_C2PMSG_65 0x0081
#define regMP0_SMN_C2PMSG_65_BASE_IDX 1
#define regMP0_SMN_C2PMSG_66 0x0082
#define regMP0_SMN_C2PMSG_66_BASE_IDX 1
#define regMP0_SMN_C2PMSG_67 0x0083
#define regMP0_SMN_C2PMSG_67_BASE_IDX 1
#define regMP0_SMN_C2PMSG_68 0x0084
#define regMP0_SMN_C2PMSG_68_BASE_IDX 1
#define regMP0_SMN_C2PMSG_69 0x0085
#define regMP0_SMN_C2PMSG_69_BASE_IDX 1
#define regMP0_SMN_C2PMSG_70 0x0086
#define regMP0_SMN_C2PMSG_70_BASE_IDX 1
#define regMP0_SMN_C2PMSG_71 0x0087
#define regMP0_SMN_C2PMSG_71_BASE_IDX 1
#define regMP0_SMN_C2PMSG_72 0x0088
#define regMP0_SMN_C2PMSG_72_BASE_IDX 1
#define regMP0_SMN_C2PMSG_73 0x0089
#define regMP0_SMN_C2PMSG_73_BASE_IDX 1
#define regMP0_SMN_C2PMSG_74 0x008a
#define regMP0_SMN_C2PMSG_74_BASE_IDX 1
#define regMP0_SMN_C2PMSG_75 0x008b
#define regMP0_SMN_C2PMSG_75_BASE_IDX 1
#define regMP0_SMN_C2PMSG_76 0x008c
#define regMP0_SMN_C2PMSG_76_BASE_IDX 1
#define regMP0_SMN_C2PMSG_77 0x008d
#define regMP0_SMN_C2PMSG_77_BASE_IDX 1
#define regMP0_SMN_C2PMSG_78 0x008e
#define regMP0_SMN_C2PMSG_78_BASE_IDX 1
#define regMP0_SMN_C2PMSG_79 0x008f
#define regMP0_SMN_C2PMSG_79_BASE_IDX 1
#define regMP0_SMN_C2PMSG_80 0x0090
#define regMP0_SMN_C2PMSG_80_BASE_IDX 1
#define regMP0_SMN_C2PMSG_81 0x0091
#define regMP0_SMN_C2PMSG_81_BASE_IDX 1
#define regMP0_SMN_C2PMSG_82 0x0092
#define regMP0_SMN_C2PMSG_82_BASE_IDX 1
#define regMP0_SMN_C2PMSG_83 0x0093
#define regMP0_SMN_C2PMSG_83_BASE_IDX 1
#define regMP0_SMN_C2PMSG_84 0x0094
#define regMP0_SMN_C2PMSG_84_BASE_IDX 1
#define regMP0_SMN_C2PMSG_85 0x0095
#define regMP0_SMN_C2PMSG_85_BASE_IDX 1
#define regMP0_SMN_C2PMSG_86 0x0096
#define regMP0_SMN_C2PMSG_86_BASE_IDX 1
#define regMP0_SMN_C2PMSG_87 0x0097
#define regMP0_SMN_C2PMSG_87_BASE_IDX 1
#define regMP0_SMN_C2PMSG_88 0x0098
#define regMP0_SMN_C2PMSG_88_BASE_IDX 1
#define regMP0_SMN_C2PMSG_89 0x0099
#define regMP0_SMN_C2PMSG_89_BASE_IDX 1
#define regMP0_SMN_C2PMSG_90 0x009a
#define regMP0_SMN_C2PMSG_90_BASE_IDX 1
#define regMP0_SMN_C2PMSG_91 0x009b
#define regMP0_SMN_C2PMSG_91_BASE_IDX 1
#define regMP0_SMN_C2PMSG_92 0x009c
#define regMP0_SMN_C2PMSG_92_BASE_IDX 1
#define regMP0_SMN_C2PMSG_93 0x009d
#define regMP0_SMN_C2PMSG_93_BASE_IDX 1
#define regMP0_SMN_C2PMSG_94 0x009e
#define regMP0_SMN_C2PMSG_94_BASE_IDX 1
#define regMP0_SMN_C2PMSG_95 0x009f
#define regMP0_SMN_C2PMSG_95_BASE_IDX 1
#define regMP0_SMN_C2PMSG_96 0x00a0
#define regMP0_SMN_C2PMSG_96_BASE_IDX 1
#define regMP0_SMN_C2PMSG_97 0x00a1
#define regMP0_SMN_C2PMSG_97_BASE_IDX 1
#define regMP0_SMN_C2PMSG_98 0x00a2
#define regMP0_SMN_C2PMSG_98_BASE_IDX 1
#define regMP0_SMN_C2PMSG_99 0x00a3
#define regMP0_SMN_C2PMSG_99_BASE_IDX 1
#define regMP0_SMN_C2PMSG_100 0x00a4
#define regMP0_SMN_C2PMSG_100_BASE_IDX 1
#define regMP0_SMN_C2PMSG_101 0x00a5
#define regMP0_SMN_C2PMSG_101_BASE_IDX 1
#define regMP0_SMN_C2PMSG_102 0x00a6
#define regMP0_SMN_C2PMSG_102_BASE_IDX 1
#define regMP0_SMN_C2PMSG_103 0x00a7
#define regMP0_SMN_C2PMSG_103_BASE_IDX 1
#define regMP0_SMN_C2PMSG_104 0x00a8
#define regMP0_SMN_C2PMSG_104_BASE_IDX 1
#define regMP0_SMN_C2PMSG_105 0x00a9
#define regMP0_SMN_C2PMSG_105_BASE_IDX 1
#define regMP0_SMN_C2PMSG_106 0x00aa
#define regMP0_SMN_C2PMSG_106_BASE_IDX 1
#define regMP0_SMN_C2PMSG_107 0x00ab
#define regMP0_SMN_C2PMSG_107_BASE_IDX 1
#define regMP0_SMN_C2PMSG_108 0x00ac
#define regMP0_SMN_C2PMSG_108_BASE_IDX 1
#define regMP0_SMN_C2PMSG_109 0x00ad
#define regMP0_SMN_C2PMSG_109_BASE_IDX 1
#define regMP0_SMN_C2PMSG_110 0x00ae
#define regMP0_SMN_C2PMSG_110_BASE_IDX 1
#define regMP0_SMN_C2PMSG_111 0x00af
#define regMP0_SMN_C2PMSG_111_BASE_IDX 1
#define regMP0_SMN_C2PMSG_112 0x00b0
#define regMP0_SMN_C2PMSG_112_BASE_IDX 1
#define regMP0_SMN_C2PMSG_113 0x00b1
#define regMP0_SMN_C2PMSG_113_BASE_IDX 1
#define regMP0_SMN_C2PMSG_114 0x00b2
#define regMP0_SMN_C2PMSG_114_BASE_IDX 1
#define regMP0_SMN_C2PMSG_115 0x00b3
#define regMP0_SMN_C2PMSG_115_BASE_IDX 1
#define regMP0_SMN_C2PMSG_116 0x00b4
#define regMP0_SMN_C2PMSG_116_BASE_IDX 1
#define regMP0_SMN_C2PMSG_117 0x00b5
#define regMP0_SMN_C2PMSG_117_BASE_IDX 1
#define regMP0_SMN_C2PMSG_118 0x00b6
#define regMP0_SMN_C2PMSG_118_BASE_IDX 1
#define regMP0_SMN_C2PMSG_119 0x00b7
#define regMP0_SMN_C2PMSG_119_BASE_IDX 1
#define regMP0_SMN_C2PMSG_120 0x00b8
#define regMP0_SMN_C2PMSG_120_BASE_IDX 1
#define regMP0_SMN_C2PMSG_121 0x00b9
#define regMP0_SMN_C2PMSG_121_BASE_IDX 1
#define regMP0_SMN_C2PMSG_122 0x00ba
#define regMP0_SMN_C2PMSG_122_BASE_IDX 1
#define regMP0_SMN_C2PMSG_123 0x00bb
#define regMP0_SMN_C2PMSG_123_BASE_IDX 1
#define regMP0_SMN_C2PMSG_124 0x00bc
#define regMP0_SMN_C2PMSG_124_BASE_IDX 1
#define regMP0_SMN_C2PMSG_125 0x00bd
#define regMP0_SMN_C2PMSG_125_BASE_IDX 1
#define regMP0_SMN_C2PMSG_126 0x00be
#define regMP0_SMN_C2PMSG_126_BASE_IDX 1
#define regMP0_SMN_C2PMSG_127 0x00bf
#define regMP0_SMN_C2PMSG_127_BASE_IDX 1
#define regMP0_SMN_IH_CREDIT 0x00c1
#define regMP0_SMN_IH_CREDIT_BASE_IDX 1
#define regMP0_SMN_IH_SW_INT 0x00c2
#define regMP0_SMN_IH_SW_INT_BASE_IDX 1
#define regMP0_SMN_IH_SW_INT_CTRL 0x00c3
#define regMP0_SMN_IH_SW_INT_CTRL_BASE_IDX 1
// addressBlock: mp_SmuMp1_SmnDec
// base address: 0x0
#define regMP1_SMN_C2PMSG_32 0x0260
#define regMP1_SMN_C2PMSG_32_BASE_IDX 1
#define regMP1_SMN_C2PMSG_33 0x0261
#define regMP1_SMN_C2PMSG_33_BASE_IDX 1
#define regMP1_SMN_C2PMSG_34 0x0262
#define regMP1_SMN_C2PMSG_34_BASE_IDX 1
#define regMP1_SMN_C2PMSG_35 0x0263
#define regMP1_SMN_C2PMSG_35_BASE_IDX 1
#define regMP1_SMN_C2PMSG_36 0x0264
#define regMP1_SMN_C2PMSG_36_BASE_IDX 1
#define regMP1_SMN_C2PMSG_37 0x0265
#define regMP1_SMN_C2PMSG_37_BASE_IDX 1
#define regMP1_SMN_C2PMSG_38 0x0266
#define regMP1_SMN_C2PMSG_38_BASE_IDX 1
#define regMP1_SMN_C2PMSG_39 0x0267
#define regMP1_SMN_C2PMSG_39_BASE_IDX 1
#define regMP1_SMN_C2PMSG_40 0x0268
#define regMP1_SMN_C2PMSG_40_BASE_IDX 1
#define regMP1_SMN_C2PMSG_41 0x0269
#define regMP1_SMN_C2PMSG_41_BASE_IDX 1
#define regMP1_SMN_C2PMSG_42 0x026a
#define regMP1_SMN_C2PMSG_42_BASE_IDX 1
#define regMP1_SMN_C2PMSG_43 0x026b
#define regMP1_SMN_C2PMSG_43_BASE_IDX 1
#define regMP1_SMN_C2PMSG_44 0x026c
#define regMP1_SMN_C2PMSG_44_BASE_IDX 1
#define regMP1_SMN_C2PMSG_45 0x026d
#define regMP1_SMN_C2PMSG_45_BASE_IDX 1
#define regMP1_SMN_C2PMSG_46 0x026e
#define regMP1_SMN_C2PMSG_46_BASE_IDX 1
#define regMP1_SMN_C2PMSG_47 0x026f
#define regMP1_SMN_C2PMSG_47_BASE_IDX 1
#define regMP1_SMN_C2PMSG_48 0x0270
#define regMP1_SMN_C2PMSG_48_BASE_IDX 1
#define regMP1_SMN_C2PMSG_49 0x0271
#define regMP1_SMN_C2PMSG_49_BASE_IDX 1
#define regMP1_SMN_C2PMSG_50 0x0272
#define regMP1_SMN_C2PMSG_50_BASE_IDX 1
#define regMP1_SMN_C2PMSG_51 0x0273
#define regMP1_SMN_C2PMSG_51_BASE_IDX 1
#define regMP1_SMN_C2PMSG_52 0x0274
#define regMP1_SMN_C2PMSG_52_BASE_IDX 1
#define regMP1_SMN_C2PMSG_53 0x0275
#define regMP1_SMN_C2PMSG_53_BASE_IDX 1
#define regMP1_SMN_C2PMSG_54 0x0276
#define regMP1_SMN_C2PMSG_54_BASE_IDX 1
#define regMP1_SMN_C2PMSG_55 0x0277
#define regMP1_SMN_C2PMSG_55_BASE_IDX 1
#define regMP1_SMN_C2PMSG_56 0x0278
#define regMP1_SMN_C2PMSG_56_BASE_IDX 1
#define regMP1_SMN_C2PMSG_57 0x0279
#define regMP1_SMN_C2PMSG_57_BASE_IDX 1
#define regMP1_SMN_C2PMSG_58 0x027a
#define regMP1_SMN_C2PMSG_58_BASE_IDX 1
#define regMP1_SMN_C2PMSG_59 0x027b
#define regMP1_SMN_C2PMSG_59_BASE_IDX 1
#define regMP1_SMN_C2PMSG_60 0x027c
#define regMP1_SMN_C2PMSG_60_BASE_IDX 1
#define regMP1_SMN_C2PMSG_61 0x027d
#define regMP1_SMN_C2PMSG_61_BASE_IDX 1
#define regMP1_SMN_C2PMSG_62 0x027e
#define regMP1_SMN_C2PMSG_62_BASE_IDX 1
#define regMP1_SMN_C2PMSG_63 0x027f
#define regMP1_SMN_C2PMSG_63_BASE_IDX 1
#define regMP1_SMN_C2PMSG_64 0x0280
#define regMP1_SMN_C2PMSG_64_BASE_IDX 1
#define regMP1_SMN_C2PMSG_65 0x0281
#define regMP1_SMN_C2PMSG_65_BASE_IDX 1
#define regMP1_SMN_C2PMSG_66 0x0282
#define regMP1_SMN_C2PMSG_66_BASE_IDX 1
#define regMP1_SMN_C2PMSG_67 0x0283
#define regMP1_SMN_C2PMSG_67_BASE_IDX 1
#define regMP1_SMN_C2PMSG_68 0x0284
#define regMP1_SMN_C2PMSG_68_BASE_IDX 1
#define regMP1_SMN_C2PMSG_69 0x0285
#define regMP1_SMN_C2PMSG_69_BASE_IDX 1
#define regMP1_SMN_C2PMSG_70 0x0286
#define regMP1_SMN_C2PMSG_70_BASE_IDX 1
#define regMP1_SMN_C2PMSG_71 0x0287
#define regMP1_SMN_C2PMSG_71_BASE_IDX 1
#define regMP1_SMN_C2PMSG_72 0x0288
#define regMP1_SMN_C2PMSG_72_BASE_IDX 1
#define regMP1_SMN_C2PMSG_73 0x0289
#define regMP1_SMN_C2PMSG_73_BASE_IDX 1
#define regMP1_SMN_C2PMSG_74 0x028a
#define regMP1_SMN_C2PMSG_74_BASE_IDX 1
#define regMP1_SMN_C2PMSG_75 0x028b
#define regMP1_SMN_C2PMSG_75_BASE_IDX 1
#define regMP1_SMN_C2PMSG_76 0x028c
#define regMP1_SMN_C2PMSG_76_BASE_IDX 1
#define regMP1_SMN_C2PMSG_77 0x028d
#define regMP1_SMN_C2PMSG_77_BASE_IDX 1
#define regMP1_SMN_C2PMSG_78 0x028e
#define regMP1_SMN_C2PMSG_78_BASE_IDX 1
#define regMP1_SMN_C2PMSG_79 0x028f
#define regMP1_SMN_C2PMSG_79_BASE_IDX 1
#define regMP1_SMN_C2PMSG_80 0x0290
#define regMP1_SMN_C2PMSG_80_BASE_IDX 1
#define regMP1_SMN_C2PMSG_81 0x0291
#define regMP1_SMN_C2PMSG_81_BASE_IDX 1
#define regMP1_SMN_C2PMSG_82 0x0292
#define regMP1_SMN_C2PMSG_82_BASE_IDX 1
#define regMP1_SMN_C2PMSG_83 0x0293
#define regMP1_SMN_C2PMSG_83_BASE_IDX 1
#define regMP1_SMN_C2PMSG_84 0x0294
#define regMP1_SMN_C2PMSG_84_BASE_IDX 1
#define regMP1_SMN_C2PMSG_85 0x0295
#define regMP1_SMN_C2PMSG_85_BASE_IDX 1
#define regMP1_SMN_C2PMSG_86 0x0296
#define regMP1_SMN_C2PMSG_86_BASE_IDX 1
#define regMP1_SMN_C2PMSG_87 0x0297
#define regMP1_SMN_C2PMSG_87_BASE_IDX 1
#define regMP1_SMN_C2PMSG_88 0x0298
#define regMP1_SMN_C2PMSG_88_BASE_IDX 1
#define regMP1_SMN_C2PMSG_89 0x0299
#define regMP1_SMN_C2PMSG_89_BASE_IDX 1
#define regMP1_SMN_C2PMSG_90 0x029a
#define regMP1_SMN_C2PMSG_90_BASE_IDX 1
#define regMP1_SMN_C2PMSG_91 0x029b
#define regMP1_SMN_C2PMSG_91_BASE_IDX 1
#define regMP1_SMN_C2PMSG_92 0x029c
#define regMP1_SMN_C2PMSG_92_BASE_IDX 1
#define regMP1_SMN_C2PMSG_93 0x029d
#define regMP1_SMN_C2PMSG_93_BASE_IDX 1
#define regMP1_SMN_C2PMSG_94 0x029e
#define regMP1_SMN_C2PMSG_94_BASE_IDX 1
#define regMP1_SMN_C2PMSG_95 0x029f
#define regMP1_SMN_C2PMSG_95_BASE_IDX 1
#define regMP1_SMN_C2PMSG_96 0x02a0
#define regMP1_SMN_C2PMSG_96_BASE_IDX 1
#define regMP1_SMN_C2PMSG_97 0x02a1
#define regMP1_SMN_C2PMSG_97_BASE_IDX 1
#define regMP1_SMN_C2PMSG_98 0x02a2
#define regMP1_SMN_C2PMSG_98_BASE_IDX 1
#define regMP1_SMN_C2PMSG_99 0x02a3
#define regMP1_SMN_C2PMSG_99_BASE_IDX 1
#define regMP1_SMN_C2PMSG_100 0x02a4
#define regMP1_SMN_C2PMSG_100_BASE_IDX 1
#define regMP1_SMN_C2PMSG_101 0x02a5
#define regMP1_SMN_C2PMSG_101_BASE_IDX 1
#define regMP1_SMN_C2PMSG_102 0x02a6
#define regMP1_SMN_C2PMSG_102_BASE_IDX 1
#define regMP1_SMN_C2PMSG_103 0x02a7
#define regMP1_SMN_C2PMSG_103_BASE_IDX 1
#define regMP1_SMN_IH_CREDIT 0x02c1
#define regMP1_SMN_IH_CREDIT_BASE_IDX 1
#define regMP1_SMN_IH_SW_INT 0x02c2
#define regMP1_SMN_IH_SW_INT_BASE_IDX 1
#define regMP1_SMN_IH_SW_INT_CTRL 0x02c3
#define regMP1_SMN_IH_SW_INT_CTRL_BASE_IDX 1
#define regMP1_SMN_FPS_CNT 0x02c4
#define regMP1_SMN_FPS_CNT_BASE_IDX 1
#define regMP1_SMN_EXT_SCRATCH0 0x0340
#define regMP1_SMN_EXT_SCRATCH0_BASE_IDX 1
#define regMP1_SMN_EXT_SCRATCH1 0x0341
#define regMP1_SMN_EXT_SCRATCH1_BASE_IDX 1
#define regMP1_SMN_EXT_SCRATCH2 0x0342
#define regMP1_SMN_EXT_SCRATCH2_BASE_IDX 1
#define regMP1_SMN_EXT_SCRATCH3 0x0343
#define regMP1_SMN_EXT_SCRATCH3_BASE_IDX 1
#define regMP1_SMN_EXT_SCRATCH4 0x0344
#define regMP1_SMN_EXT_SCRATCH4_BASE_IDX 1
#define regMP1_SMN_EXT_SCRATCH5 0x0345
#define regMP1_SMN_EXT_SCRATCH5_BASE_IDX 1
#define regMP1_SMN_EXT_SCRATCH6 0x0346
#define regMP1_SMN_EXT_SCRATCH6_BASE_IDX 1
#define regMP1_SMN_EXT_SCRATCH7 0x0347
#define regMP1_SMN_EXT_SCRATCH7_BASE_IDX 1
#endif

595
drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_4_sh_mask.h Normal file
View File

@ -0,0 +1,595 @@
/*
* Copyright 2020 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*
*/
#ifndef _mp_13_0_4_SH_MASK_HEADER
#define _mp_13_0_4_SH_MASK_HEADER
// addressBlock: mp_SmuMp0_SmnDec
//MP0_SMN_C2PMSG_32
#define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_33
#define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_34
#define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_35
#define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_36
#define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_37
#define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_38
#define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_39
#define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_40
#define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_41
#define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_42
#define MP0_SMN_C2PMSG_42__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_43
#define MP0_SMN_C2PMSG_43__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_44
#define MP0_SMN_C2PMSG_44__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_45
#define MP0_SMN_C2PMSG_45__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_46
#define MP0_SMN_C2PMSG_46__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_47
#define MP0_SMN_C2PMSG_47__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_48
#define MP0_SMN_C2PMSG_48__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_49
#define MP0_SMN_C2PMSG_49__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_50
#define MP0_SMN_C2PMSG_50__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_51
#define MP0_SMN_C2PMSG_51__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_52
#define MP0_SMN_C2PMSG_52__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_53
#define MP0_SMN_C2PMSG_53__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_54
#define MP0_SMN_C2PMSG_54__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_55
#define MP0_SMN_C2PMSG_55__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_56
#define MP0_SMN_C2PMSG_56__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_57
#define MP0_SMN_C2PMSG_57__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_58
#define MP0_SMN_C2PMSG_58__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_59
#define MP0_SMN_C2PMSG_59__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_60
#define MP0_SMN_C2PMSG_60__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_61
#define MP0_SMN_C2PMSG_61__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_62
#define MP0_SMN_C2PMSG_62__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_63
#define MP0_SMN_C2PMSG_63__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_64
#define MP0_SMN_C2PMSG_64__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_65
#define MP0_SMN_C2PMSG_65__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_66
#define MP0_SMN_C2PMSG_66__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_67
#define MP0_SMN_C2PMSG_67__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_68
#define MP0_SMN_C2PMSG_68__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_69
#define MP0_SMN_C2PMSG_69__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_70
#define MP0_SMN_C2PMSG_70__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_71
#define MP0_SMN_C2PMSG_71__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_72
#define MP0_SMN_C2PMSG_72__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_73
#define MP0_SMN_C2PMSG_73__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_74
#define MP0_SMN_C2PMSG_74__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_75
#define MP0_SMN_C2PMSG_75__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_76
#define MP0_SMN_C2PMSG_76__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_77
#define MP0_SMN_C2PMSG_77__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_78
#define MP0_SMN_C2PMSG_78__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_79
#define MP0_SMN_C2PMSG_79__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_80
#define MP0_SMN_C2PMSG_80__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_81
#define MP0_SMN_C2PMSG_81__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_82
#define MP0_SMN_C2PMSG_82__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_83
#define MP0_SMN_C2PMSG_83__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_84
#define MP0_SMN_C2PMSG_84__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_85
#define MP0_SMN_C2PMSG_85__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_86
#define MP0_SMN_C2PMSG_86__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_87
#define MP0_SMN_C2PMSG_87__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_88
#define MP0_SMN_C2PMSG_88__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_89
#define MP0_SMN_C2PMSG_89__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_90
#define MP0_SMN_C2PMSG_90__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_91
#define MP0_SMN_C2PMSG_91__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_92
#define MP0_SMN_C2PMSG_92__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_93
#define MP0_SMN_C2PMSG_93__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_94
#define MP0_SMN_C2PMSG_94__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_95
#define MP0_SMN_C2PMSG_95__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_96
#define MP0_SMN_C2PMSG_96__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_97
#define MP0_SMN_C2PMSG_97__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_98
#define MP0_SMN_C2PMSG_98__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_99
#define MP0_SMN_C2PMSG_99__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_100
#define MP0_SMN_C2PMSG_100__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_101
#define MP0_SMN_C2PMSG_101__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_102
#define MP0_SMN_C2PMSG_102__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_103
#define MP0_SMN_C2PMSG_103__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_IH_CREDIT
#define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
#define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10
#define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
#define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
//MP0_SMN_IH_SW_INT
#define MP0_SMN_IH_SW_INT__ID__SHIFT 0x0
#define MP0_SMN_IH_SW_INT__VALID__SHIFT 0x8
#define MP0_SMN_IH_SW_INT__ID_MASK 0x000000FFL
#define MP0_SMN_IH_SW_INT__VALID_MASK 0x00000100L
//MP0_SMN_IH_SW_INT_CTRL
#define MP0_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0
#define MP0_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8
#define MP0_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L
#define MP0_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L
// addressBlock: mp_SmuMp1_SmnDec
//MP1_SMN_C2PMSG_32
#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_33
#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_34
#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_35
#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_36
#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_37
#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_38
#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_39
#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_40
#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_41
#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_42
#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_43
#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_44
#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_45
#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_46
#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_47
#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_48
#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_49
#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_50
#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_51
#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_52
#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_53
#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_54
#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_55
#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_56
#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_57
#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_58
#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_59
#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_60
#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_61
#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_62
#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_63
#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_64
#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_65
#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_66
#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_67
#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_68
#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_69
#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_70
#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_71
#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_72
#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_73
#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_74
#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_75
#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_76
#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_77
#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_78
#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_79
#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_80
#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_81
#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_82
#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_83
#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_84
#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_85
#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_86
#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_87
#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_88
#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_89
#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_90
#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_91
#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_92
#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_93
#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_94
#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_95
#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_96
#define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_97
#define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_98
#define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_99
#define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_100
#define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_101
#define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_102
#define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_103
#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_104
#define MP1_SMN_C2PMSG_104__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_104__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_105
#define MP1_SMN_C2PMSG_105__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_105__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_106
#define MP1_SMN_C2PMSG_106__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_106__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_107
#define MP1_SMN_C2PMSG_107__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_107__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_108
#define MP1_SMN_C2PMSG_108__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_108__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_109
#define MP1_SMN_C2PMSG_109__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_109__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_110
#define MP1_SMN_C2PMSG_110__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_110__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_111
#define MP1_SMN_C2PMSG_111__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_111__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_112
#define MP1_SMN_C2PMSG_112__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_112__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_113
#define MP1_SMN_C2PMSG_113__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_113__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_114
#define MP1_SMN_C2PMSG_114__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_114__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_115
#define MP1_SMN_C2PMSG_115__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_115__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_116
#define MP1_SMN_C2PMSG_116__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_116__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_117
#define MP1_SMN_C2PMSG_117__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_117__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_118
#define MP1_SMN_C2PMSG_118__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_118__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_119
#define MP1_SMN_C2PMSG_119__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_119__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_120
#define MP1_SMN_C2PMSG_120__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_120__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_121
#define MP1_SMN_C2PMSG_121__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_121__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_122
#define MP1_SMN_C2PMSG_122__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_122__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_123
#define MP1_SMN_C2PMSG_123__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_123__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_124
#define MP1_SMN_C2PMSG_124__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_124__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_125
#define MP1_SMN_C2PMSG_125__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_125__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_126
#define MP1_SMN_C2PMSG_126__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_126__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_127
#define MP1_SMN_C2PMSG_127__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_127__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_IH_CREDIT
#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10
#define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
#define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
//MP1_SMN_IH_SW_INT
#define MP1_SMN_IH_SW_INT__ID__SHIFT 0x0
#define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x8
#define MP1_SMN_IH_SW_INT__ID_MASK 0x000000FFL
#define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000100L
//MP1_SMN_IH_SW_INT_CTRL
#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0
#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8
#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L
#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L
//MP1_SMN_FPS_CNT
#define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0
#define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH0
#define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH1
#define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH2
#define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH3
#define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH4
#define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH5
#define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH6
#define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH7
#define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL
#endif

9
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
View File

@ -1361,6 +1361,15 @@ static int smu_hw_init(void *handle)
}
if (smu->is_apu) {
if ((smu->ppt_funcs->set_gfx_power_up_by_imu) &&
likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu);
if (ret) {
dev_err(adev->dev, "Failed to Enable gfx imu!\n");
return ret;
}
}
smu_dpm_set_vcn_enable(smu, true);
smu_dpm_set_jpeg_enable(smu, true);
smu_set_gfx_cgpg(smu, true);

2
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h
View File

@ -97,7 +97,7 @@
#define FEATURE_MEM_TEMP_READ_BIT 47
#define FEATURE_ATHUB_MMHUB_PG_BIT 48
#define FEATURE_SOC_PCC_BIT 49
#define FEATURE_SPARE_50_BIT 50
#define FEATURE_EDC_PWRBRK_BIT 50
#define FEATURE_SPARE_51_BIT 51
#define FEATURE_SPARE_52_BIT 52
#define FEATURE_SPARE_53_BIT 53

2
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
View File

@ -30,7 +30,7 @@
#define SMU13_DRIVER_IF_VERSION_ALDE 0x08
#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_4 0x04
#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_5 0x04
#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0 0x2B
#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0 0x2C
#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_7 0x2C
#define SMU13_MODE1_RESET_WAIT_TIME_IN_MS 500 //500ms

3
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
View File

@ -313,6 +313,9 @@ smu_v13_0_0_get_allowed_feature_mask(struct smu_context *smu,
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT);
if (adev->pm.pp_feature & PP_ULV_MASK)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
return 0;
}

31
drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
View File

@ -42,6 +42,11 @@
#undef pr_info
#undef pr_debug
#define regSMUIO_GFX_MISC_CNTL 0x00c5
#define regSMUIO_GFX_MISC_CNTL_BASE_IDX 0
#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK 0x00000006L
#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT 0x1L
#define FEATURE_MASK(feature) (1ULL << feature)
#define SMC_DPM_FEATURE ( \
FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
@ -587,6 +592,31 @@ static ssize_t yellow_carp_get_gpu_metrics(struct smu_context *smu,
return sizeof(struct gpu_metrics_v2_1);
}
/**
* yellow_carp_get_gfxoff_status - get gfxoff status
*
* @smu: smu_context pointer
*
* This function will be used to get gfxoff status
*
* Returns 0=GFXOFF(default).
* Returns 1=Transition out of GFX State.
* Returns 2=Not in GFXOFF.
* Returns 3=Transition into GFXOFF.
*/
static uint32_t yellow_carp_get_gfxoff_status(struct smu_context *smu)
{
uint32_t reg;
uint32_t gfxoff_status = 0;
struct amdgpu_device *adev = smu->adev;
reg = RREG32_SOC15(SMUIO, 0, regSMUIO_GFX_MISC_CNTL);
gfxoff_status = (reg & SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK)
>> SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT;
return gfxoff_status;
}
static int yellow_carp_set_default_dpm_tables(struct smu_context *smu)
{
struct smu_table_context *smu_table = &smu->smu_table;
@ -1186,6 +1216,7 @@ static const struct pptable_funcs yellow_carp_ppt_funcs = {
.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
.set_driver_table_location = smu_v13_0_set_driver_table_location,
.gfx_off_control = smu_v13_0_gfx_off_control,
.get_gfx_off_status = yellow_carp_get_gfxoff_status,
.post_init = yellow_carp_post_smu_init,
.mode2_reset = yellow_carp_mode2_reset,
.get_dpm_ultimate_freq = yellow_carp_get_dpm_ultimate_freq,