forked from Minki/linux
Merge branch 'ftgmac100-rework-batch-1-Link-and-Interrupts'
Benjamin Herrenschmidt says: ==================== ftgmac100: Rework batch 1 - Link & Interrupts This is version 2 of the first batch of updates to the ftgmac100 driver. Essentially: - A few misc cleanups - Fixing link speed & duplex handling (including dealing with an Aspeed requirement to double reset the controller when the speed changes) - And addition of a reset task workqueue which will be used for delaying the re-initialization of the controller - Fixing a number of issues with how interrupts and NAPI are dealt with. Subsequent batches will rework and improve the rx path, the tx path, and add a bunch of features and fixes. Version 2 addresses some review comments to patches 5 and 10 (see version history in the respective emails). ==================== Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
540c86f3ed
@ -46,52 +46,51 @@
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#define MAX_PKT_SIZE 1518
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#define RX_BUF_SIZE PAGE_SIZE /* must be smaller than 0x3fff */
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/******************************************************************************
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* private data
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*****************************************************************************/
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struct ftgmac100_descs {
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struct ftgmac100_rxdes rxdes[RX_QUEUE_ENTRIES];
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struct ftgmac100_txdes txdes[TX_QUEUE_ENTRIES];
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};
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struct ftgmac100 {
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/* Registers */
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struct resource *res;
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void __iomem *base;
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int irq;
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struct ftgmac100_descs *descs;
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dma_addr_t descs_dma_addr;
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/* Rx ring */
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struct page *rx_pages[RX_QUEUE_ENTRIES];
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unsigned int rx_pointer;
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u32 rxdes0_edorr_mask;
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/* Tx ring */
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unsigned int tx_clean_pointer;
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unsigned int tx_pointer;
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unsigned int tx_pending;
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u32 txdes0_edotr_mask;
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spinlock_t tx_lock;
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/* Component structures */
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struct net_device *netdev;
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struct device *dev;
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struct ncsi_dev *ndev;
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struct napi_struct napi;
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struct work_struct reset_task;
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struct mii_bus *mii_bus;
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int old_speed;
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int int_mask_all;
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bool use_ncsi;
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bool enabled;
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u32 rxdes0_edorr_mask;
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u32 txdes0_edotr_mask;
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/* Link management */
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int cur_speed;
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int cur_duplex;
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bool use_ncsi;
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/* Misc */
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bool need_mac_restart;
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};
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static int ftgmac100_alloc_rx_page(struct ftgmac100 *priv,
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struct ftgmac100_rxdes *rxdes, gfp_t gfp);
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/******************************************************************************
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* internal functions (hardware register access)
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*****************************************************************************/
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static void ftgmac100_set_rx_ring_base(struct ftgmac100 *priv, dma_addr_t addr)
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{
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iowrite32(addr, priv->base + FTGMAC100_OFFSET_RXR_BADR);
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@ -115,27 +114,64 @@ static void ftgmac100_txdma_normal_prio_start_polling(struct ftgmac100 *priv)
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iowrite32(1, priv->base + FTGMAC100_OFFSET_NPTXPD);
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}
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static int ftgmac100_reset_hw(struct ftgmac100 *priv)
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static int ftgmac100_reset_mac(struct ftgmac100 *priv, u32 maccr)
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{
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struct net_device *netdev = priv->netdev;
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int i;
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/* NOTE: reset clears all registers */
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iowrite32(FTGMAC100_MACCR_SW_RST, priv->base + FTGMAC100_OFFSET_MACCR);
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for (i = 0; i < 5; i++) {
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iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
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iowrite32(maccr | FTGMAC100_MACCR_SW_RST,
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priv->base + FTGMAC100_OFFSET_MACCR);
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for (i = 0; i < 50; i++) {
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unsigned int maccr;
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maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
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if (!(maccr & FTGMAC100_MACCR_SW_RST))
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return 0;
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udelay(1000);
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udelay(1);
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}
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netdev_err(netdev, "software reset failed\n");
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netdev_err(netdev, "Hardware reset failed\n");
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return -EIO;
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}
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static int ftgmac100_reset_and_config_mac(struct ftgmac100 *priv)
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{
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u32 maccr = 0;
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switch (priv->cur_speed) {
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case SPEED_10:
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case 0: /* no link */
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break;
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case SPEED_100:
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maccr |= FTGMAC100_MACCR_FAST_MODE;
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break;
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case SPEED_1000:
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maccr |= FTGMAC100_MACCR_GIGA_MODE;
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break;
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default:
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netdev_err(priv->netdev, "Unknown speed %d !\n",
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priv->cur_speed);
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break;
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}
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/* (Re)initialize the queue pointers */
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priv->rx_pointer = 0;
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priv->tx_clean_pointer = 0;
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priv->tx_pointer = 0;
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priv->tx_pending = 0;
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/* The doc says reset twice with 10us interval */
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if (ftgmac100_reset_mac(priv, maccr))
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return -EIO;
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usleep_range(10, 1000);
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return ftgmac100_reset_mac(priv, maccr);
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}
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static void ftgmac100_set_mac(struct ftgmac100 *priv, const unsigned char *mac)
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{
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unsigned int maddr = mac[0] << 8 | mac[1];
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@ -211,33 +247,28 @@ static void ftgmac100_init_hw(struct ftgmac100 *priv)
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ftgmac100_set_mac(priv, priv->netdev->dev_addr);
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}
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#define MACCR_ENABLE_ALL (FTGMAC100_MACCR_TXDMA_EN | \
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FTGMAC100_MACCR_RXDMA_EN | \
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FTGMAC100_MACCR_TXMAC_EN | \
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FTGMAC100_MACCR_RXMAC_EN | \
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FTGMAC100_MACCR_FULLDUP | \
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FTGMAC100_MACCR_CRC_APD | \
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FTGMAC100_MACCR_RX_RUNT | \
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FTGMAC100_MACCR_RX_BROADPKT)
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static void ftgmac100_start_hw(struct ftgmac100 *priv, int speed)
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static void ftgmac100_start_hw(struct ftgmac100 *priv)
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{
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int maccr = MACCR_ENABLE_ALL;
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u32 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
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switch (speed) {
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default:
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case 10:
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break;
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/* Keep the original GMAC and FAST bits */
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maccr &= (FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_GIGA_MODE);
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case 100:
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maccr |= FTGMAC100_MACCR_FAST_MODE;
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break;
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/* Add all the main enable bits */
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maccr |= FTGMAC100_MACCR_TXDMA_EN |
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FTGMAC100_MACCR_RXDMA_EN |
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FTGMAC100_MACCR_TXMAC_EN |
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FTGMAC100_MACCR_RXMAC_EN |
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FTGMAC100_MACCR_CRC_APD |
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FTGMAC100_MACCR_PHY_LINK_LEVEL |
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FTGMAC100_MACCR_RX_RUNT |
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FTGMAC100_MACCR_RX_BROADPKT;
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case 1000:
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maccr |= FTGMAC100_MACCR_GIGA_MODE;
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break;
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}
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/* Add other bits as needed */
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if (priv->cur_duplex == DUPLEX_FULL)
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maccr |= FTGMAC100_MACCR_FULLDUP;
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/* Hit the HW */
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iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
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}
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@ -246,9 +277,6 @@ static void ftgmac100_stop_hw(struct ftgmac100 *priv)
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iowrite32(0, priv->base + FTGMAC100_OFFSET_MACCR);
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}
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/******************************************************************************
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* internal functions (receive descriptor)
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*****************************************************************************/
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static bool ftgmac100_rxdes_first_segment(struct ftgmac100_rxdes *rxdes)
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{
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return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_FRS);
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@ -373,9 +401,6 @@ static struct page *ftgmac100_rxdes_get_page(struct ftgmac100 *priv,
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return *ftgmac100_rxdes_page_slot(priv, rxdes);
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}
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/******************************************************************************
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* internal functions (receive)
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*****************************************************************************/
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static int ftgmac100_next_rx_pointer(int pointer)
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{
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return (pointer + 1) & (RX_QUEUE_ENTRIES - 1);
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@ -560,9 +585,6 @@ static bool ftgmac100_rx_packet(struct ftgmac100 *priv, int *processed)
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return true;
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}
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/******************************************************************************
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* internal functions (transmit descriptor)
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*****************************************************************************/
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static void ftgmac100_txdes_reset(const struct ftgmac100 *priv,
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struct ftgmac100_txdes *txdes)
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{
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@ -656,9 +678,6 @@ static struct sk_buff *ftgmac100_txdes_get_skb(struct ftgmac100_txdes *txdes)
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return (struct sk_buff *)txdes->txdes2;
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}
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/******************************************************************************
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* internal functions (transmit)
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*****************************************************************************/
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static int ftgmac100_next_tx_pointer(int pointer)
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{
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return (pointer + 1) & (TX_QUEUE_ENTRIES - 1);
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@ -774,9 +793,6 @@ static int ftgmac100_xmit(struct ftgmac100 *priv, struct sk_buff *skb,
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return NETDEV_TX_OK;
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}
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/******************************************************************************
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* internal functions (buffer)
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*****************************************************************************/
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static int ftgmac100_alloc_rx_page(struct ftgmac100 *priv,
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struct ftgmac100_rxdes *rxdes, gfp_t gfp)
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{
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@ -809,6 +825,7 @@ static void ftgmac100_free_buffers(struct ftgmac100 *priv)
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{
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int i;
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/* Free all RX buffers */
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for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
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struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i];
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struct page *page = ftgmac100_rxdes_get_page(priv, rxdes);
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@ -821,6 +838,7 @@ static void ftgmac100_free_buffers(struct ftgmac100 *priv)
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__free_page(page);
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}
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/* Free all TX buffers */
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for (i = 0; i < TX_QUEUE_ENTRIES; i++) {
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struct ftgmac100_txdes *txdes = &priv->descs->txdes[i];
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struct sk_buff *skb = ftgmac100_txdes_get_skb(txdes);
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@ -832,70 +850,90 @@ static void ftgmac100_free_buffers(struct ftgmac100 *priv)
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dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE);
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kfree_skb(skb);
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}
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dma_free_coherent(priv->dev, sizeof(struct ftgmac100_descs),
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priv->descs, priv->descs_dma_addr);
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}
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static int ftgmac100_alloc_buffers(struct ftgmac100 *priv)
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static void ftgmac100_free_rings(struct ftgmac100 *priv)
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{
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int i;
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/* Free descriptors */
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if (priv->descs)
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dma_free_coherent(priv->dev, sizeof(struct ftgmac100_descs),
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priv->descs, priv->descs_dma_addr);
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}
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static int ftgmac100_alloc_rings(struct ftgmac100 *priv)
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{
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/* Allocate descriptors */
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priv->descs = dma_zalloc_coherent(priv->dev,
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sizeof(struct ftgmac100_descs),
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&priv->descs_dma_addr, GFP_KERNEL);
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if (!priv->descs)
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return -ENOMEM;
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/* initialize RX ring */
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ftgmac100_rxdes_set_end_of_ring(priv,
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&priv->descs->rxdes[RX_QUEUE_ENTRIES - 1]);
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return 0;
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}
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static void ftgmac100_init_rings(struct ftgmac100 *priv)
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{
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int i;
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/* Initialize RX ring */
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for (i = 0; i < RX_QUEUE_ENTRIES; i++)
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priv->descs->rxdes[i].rxdes0 = 0;
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ftgmac100_rxdes_set_end_of_ring(priv, &priv->descs->rxdes[i - 1]);
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/* Initialize TX ring */
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for (i = 0; i < TX_QUEUE_ENTRIES; i++)
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priv->descs->txdes[i].txdes0 = 0;
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ftgmac100_txdes_set_end_of_ring(priv, &priv->descs->txdes[i -1]);
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}
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static int ftgmac100_alloc_rx_buffers(struct ftgmac100 *priv)
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{
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int i;
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for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
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struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i];
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if (ftgmac100_alloc_rx_page(priv, rxdes, GFP_KERNEL))
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goto err;
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return -ENOMEM;
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}
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/* initialize TX ring */
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ftgmac100_txdes_set_end_of_ring(priv,
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&priv->descs->txdes[TX_QUEUE_ENTRIES - 1]);
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return 0;
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err:
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ftgmac100_free_buffers(priv);
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return -ENOMEM;
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}
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/******************************************************************************
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* internal functions (mdio)
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*****************************************************************************/
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static void ftgmac100_adjust_link(struct net_device *netdev)
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{
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struct ftgmac100 *priv = netdev_priv(netdev);
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struct phy_device *phydev = netdev->phydev;
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int ier;
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int new_speed;
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if (phydev->speed == priv->old_speed)
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/* We store "no link" as speed 0 */
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if (!phydev->link)
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new_speed = 0;
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else
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new_speed = phydev->speed;
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if (phydev->speed == priv->cur_speed &&
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phydev->duplex == priv->cur_duplex)
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return;
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priv->old_speed = phydev->speed;
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/* Print status if we have a link or we had one and just lost it,
|
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* don't print otherwise.
|
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*/
|
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if (new_speed || priv->cur_speed)
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phy_print_status(phydev);
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ier = ioread32(priv->base + FTGMAC100_OFFSET_IER);
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priv->cur_speed = new_speed;
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priv->cur_duplex = phydev->duplex;
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|
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/* disable all interrupts */
|
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/* Link is down, do nothing else */
|
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if (!new_speed)
|
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return;
|
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|
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/* Disable all interrupts */
|
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iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
|
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|
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netif_stop_queue(netdev);
|
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ftgmac100_stop_hw(priv);
|
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|
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netif_start_queue(netdev);
|
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ftgmac100_init_hw(priv);
|
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ftgmac100_start_hw(priv, phydev->speed);
|
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|
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/* re-enable interrupts */
|
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iowrite32(ier, priv->base + FTGMAC100_OFFSET_IER);
|
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/* Reset the adapter asynchronously */
|
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schedule_work(&priv->reset_task);
|
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}
|
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|
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static int ftgmac100_mii_probe(struct ftgmac100 *priv)
|
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@ -920,9 +958,6 @@ static int ftgmac100_mii_probe(struct ftgmac100 *priv)
|
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return 0;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* struct mii_bus functions
|
||||
*****************************************************************************/
|
||||
static int ftgmac100_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
|
||||
{
|
||||
struct net_device *netdev = bus->priv;
|
||||
@ -994,9 +1029,6 @@ static int ftgmac100_mdiobus_write(struct mii_bus *bus, int phy_addr,
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* struct ethtool_ops functions
|
||||
*****************************************************************************/
|
||||
static void ftgmac100_get_drvinfo(struct net_device *netdev,
|
||||
struct ethtool_drvinfo *info)
|
||||
{
|
||||
@ -1012,168 +1044,260 @@ static const struct ethtool_ops ftgmac100_ethtool_ops = {
|
||||
.set_link_ksettings = phy_ethtool_set_link_ksettings,
|
||||
};
|
||||
|
||||
/******************************************************************************
|
||||
* interrupt handler
|
||||
*****************************************************************************/
|
||||
static irqreturn_t ftgmac100_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
struct net_device *netdev = dev_id;
|
||||
struct ftgmac100 *priv = netdev_priv(netdev);
|
||||
unsigned int status, new_mask = FTGMAC100_INT_BAD;
|
||||
|
||||
/* When running in NCSI mode, the interface should be ready for
|
||||
* receiving or transmitting NCSI packets before it's opened.
|
||||
*/
|
||||
if (likely(priv->use_ncsi || netif_running(netdev))) {
|
||||
/* Disable interrupts for polling */
|
||||
iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
|
||||
napi_schedule(&priv->napi);
|
||||
/* Fetch and clear interrupt bits, process abnormal ones */
|
||||
status = ioread32(priv->base + FTGMAC100_OFFSET_ISR);
|
||||
iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR);
|
||||
if (unlikely(status & FTGMAC100_INT_BAD)) {
|
||||
|
||||
/* RX buffer unavailable */
|
||||
if (status & FTGMAC100_INT_NO_RXBUF)
|
||||
netdev->stats.rx_over_errors++;
|
||||
|
||||
/* received packet lost due to RX FIFO full */
|
||||
if (status & FTGMAC100_INT_RPKT_LOST)
|
||||
netdev->stats.rx_fifo_errors++;
|
||||
|
||||
/* sent packet lost due to excessive TX collision */
|
||||
if (status & FTGMAC100_INT_XPKT_LOST)
|
||||
netdev->stats.tx_fifo_errors++;
|
||||
|
||||
/* AHB error -> Reset the chip */
|
||||
if (status & FTGMAC100_INT_AHB_ERR) {
|
||||
if (net_ratelimit())
|
||||
netdev_warn(netdev,
|
||||
"AHB bus error ! Resetting chip.\n");
|
||||
iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
|
||||
schedule_work(&priv->reset_task);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
/* We may need to restart the MAC after such errors, delay
|
||||
* this until after we have freed some Rx buffers though
|
||||
*/
|
||||
priv->need_mac_restart = true;
|
||||
|
||||
/* Disable those errors until we restart */
|
||||
new_mask &= ~status;
|
||||
}
|
||||
|
||||
/* Only enable "bad" interrupts while NAPI is on */
|
||||
iowrite32(new_mask, priv->base + FTGMAC100_OFFSET_IER);
|
||||
|
||||
/* Schedule NAPI bh */
|
||||
napi_schedule_irqoff(&priv->napi);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* struct napi_struct functions
|
||||
*****************************************************************************/
|
||||
static int ftgmac100_poll(struct napi_struct *napi, int budget)
|
||||
{
|
||||
struct ftgmac100 *priv = container_of(napi, struct ftgmac100, napi);
|
||||
struct net_device *netdev = priv->netdev;
|
||||
unsigned int status;
|
||||
bool completed = true;
|
||||
bool more, completed = true;
|
||||
int rx = 0;
|
||||
|
||||
status = ioread32(priv->base + FTGMAC100_OFFSET_ISR);
|
||||
iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR);
|
||||
ftgmac100_tx_complete(priv);
|
||||
|
||||
if (status & (FTGMAC100_INT_RPKT_BUF | FTGMAC100_INT_NO_RXBUF)) {
|
||||
/*
|
||||
* FTGMAC100_INT_RPKT_BUF:
|
||||
* RX DMA has received packets into RX buffer successfully
|
||||
*
|
||||
* FTGMAC100_INT_NO_RXBUF:
|
||||
* RX buffer unavailable
|
||||
*/
|
||||
bool retry;
|
||||
do {
|
||||
more = ftgmac100_rx_packet(priv, &rx);
|
||||
} while (more && rx < budget);
|
||||
|
||||
do {
|
||||
retry = ftgmac100_rx_packet(priv, &rx);
|
||||
} while (retry && rx < budget);
|
||||
if (more && rx == budget)
|
||||
completed = false;
|
||||
|
||||
if (retry && rx == budget)
|
||||
completed = false;
|
||||
|
||||
/* The interrupt is telling us to kick the MAC back to life
|
||||
* after an RX overflow
|
||||
*/
|
||||
if (unlikely(priv->need_mac_restart)) {
|
||||
ftgmac100_start_hw(priv);
|
||||
|
||||
/* Re-enable "bad" interrupts */
|
||||
iowrite32(FTGMAC100_INT_BAD,
|
||||
priv->base + FTGMAC100_OFFSET_IER);
|
||||
}
|
||||
|
||||
if (status & (FTGMAC100_INT_XPKT_ETH | FTGMAC100_INT_XPKT_LOST)) {
|
||||
/*
|
||||
* FTGMAC100_INT_XPKT_ETH:
|
||||
* packet transmitted to ethernet successfully
|
||||
*
|
||||
* FTGMAC100_INT_XPKT_LOST:
|
||||
* packet transmitted to ethernet lost due to late
|
||||
* collision or excessive collision
|
||||
*/
|
||||
ftgmac100_tx_complete(priv);
|
||||
}
|
||||
|
||||
if (status & priv->int_mask_all & (FTGMAC100_INT_NO_RXBUF |
|
||||
FTGMAC100_INT_RPKT_LOST | FTGMAC100_INT_AHB_ERR)) {
|
||||
if (net_ratelimit())
|
||||
netdev_info(netdev, "[ISR] = 0x%x: %s%s%s\n", status,
|
||||
status & FTGMAC100_INT_NO_RXBUF ? "NO_RXBUF " : "",
|
||||
status & FTGMAC100_INT_RPKT_LOST ? "RPKT_LOST " : "",
|
||||
status & FTGMAC100_INT_AHB_ERR ? "AHB_ERR " : "");
|
||||
|
||||
if (status & FTGMAC100_INT_NO_RXBUF) {
|
||||
/* RX buffer unavailable */
|
||||
netdev->stats.rx_over_errors++;
|
||||
}
|
||||
|
||||
if (status & FTGMAC100_INT_RPKT_LOST) {
|
||||
/* received packet lost due to RX FIFO full */
|
||||
netdev->stats.rx_fifo_errors++;
|
||||
}
|
||||
}
|
||||
/* Keep NAPI going if we have still packets to reclaim */
|
||||
if (priv->tx_pending)
|
||||
return budget;
|
||||
|
||||
if (completed) {
|
||||
/* We are about to re-enable all interrupts. However
|
||||
* the HW has been latching RX/TX packet interrupts while
|
||||
* they were masked. So we clear them first, then we need
|
||||
* to re-check if there's something to process
|
||||
*/
|
||||
iowrite32(FTGMAC100_INT_RXTX,
|
||||
priv->base + FTGMAC100_OFFSET_ISR);
|
||||
if (ftgmac100_rxdes_packet_ready
|
||||
(ftgmac100_current_rxdes(priv)) || priv->tx_pending)
|
||||
return budget;
|
||||
|
||||
/* deschedule NAPI */
|
||||
napi_complete(napi);
|
||||
|
||||
/* enable all interrupts */
|
||||
iowrite32(priv->int_mask_all,
|
||||
iowrite32(FTGMAC100_INT_ALL,
|
||||
priv->base + FTGMAC100_OFFSET_IER);
|
||||
}
|
||||
|
||||
return rx;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* struct net_device_ops functions
|
||||
*****************************************************************************/
|
||||
static int ftgmac100_init_all(struct ftgmac100 *priv, bool ignore_alloc_err)
|
||||
{
|
||||
int err = 0;
|
||||
|
||||
/* Re-init descriptors (adjust queue sizes) */
|
||||
ftgmac100_init_rings(priv);
|
||||
|
||||
/* Realloc rx descriptors */
|
||||
err = ftgmac100_alloc_rx_buffers(priv);
|
||||
if (err && !ignore_alloc_err)
|
||||
return err;
|
||||
|
||||
/* Reinit and restart HW */
|
||||
ftgmac100_init_hw(priv);
|
||||
ftgmac100_start_hw(priv);
|
||||
|
||||
/* Re-enable the device */
|
||||
napi_enable(&priv->napi);
|
||||
netif_start_queue(priv->netdev);
|
||||
|
||||
/* Enable all interrupts */
|
||||
iowrite32(FTGMAC100_INT_ALL, priv->base + FTGMAC100_OFFSET_IER);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static void ftgmac100_reset_task(struct work_struct *work)
|
||||
{
|
||||
struct ftgmac100 *priv = container_of(work, struct ftgmac100,
|
||||
reset_task);
|
||||
struct net_device *netdev = priv->netdev;
|
||||
int err;
|
||||
|
||||
netdev_dbg(netdev, "Resetting NIC...\n");
|
||||
|
||||
/* Lock the world */
|
||||
rtnl_lock();
|
||||
if (netdev->phydev)
|
||||
mutex_lock(&netdev->phydev->lock);
|
||||
if (priv->mii_bus)
|
||||
mutex_lock(&priv->mii_bus->mdio_lock);
|
||||
|
||||
|
||||
/* Check if the interface is still up */
|
||||
if (!netif_running(netdev))
|
||||
goto bail;
|
||||
|
||||
/* Stop the network stack */
|
||||
netif_trans_update(netdev);
|
||||
napi_disable(&priv->napi);
|
||||
netif_tx_disable(netdev);
|
||||
|
||||
/* Stop and reset the MAC */
|
||||
ftgmac100_stop_hw(priv);
|
||||
err = ftgmac100_reset_and_config_mac(priv);
|
||||
if (err) {
|
||||
/* Not much we can do ... it might come back... */
|
||||
netdev_err(netdev, "attempting to continue...\n");
|
||||
}
|
||||
|
||||
/* Free all rx and tx buffers */
|
||||
ftgmac100_free_buffers(priv);
|
||||
|
||||
/* Setup everything again and restart chip */
|
||||
ftgmac100_init_all(priv, true);
|
||||
|
||||
netdev_dbg(netdev, "Reset done !\n");
|
||||
bail:
|
||||
if (priv->mii_bus)
|
||||
mutex_unlock(&priv->mii_bus->mdio_lock);
|
||||
if (netdev->phydev)
|
||||
mutex_unlock(&netdev->phydev->lock);
|
||||
rtnl_unlock();
|
||||
}
|
||||
|
||||
static int ftgmac100_open(struct net_device *netdev)
|
||||
{
|
||||
struct ftgmac100 *priv = netdev_priv(netdev);
|
||||
unsigned int status;
|
||||
int err;
|
||||
|
||||
err = ftgmac100_alloc_buffers(priv);
|
||||
/* Allocate ring buffers */
|
||||
err = ftgmac100_alloc_rings(priv);
|
||||
if (err) {
|
||||
netdev_err(netdev, "failed to allocate buffers\n");
|
||||
goto err_alloc;
|
||||
netdev_err(netdev, "Failed to allocate descriptors\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
err = request_irq(priv->irq, ftgmac100_interrupt, 0, netdev->name, netdev);
|
||||
if (err) {
|
||||
netdev_err(netdev, "failed to request irq %d\n", priv->irq);
|
||||
goto err_irq;
|
||||
/* When using NC-SI we force the speed to 100Mbit/s full duplex,
|
||||
*
|
||||
* Otherwise we leave it set to 0 (no link), the link
|
||||
* message from the PHY layer will handle setting it up to
|
||||
* something else if needed.
|
||||
*/
|
||||
if (priv->use_ncsi) {
|
||||
priv->cur_duplex = DUPLEX_FULL;
|
||||
priv->cur_speed = SPEED_100;
|
||||
} else {
|
||||
priv->cur_duplex = 0;
|
||||
priv->cur_speed = 0;
|
||||
}
|
||||
|
||||
priv->rx_pointer = 0;
|
||||
priv->tx_clean_pointer = 0;
|
||||
priv->tx_pointer = 0;
|
||||
priv->tx_pending = 0;
|
||||
|
||||
err = ftgmac100_reset_hw(priv);
|
||||
/* Reset the hardware */
|
||||
err = ftgmac100_reset_and_config_mac(priv);
|
||||
if (err)
|
||||
goto err_hw;
|
||||
|
||||
ftgmac100_init_hw(priv);
|
||||
ftgmac100_start_hw(priv, priv->use_ncsi ? 100 : 10);
|
||||
/* Initialize NAPI */
|
||||
netif_napi_add(netdev, &priv->napi, ftgmac100_poll, 64);
|
||||
|
||||
/* Clear stale interrupts */
|
||||
status = ioread32(priv->base + FTGMAC100_OFFSET_ISR);
|
||||
iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR);
|
||||
/* Grab our interrupt */
|
||||
err = request_irq(netdev->irq, ftgmac100_interrupt, 0, netdev->name, netdev);
|
||||
if (err) {
|
||||
netdev_err(netdev, "failed to request irq %d\n", netdev->irq);
|
||||
goto err_irq;
|
||||
}
|
||||
|
||||
if (netdev->phydev)
|
||||
/* Start things up */
|
||||
err = ftgmac100_init_all(priv, false);
|
||||
if (err) {
|
||||
netdev_err(netdev, "Failed to allocate packet buffers\n");
|
||||
goto err_alloc;
|
||||
}
|
||||
|
||||
if (netdev->phydev) {
|
||||
/* If we have a PHY, start polling */
|
||||
phy_start(netdev->phydev);
|
||||
else if (priv->use_ncsi)
|
||||
} else if (priv->use_ncsi) {
|
||||
/* If using NC-SI, set our carrier on and start the stack */
|
||||
netif_carrier_on(netdev);
|
||||
|
||||
napi_enable(&priv->napi);
|
||||
netif_start_queue(netdev);
|
||||
|
||||
/* enable all interrupts */
|
||||
iowrite32(priv->int_mask_all, priv->base + FTGMAC100_OFFSET_IER);
|
||||
|
||||
/* Start the NCSI device */
|
||||
if (priv->use_ncsi) {
|
||||
/* Start the NCSI device */
|
||||
err = ncsi_start_dev(priv->ndev);
|
||||
if (err)
|
||||
goto err_ncsi;
|
||||
}
|
||||
|
||||
priv->enabled = true;
|
||||
|
||||
return 0;
|
||||
|
||||
err_ncsi:
|
||||
err_ncsi:
|
||||
napi_disable(&priv->napi);
|
||||
netif_stop_queue(netdev);
|
||||
iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
|
||||
err_hw:
|
||||
free_irq(priv->irq, netdev);
|
||||
err_irq:
|
||||
err_alloc:
|
||||
ftgmac100_free_buffers(priv);
|
||||
err_alloc:
|
||||
free_irq(netdev->irq, netdev);
|
||||
err_irq:
|
||||
netif_napi_del(&priv->napi);
|
||||
err_hw:
|
||||
iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
|
||||
ftgmac100_free_rings(priv);
|
||||
return err;
|
||||
}
|
||||
|
||||
@ -1181,23 +1305,29 @@ static int ftgmac100_stop(struct net_device *netdev)
|
||||
{
|
||||
struct ftgmac100 *priv = netdev_priv(netdev);
|
||||
|
||||
if (!priv->enabled)
|
||||
return 0;
|
||||
/* Note about the reset task: We are called with the rtnl lock
|
||||
* held, so we are synchronized against the core of the reset
|
||||
* task. We must not try to synchronously cancel it otherwise
|
||||
* we can deadlock. But since it will test for netif_running()
|
||||
* which has already been cleared by the net core, we don't
|
||||
* anything special to do.
|
||||
*/
|
||||
|
||||
/* disable all interrupts */
|
||||
priv->enabled = false;
|
||||
iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
|
||||
|
||||
netif_stop_queue(netdev);
|
||||
napi_disable(&priv->napi);
|
||||
netif_napi_del(&priv->napi);
|
||||
if (netdev->phydev)
|
||||
phy_stop(netdev->phydev);
|
||||
else if (priv->use_ncsi)
|
||||
ncsi_stop_dev(priv->ndev);
|
||||
|
||||
ftgmac100_stop_hw(priv);
|
||||
free_irq(priv->irq, netdev);
|
||||
free_irq(netdev->irq, netdev);
|
||||
ftgmac100_free_buffers(priv);
|
||||
ftgmac100_free_rings(priv);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -1321,9 +1451,6 @@ static void ftgmac100_ncsi_handler(struct ncsi_dev *nd)
|
||||
nd->link_up ? "up" : "down");
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* struct platform_driver functions
|
||||
*****************************************************************************/
|
||||
static int ftgmac100_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct resource *res;
|
||||
@ -1361,12 +1488,10 @@ static int ftgmac100_probe(struct platform_device *pdev)
|
||||
priv = netdev_priv(netdev);
|
||||
priv->netdev = netdev;
|
||||
priv->dev = &pdev->dev;
|
||||
INIT_WORK(&priv->reset_task, ftgmac100_reset_task);
|
||||
|
||||
spin_lock_init(&priv->tx_lock);
|
||||
|
||||
/* initialize NAPI */
|
||||
netif_napi_add(netdev, &priv->napi, ftgmac100_poll, 64);
|
||||
|
||||
/* map io memory */
|
||||
priv->res = request_mem_region(res->start, resource_size(res),
|
||||
dev_name(&pdev->dev));
|
||||
@ -1383,18 +1508,11 @@ static int ftgmac100_probe(struct platform_device *pdev)
|
||||
goto err_ioremap;
|
||||
}
|
||||
|
||||
priv->irq = irq;
|
||||
netdev->irq = irq;
|
||||
|
||||
/* MAC address from chip or random one */
|
||||
ftgmac100_setup_mac(priv);
|
||||
|
||||
priv->int_mask_all = (FTGMAC100_INT_RPKT_LOST |
|
||||
FTGMAC100_INT_XPKT_ETH |
|
||||
FTGMAC100_INT_XPKT_LOST |
|
||||
FTGMAC100_INT_AHB_ERR |
|
||||
FTGMAC100_INT_RPKT_BUF |
|
||||
FTGMAC100_INT_NO_RXBUF);
|
||||
|
||||
if (of_machine_is_compatible("aspeed,ast2400") ||
|
||||
of_machine_is_compatible("aspeed,ast2500")) {
|
||||
priv->rxdes0_edorr_mask = BIT(30);
|
||||
@ -1440,7 +1558,7 @@ static int ftgmac100_probe(struct platform_device *pdev)
|
||||
goto err_register_netdev;
|
||||
}
|
||||
|
||||
netdev_info(netdev, "irq %d, mapped at %p\n", priv->irq, priv->base);
|
||||
netdev_info(netdev, "irq %d, mapped at %p\n", netdev->irq, priv->base);
|
||||
|
||||
return 0;
|
||||
|
||||
@ -1467,6 +1585,12 @@ static int ftgmac100_remove(struct platform_device *pdev)
|
||||
priv = netdev_priv(netdev);
|
||||
|
||||
unregister_netdev(netdev);
|
||||
|
||||
/* There's a small chance the reset task will have been re-queued,
|
||||
* during stop, make sure it's gone before we free the structure.
|
||||
*/
|
||||
cancel_work_sync(&priv->reset_task);
|
||||
|
||||
ftgmac100_destroy_mdio(netdev);
|
||||
|
||||
iounmap(priv->base);
|
||||
|
||||
@ -86,6 +86,20 @@
|
||||
#define FTGMAC100_INT_PHYSTS_CHG (1 << 9)
|
||||
#define FTGMAC100_INT_NO_HPTXBUF (1 << 10)
|
||||
|
||||
/* Interrupts we care about in NAPI mode */
|
||||
#define FTGMAC100_INT_BAD (FTGMAC100_INT_RPKT_LOST | \
|
||||
FTGMAC100_INT_XPKT_LOST | \
|
||||
FTGMAC100_INT_AHB_ERR | \
|
||||
FTGMAC100_INT_NO_RXBUF)
|
||||
|
||||
/* Normal RX/TX interrupts, enabled when NAPI off */
|
||||
#define FTGMAC100_INT_RXTX (FTGMAC100_INT_XPKT_ETH | \
|
||||
FTGMAC100_INT_RPKT_BUF)
|
||||
|
||||
/* All the interrupts we care about */
|
||||
#define FTGMAC100_INT_ALL (FTGMAC100_INT_RPKT_BUF | \
|
||||
FTGMAC100_INT_BAD)
|
||||
|
||||
/*
|
||||
* Interrupt timer control register
|
||||
*/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user