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drm/amdgpu: enable gfx eop interrupt per gfx pipe

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Navi10 has 2 gfx pipe and need to enable gfx eop interrupt
per pipe, instead of enable eop int for all gfx pipes at one
time.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Hawking Zhang
2019-03-11 22:04:44 +08:00
committed by Alex Deucher
parent 1919196165
commit 53b2fe415f
5 changed files with 10 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/drm/amd/amdgpu/amdgpu.h
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@@ -213,7 +213,8 @@ struct amdgpu_atif;
struct kfd_vm_fault_info; struct kfd_vm_fault_info;
enum amdgpu_cp_irq { enum amdgpu_cp_irq {
AMDGPU_CP_IRQ_GFX_EOP = 0, AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,
AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,

4
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
View File

@@ -3113,7 +3113,7 @@ static int gfx_v6_0_sw_init(void *handle)
ring->ring_obj = NULL; ring->ring_obj = NULL;
sprintf(ring->name, "gfx"); sprintf(ring->name, "gfx");
r = amdgpu_ring_init(adev, ring, 1024, r = amdgpu_ring_init(adev, ring, 1024,
&adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP); &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP);
if (r) if (r)
return r; return r;
} }
@@ -3348,7 +3348,7 @@ static int gfx_v6_0_set_eop_interrupt_state(struct amdgpu_device *adev,
enum amdgpu_interrupt_state state) enum amdgpu_interrupt_state state)
{ {
switch (type) { switch (type) {
case AMDGPU_CP_IRQ_GFX_EOP: case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
gfx_v6_0_set_gfx_eop_interrupt_state(adev, state); gfx_v6_0_set_gfx_eop_interrupt_state(adev, state);
break; break;
case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:

4
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
View File

@@ -4460,7 +4460,7 @@ static int gfx_v7_0_sw_init(void *handle)
ring->ring_obj = NULL; ring->ring_obj = NULL;
sprintf(ring->name, "gfx"); sprintf(ring->name, "gfx");
r = amdgpu_ring_init(adev, ring, 1024, r = amdgpu_ring_init(adev, ring, 1024,
&adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP); &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP);
if (r) if (r)
return r; return r;
} }
@@ -4797,7 +4797,7 @@ static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev,
enum amdgpu_interrupt_state state) enum amdgpu_interrupt_state state)
{ {
switch (type) { switch (type) {
case AMDGPU_CP_IRQ_GFX_EOP: case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
gfx_v7_0_set_gfx_eop_interrupt_state(adev, state); gfx_v7_0_set_gfx_eop_interrupt_state(adev, state);
break; break;
case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:

4
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
View File

@@ -2005,7 +2005,7 @@ static int gfx_v8_0_sw_init(void *handle)
} }
r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq,
AMDGPU_CP_IRQ_GFX_EOP); AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP);
if (r) if (r)
return r; return r;
} }
@@ -6533,7 +6533,7 @@ static int gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device *adev,
enum amdgpu_interrupt_state state) enum amdgpu_interrupt_state state)
{ {
switch (type) { switch (type) {
case AMDGPU_CP_IRQ_GFX_EOP: case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
gfx_v8_0_set_gfx_eop_interrupt_state(adev, state); gfx_v8_0_set_gfx_eop_interrupt_state(adev, state);
break; break;
case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:

4
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
View File

@@ -1721,7 +1721,7 @@ static int gfx_v9_0_sw_init(void *handle)
ring->use_doorbell = true; ring->use_doorbell = true;
ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
r = amdgpu_ring_init(adev, ring, 1024, r = amdgpu_ring_init(adev, ring, 1024,
&adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP); &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP);
if (r) if (r)
return r; return r;
} }
@@ -5025,7 +5025,7 @@ static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
enum amdgpu_interrupt_state state) enum amdgpu_interrupt_state state)
{ {
switch (type) { switch (type) {
case AMDGPU_CP_IRQ_GFX_EOP: case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
gfx_v9_0_set_gfx_eop_interrupt_state(adev, state); gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
break; break;
case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: