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Merge branch 'drm-rockchip-next-2017-02-05' of https://github.com/markyzq/kernel-drm-rockchip into drm-next

Browse Source 
rockchip CDN-DP support.

* 'drm-rockchip-next-2017-02-05' of https://github.com/markyzq/kernel-drm-rockchip:
  drm/rockchip: cdn-dp: don't configure hardware in mode_set
  drm/rockchip: cdn-dp: retry to check sink count
  drm/rockchip: cdn-dp: Move mutex_init to probe
  drm/rockchip: cdn-dp: do not use drm_helper_hpd_irq_event
  drm/rockchip: cdn-dp: Do not run worker while suspended
  drm/rockchip: cdn-dp: Load firmware if no monitor connected
  drm/rockchip: cdn-dp: add cdn DP support for rk3399
  drm/rockchip: return ERR_PTR instead of NULL
  drm/rockchip: vop: make vop register setting take effect
This commit is contained in:
Dave Airlie 2017-02-07 11:03:30 +10:00
commit 538f1dcdc5
10 changed files with 2872 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/gpu/drm/rockchip/Kconfig
View File

@ -21,6 +21,16 @@ config ROCKCHIP_ANALOGIX_DP
for the Analogix Core DP driver. If you want to enable DP
on RK3288 based SoC, you should selet this option.
config ROCKCHIP_CDN_DP
tristate "Rockchip cdn DP"
depends on DRM_ROCKCHIP
select SND_SOC_HDMI_CODEC if SND_SOC
help
This selects support for Rockchip SoC specific extensions
for the cdn DP driver. If you want to enable Dp on
RK3399 based SoC, you should select this
option.
config ROCKCHIP_DW_HDMI
tristate "Rockchip specific extensions for Synopsys DW HDMI"
depends on DRM_ROCKCHIP

2
drivers/gpu/drm/rockchip/Makefile
View File

@ -7,6 +7,8 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o \
rockchipdrm-$(CONFIG_DRM_FBDEV_EMULATION) += rockchip_drm_fbdev.o
obj-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
obj-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp.o
cdn-dp-objs := cdn-dp-core.o cdn-dp-reg.o
obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
obj-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi.o
obj-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi.o

1260
drivers/gpu/drm/rockchip/cdn-dp-core.c Normal file
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File diff suppressed because it is too large Load Diff

112
drivers/gpu/drm/rockchip/cdn-dp-core.h Normal file
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@ -0,0 +1,112 @@
/*
* Copyright (C) 2016 Chris Zhong <zyw@rock-chips.com>
* Copyright (C) 2016 ROCKCHIP, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _CDN_DP_CORE_H
#define _CDN_DP_CORE_H
#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_dp_helper.h>
#include <drm/drm_panel.h>
#include "rockchip_drm_drv.h"
#define MAX_PHY 2
enum audio_format {
AFMT_I2S = 0,
AFMT_SPDIF = 1,
AFMT_UNUSED,
};
struct audio_info {
enum audio_format format;
int sample_rate;
int channels;
int sample_width;
};
enum vic_pxl_encoding_format {
PXL_RGB = 0x1,
YCBCR_4_4_4 = 0x2,
YCBCR_4_2_2 = 0x4,
YCBCR_4_2_0 = 0x8,
Y_ONLY = 0x10,
};
struct video_info {
bool h_sync_polarity;
bool v_sync_polarity;
bool interlaced;
int color_depth;
enum vic_pxl_encoding_format color_fmt;
};
struct cdn_firmware_header {
u32 size_bytes; /* size of the entire header+image(s) in bytes */
u32 header_size; /* size of just the header in bytes */
u32 iram_size; /* size of iram */
u32 dram_size; /* size of dram */
};
struct cdn_dp_port {
struct cdn_dp_device *dp;
struct notifier_block event_nb;
struct extcon_dev *extcon;
struct phy *phy;
u8 lanes;
bool phy_enabled;
u8 id;
};
struct cdn_dp_device {
struct device *dev;
struct drm_device *drm_dev;
struct drm_connector connector;
struct drm_encoder encoder;
struct drm_display_mode mode;
struct platform_device *audio_pdev;
struct work_struct event_work;
struct edid *edid;
struct mutex lock;
bool connected;
bool active;
bool suspended;
const struct firmware *fw; /* cdn dp firmware */
unsigned int fw_version; /* cdn fw version */
bool fw_loaded;
void __iomem *regs;
struct regmap *grf;
struct clk *core_clk;
struct clk *pclk;
struct clk *spdif_clk;
struct clk *grf_clk;
struct reset_control *spdif_rst;
struct reset_control *dptx_rst;
struct reset_control *apb_rst;
struct reset_control *core_rst;
struct audio_info audio_info;
struct video_info video_info;
struct drm_dp_link link;
struct cdn_dp_port *port[MAX_PHY];
u8 ports;
u8 lanes;
int active_port;
u8 dpcd[DP_RECEIVER_CAP_SIZE];
bool sink_has_audio;
};
#endif /* _CDN_DP_CORE_H */

979
drivers/gpu/drm/rockchip/cdn-dp-reg.c Normal file
View File

@ -0,0 +1,979 @@
/*
* Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
* Author: Chris Zhong <zyw@rock-chips.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/reset.h>
#include "cdn-dp-core.h"
#include "cdn-dp-reg.h"
#define CDN_DP_SPDIF_CLK 200000000
#define FW_ALIVE_TIMEOUT_US 1000000
#define MAILBOX_RETRY_US 1000
#define MAILBOX_TIMEOUT_US 5000000
#define LINK_TRAINING_RETRY_MS 20
#define LINK_TRAINING_TIMEOUT_MS 500
void cdn_dp_set_fw_clk(struct cdn_dp_device *dp, u32 clk)
{
writel(clk / 1000000, dp->regs + SW_CLK_H);
}
void cdn_dp_clock_reset(struct cdn_dp_device *dp)
{
u32 val;
val = DPTX_FRMR_DATA_CLK_RSTN_EN |
DPTX_FRMR_DATA_CLK_EN |
DPTX_PHY_DATA_RSTN_EN |
DPTX_PHY_DATA_CLK_EN |
DPTX_PHY_CHAR_RSTN_EN |
DPTX_PHY_CHAR_CLK_EN |
SOURCE_AUX_SYS_CLK_RSTN_EN |
SOURCE_AUX_SYS_CLK_EN |
DPTX_SYS_CLK_RSTN_EN |
DPTX_SYS_CLK_EN |
CFG_DPTX_VIF_CLK_RSTN_EN |
CFG_DPTX_VIF_CLK_EN;
writel(val, dp->regs + SOURCE_DPTX_CAR);
val = SOURCE_PHY_RSTN_EN | SOURCE_PHY_CLK_EN;
writel(val, dp->regs + SOURCE_PHY_CAR);
val = SOURCE_PKT_SYS_RSTN_EN |
SOURCE_PKT_SYS_CLK_EN |
SOURCE_PKT_DATA_RSTN_EN |
SOURCE_PKT_DATA_CLK_EN;
writel(val, dp->regs + SOURCE_PKT_CAR);
val = SPDIF_CDR_CLK_RSTN_EN |
SPDIF_CDR_CLK_EN |
SOURCE_AIF_SYS_RSTN_EN |
SOURCE_AIF_SYS_CLK_EN |
SOURCE_AIF_CLK_RSTN_EN |
SOURCE_AIF_CLK_EN;
writel(val, dp->regs + SOURCE_AIF_CAR);
val = SOURCE_CIPHER_SYSTEM_CLK_RSTN_EN |
SOURCE_CIPHER_SYS_CLK_EN |
SOURCE_CIPHER_CHAR_CLK_RSTN_EN |
SOURCE_CIPHER_CHAR_CLK_EN;
writel(val, dp->regs + SOURCE_CIPHER_CAR);
val = SOURCE_CRYPTO_SYS_CLK_RSTN_EN |
SOURCE_CRYPTO_SYS_CLK_EN;
writel(val, dp->regs + SOURCE_CRYPTO_CAR);
/* enable Mailbox and PIF interrupt */
writel(0, dp->regs + APB_INT_MASK);
}
static int cdn_dp_mailbox_read(struct cdn_dp_device *dp)
{
int val, ret;
ret = readx_poll_timeout(readl, dp->regs + MAILBOX_EMPTY_ADDR,
val, !val, MAILBOX_RETRY_US,
MAILBOX_TIMEOUT_US);
if (ret < 0)
return ret;
return readl(dp->regs + MAILBOX0_RD_DATA) & 0xff;
}
static int cdp_dp_mailbox_write(struct cdn_dp_device *dp, u8 val)
{
int ret, full;
ret = readx_poll_timeout(readl, dp->regs + MAILBOX_FULL_ADDR,
full, !full, MAILBOX_RETRY_US,
MAILBOX_TIMEOUT_US);
if (ret < 0)
return ret;
writel(val, dp->regs + MAILBOX0_WR_DATA);
return 0;
}
static int cdn_dp_mailbox_validate_receive(struct cdn_dp_device *dp,
u8 module_id, u8 opcode,
u8 req_size)
{
u32 mbox_size, i;
u8 header[4];
int ret;
/* read the header of the message */
for (i = 0; i < 4; i++) {
ret = cdn_dp_mailbox_read(dp);
if (ret < 0)
return ret;
header[i] = ret;
}
mbox_size = (header[2] << 8) | header[3];
if (opcode != header[0] || module_id != header[1] ||
req_size != mbox_size) {
/*
* If the message in mailbox is not what we want, we need to
* clear the mailbox by reading its contents.
*/
for (i = 0; i < mbox_size; i++)
if (cdn_dp_mailbox_read(dp) < 0)
break;
return -EINVAL;
}
return 0;
}
static int cdn_dp_mailbox_read_receive(struct cdn_dp_device *dp,
u8 *buff, u8 buff_size)
{
u32 i;
int ret;
for (i = 0; i < buff_size; i++) {
ret = cdn_dp_mailbox_read(dp);
if (ret < 0)
return ret;
buff[i] = ret;
}
return 0;
}
static int cdn_dp_mailbox_send(struct cdn_dp_device *dp, u8 module_id,
u8 opcode, u16 size, u8 *message)
{
u8 header[4];
int ret, i;
header[0] = opcode;
header[1] = module_id;
header[2] = (size >> 8) & 0xff;
header[3] = size & 0xff;
for (i = 0; i < 4; i++) {
ret = cdp_dp_mailbox_write(dp, header[i]);
if (ret)
return ret;
}
for (i = 0; i < size; i++) {
ret = cdp_dp_mailbox_write(dp, message[i]);
if (ret)
return ret;
}
return 0;
}
static int cdn_dp_reg_write(struct cdn_dp_device *dp, u16 addr, u32 val)
{
u8 msg[6];
msg[0] = (addr >> 8) & 0xff;
msg[1] = addr & 0xff;
msg[2] = (val >> 24) & 0xff;
msg[3] = (val >> 16) & 0xff;
msg[4] = (val >> 8) & 0xff;
msg[5] = val & 0xff;
return cdn_dp_mailbox_send(dp, MB_MODULE_ID_DP_TX, DPTX_WRITE_REGISTER,
sizeof(msg), msg);
}
static int cdn_dp_reg_write_bit(struct cdn_dp_device *dp, u16 addr,
u8 start_bit, u8 bits_no, u32 val)
{
u8 field[8];
field[0] = (addr >> 8) & 0xff;
field[1] = addr & 0xff;
field[2] = start_bit;
field[3] = bits_no;
field[4] = (val >> 24) & 0xff;
field[5] = (val >> 16) & 0xff;
field[6] = (val >> 8) & 0xff;
field[7] = val & 0xff;
return cdn_dp_mailbox_send(dp, MB_MODULE_ID_DP_TX, DPTX_WRITE_FIELD,
sizeof(field), field);
}
int cdn_dp_dpcd_read(struct cdn_dp_device *dp, u32 addr, u8 *data, u16 len)
{
u8 msg[5], reg[5];
int ret;
msg[0] = (len >> 8) & 0xff;
msg[1] = len & 0xff;
msg[2] = (addr >> 16) & 0xff;
msg[3] = (addr >> 8) & 0xff;
msg[4] = addr & 0xff;
ret = cdn_dp_mailbox_send(dp, MB_MODULE_ID_DP_TX, DPTX_READ_DPCD,
sizeof(msg), msg);
if (ret)
goto err_dpcd_read;
ret = cdn_dp_mailbox_validate_receive(dp, MB_MODULE_ID_DP_TX,
DPTX_READ_DPCD,
sizeof(reg) + len);
if (ret)
goto err_dpcd_read;
ret = cdn_dp_mailbox_read_receive(dp, reg, sizeof(reg));
if (ret)
goto err_dpcd_read;
ret = cdn_dp_mailbox_read_receive(dp, data, len);
err_dpcd_read:
return ret;
}
int cdn_dp_dpcd_write(struct cdn_dp_device *dp, u32 addr, u8 value)
{
u8 msg[6], reg[5];
int ret;
msg[0] = 0;
msg[1] = 1;
msg[2] = (addr >> 16) & 0xff;
msg[3] = (addr >> 8) & 0xff;
msg[4] = addr & 0xff;
msg[5] = value;
ret = cdn_dp_mailbox_send(dp, MB_MODULE_ID_DP_TX, DPTX_WRITE_DPCD,
sizeof(msg), msg);
if (ret)
goto err_dpcd_write;
ret = cdn_dp_mailbox_validate_receive(dp, MB_MODULE_ID_DP_TX,
DPTX_WRITE_DPCD, sizeof(reg));
if (ret)
goto err_dpcd_write;
ret = cdn_dp_mailbox_read_receive(dp, reg, sizeof(reg));
if (ret)
goto err_dpcd_write;
if (addr != (reg[2] << 16 | reg[3] << 8 | reg[4]))
ret = -EINVAL;
err_dpcd_write:
if (ret)
DRM_DEV_ERROR(dp->dev, "dpcd write failed: %d\n", ret);
return ret;
}
int cdn_dp_load_firmware(struct cdn_dp_device *dp, const u32 *i_mem,
u32 i_size, const u32 *d_mem, u32 d_size)
{
u32 reg;
int i, ret;
/* reset ucpu before load firmware*/
writel(APB_IRAM_PATH | APB_DRAM_PATH | APB_XT_RESET,
dp->regs + APB_CTRL);
for (i = 0; i < i_size; i += 4)
writel(*i_mem++, dp->regs + ADDR_IMEM + i);
for (i = 0; i < d_size; i += 4)
writel(*d_mem++, dp->regs + ADDR_DMEM + i);
/* un-reset ucpu */
writel(0, dp->regs + APB_CTRL);
/* check the keep alive register to make sure fw working */
ret = readx_poll_timeout(readl, dp->regs + KEEP_ALIVE,
reg, reg, 2000, FW_ALIVE_TIMEOUT_US);
if (ret < 0) {
DRM_DEV_ERROR(dp->dev, "failed to loaded the FW reg = %x\n",
reg);
return -EINVAL;
}
reg = readl(dp->regs + VER_L) & 0xff;
dp->fw_version = reg;
reg = readl(dp->regs + VER_H) & 0xff;
dp->fw_version |= reg << 8;
reg = readl(dp->regs + VER_LIB_L_ADDR) & 0xff;
dp->fw_version |= reg << 16;
reg = readl(dp->regs + VER_LIB_H_ADDR) & 0xff;
dp->fw_version |= reg << 24;
dev_dbg(dp->dev, "firmware version: %x\n", dp->fw_version);
return 0;
}
int cdn_dp_set_firmware_active(struct cdn_dp_device *dp, bool enable)
{
u8 msg[5];
int ret, i;
msg[0] = GENERAL_MAIN_CONTROL;
msg[1] = MB_MODULE_ID_GENERAL;
msg[2] = 0;
msg[3] = 1;
msg[4] = enable ? FW_ACTIVE : FW_STANDBY;
for (i = 0; i < sizeof(msg); i++) {
ret = cdp_dp_mailbox_write(dp, msg[i]);
if (ret)
goto err_set_firmware_active;
}
/* read the firmware state */
for (i = 0; i < sizeof(msg); i++) {
ret = cdn_dp_mailbox_read(dp);
if (ret < 0)
goto err_set_firmware_active;
msg[i] = ret;
}
ret = 0;
err_set_firmware_active:
if (ret < 0)
DRM_DEV_ERROR(dp->dev, "set firmware active failed\n");
return ret;
}
int cdn_dp_set_host_cap(struct cdn_dp_device *dp, u8 lanes, bool flip)
{
u8 msg[8];
int ret;
msg[0] = CDN_DP_MAX_LINK_RATE;
msg[1] = lanes | SCRAMBLER_EN;
msg[2] = VOLTAGE_LEVEL_2;
msg[3] = PRE_EMPHASIS_LEVEL_3;
msg[4] = PTS1 | PTS2 | PTS3 | PTS4;
msg[5] = FAST_LT_NOT_SUPPORT;
msg[6] = flip ? LANE_MAPPING_FLIPPED : LANE_MAPPING_NORMAL;
msg[7] = ENHANCED;
ret = cdn_dp_mailbox_send(dp, MB_MODULE_ID_DP_TX,
DPTX_SET_HOST_CAPABILITIES,
sizeof(msg), msg);
if (ret)
goto err_set_host_cap;
ret = cdn_dp_reg_write(dp, DP_AUX_SWAP_INVERSION_CONTROL,
AUX_HOST_INVERT);
err_set_host_cap:
if (ret)
DRM_DEV_ERROR(dp->dev, "set host cap failed: %d\n", ret);
return ret;
}
int cdn_dp_event_config(struct cdn_dp_device *dp)
{
u8 msg[5];
int ret;
memset(msg, 0, sizeof(msg));
msg[0] = DPTX_EVENT_ENABLE_HPD | DPTX_EVENT_ENABLE_TRAINING;
ret = cdn_dp_mailbox_send(dp, MB_MODULE_ID_DP_TX, DPTX_ENABLE_EVENT,
sizeof(msg), msg);
if (ret)
DRM_DEV_ERROR(dp->dev, "set event config failed: %d\n", ret);
return ret;
}
u32 cdn_dp_get_event(struct cdn_dp_device *dp)
{
return readl(dp->regs + SW_EVENTS0);
}
int cdn_dp_get_hpd_status(struct cdn_dp_device *dp)
{
u8 status;
int ret;
ret = cdn_dp_mailbox_send(dp, MB_MODULE_ID_DP_TX, DPTX_HPD_STATE,
0, NULL);
if (ret)
goto err_get_hpd;
ret = cdn_dp_mailbox_validate_receive(dp, MB_MODULE_ID_DP_TX,
DPTX_HPD_STATE, sizeof(status));
if (ret)
goto err_get_hpd;
ret = cdn_dp_mailbox_read_receive(dp, &status, sizeof(status));
if (ret)
goto err_get_hpd;
return status;
err_get_hpd:
DRM_DEV_ERROR(dp->dev, "get hpd status failed: %d\n", ret);
return ret;
}
int cdn_dp_get_edid_block(void *data, u8 *edid,
unsigned int block, size_t length)
{
struct cdn_dp_device *dp = data;
u8 msg[2], reg[2], i;
int ret;
for (i = 0; i < 4; i++) {
msg[0] = block / 2;
msg[1] = block % 2;
ret = cdn_dp_mailbox_send(dp, MB_MODULE_ID_DP_TX, DPTX_GET_EDID,
sizeof(msg), msg);
if (ret)
continue;
ret = cdn_dp_mailbox_validate_receive(dp, MB_MODULE_ID_DP_TX,
DPTX_GET_EDID,
sizeof(reg) + length);
if (ret)
continue;
ret = cdn_dp_mailbox_read_receive(dp, reg, sizeof(reg));
if (ret)
continue;
ret = cdn_dp_mailbox_read_receive(dp, edid, length);
if (ret)
continue;
if (reg[0] == length && reg[1] == block / 2)
break;
}
if (ret)
DRM_DEV_ERROR(dp->dev, "get block[%d] edid failed: %d\n", block,
ret);
return ret;
}
static int cdn_dp_training_start(struct cdn_dp_device *dp)
{
unsigned long timeout;
u8 msg, event[2];
int ret;
msg = LINK_TRAINING_RUN;
/* start training */
ret = cdn_dp_mailbox_send(dp, MB_MODULE_ID_DP_TX, DPTX_TRAINING_CONTROL,
sizeof(msg), &msg);
if (ret)
goto err_training_start;
timeout = jiffies + msecs_to_jiffies(LINK_TRAINING_TIMEOUT_MS);
while (time_before(jiffies, timeout)) {
msleep(LINK_TRAINING_RETRY_MS);
ret = cdn_dp_mailbox_send(dp, MB_MODULE_ID_DP_TX,
DPTX_READ_EVENT, 0, NULL);
if (ret)
goto err_training_start;
ret = cdn_dp_mailbox_validate_receive(dp, MB_MODULE_ID_DP_TX,
DPTX_READ_EVENT,
sizeof(event));
if (ret)
goto err_training_start;
ret = cdn_dp_mailbox_read_receive(dp, event, sizeof(event));
if (ret)
goto err_training_start;
if (event[1] & EQ_PHASE_FINISHED)
return 0;
}
ret = -ETIMEDOUT;
err_training_start:
DRM_DEV_ERROR(dp->dev, "training failed: %d\n", ret);
return ret;
}
static int cdn_dp_get_training_status(struct cdn_dp_device *dp)
{
u8 status[10];
int ret;
ret = cdn_dp_mailbox_send(dp, MB_MODULE_ID_DP_TX, DPTX_READ_LINK_STAT,
0, NULL);
if (ret)
goto err_get_training_status;
ret = cdn_dp_mailbox_validate_receive(dp, MB_MODULE_ID_DP_TX,
DPTX_READ_LINK_STAT,
sizeof(status));
if (ret)
goto err_get_training_status;
ret = cdn_dp_mailbox_read_receive(dp, status, sizeof(status));
if (ret)
goto err_get_training_status;
dp->link.rate = status[0];
dp->link.num_lanes = status[1];
err_get_training_status:
if (ret)
DRM_DEV_ERROR(dp->dev, "get training status failed: %d\n", ret);
return ret;
}
int cdn_dp_train_link(struct cdn_dp_device *dp)
{
int ret;
ret = cdn_dp_training_start(dp);
if (ret) {
DRM_DEV_ERROR(dp->dev, "Failed to start training %d\n", ret);
return ret;
}
ret = cdn_dp_get_training_status(dp);
if (ret) {
DRM_DEV_ERROR(dp->dev, "Failed to get training stat %d\n", ret);
return ret;
}
DRM_DEV_DEBUG_KMS(dp->dev, "rate:0x%x, lanes:%d\n", dp->link.rate,
dp->link.num_lanes);
return ret;
}
int cdn_dp_set_video_status(struct cdn_dp_device *dp, int active)
{
u8 msg;
int ret;
msg = !!active;
ret = cdn_dp_mailbox_send(dp, MB_MODULE_ID_DP_TX, DPTX_SET_VIDEO,
sizeof(msg), &msg);
if (ret)
DRM_DEV_ERROR(dp->dev, "set video status failed: %d\n", ret);
return ret;
}
static int cdn_dp_get_msa_misc(struct video_info *video,
struct drm_display_mode *mode)
{
u32 msa_misc;
u8 val[2];
switch (video->color_fmt) {
case PXL_RGB:
case Y_ONLY:
val[0] = 0;
break;
/* set YUV default color space conversion to BT601 */
case YCBCR_4_4_4:
val[0] = 6 + BT_601 * 8;
break;
case YCBCR_4_2_2:
val[0] = 5 + BT_601 * 8;
break;
case YCBCR_4_2_0:
val[0] = 5;
break;
};
switch (video->color_depth) {
case 6:
val[1] = 0;
break;
case 8:
val[1] = 1;
break;
case 10:
val[1] = 2;
break;
case 12:
val[1] = 3;
break;
case 16:
val[1] = 4;
break;
};
msa_misc = 2 * val[0] + 32 * val[1] +
((video->color_fmt == Y_ONLY) ? (1 << 14) : 0);
return msa_misc;
}
int cdn_dp_config_video(struct cdn_dp_device *dp)
{
struct video_info *video = &dp->video_info;
struct drm_display_mode *mode = &dp->mode;
u64 symbol;
u32 val, link_rate, rem;
u8 bit_per_pix, tu_size_reg = TU_SIZE;
int ret;
bit_per_pix = (video->color_fmt == YCBCR_4_2_2) ?
(video->color_depth * 2) : (video->color_depth * 3);
link_rate = drm_dp_bw_code_to_link_rate(dp->link.rate) / 1000;
ret = cdn_dp_reg_write(dp, BND_HSYNC2VSYNC, VIF_BYPASS_INTERLACE);
if (ret)
goto err_config_video;
ret = cdn_dp_reg_write(dp, HSYNC2VSYNC_POL_CTRL, 0);
if (ret)
goto err_config_video;
/*
* get a best tu_size and valid symbol:
* 1. chose Lclk freq(162Mhz, 270Mhz, 540Mhz), set TU to 32
* 2. calculate VS(valid symbol) = TU * Pclk * Bpp / (Lclk * Lanes)
* 3. if VS > *.85 or VS < *.1 or VS < 2 or TU < VS + 4, then set
* TU += 2 and repeat 2nd step.
*/
do {
tu_size_reg += 2;
symbol = tu_size_reg * mode->clock * bit_per_pix;
do_div(symbol, dp->link.num_lanes * link_rate * 8);
rem = do_div(symbol, 1000);
if (tu_size_reg > 64) {
ret = -EINVAL;
goto err_config_video;
}
} while ((symbol <= 1) || (tu_size_reg - symbol < 4) ||
(rem > 850) || (rem < 100));
val = symbol + (tu_size_reg << 8);
val |= TU_CNT_RST_EN;
ret = cdn_dp_reg_write(dp, DP_FRAMER_TU, val);
if (ret)
goto err_config_video;
/* set the FIFO Buffer size */
val = div_u64(mode->clock * (symbol + 1), 1000) + link_rate;
val /= (dp->link.num_lanes * link_rate);
val = div_u64(8 * (symbol + 1), bit_per_pix) - val;
val += 2;
ret = cdn_dp_reg_write(dp, DP_VC_TABLE(15), val);
switch (video->color_depth) {
case 6:
val = BCS_6;
break;
case 8:
val = BCS_8;
break;
case 10:
val = BCS_10;
break;
case 12:
val = BCS_12;
break;
case 16:
val = BCS_16;
break;
};
val += video->color_fmt << 8;
ret = cdn_dp_reg_write(dp, DP_FRAMER_PXL_REPR, val);
if (ret)
goto err_config_video;
val = video->h_sync_polarity ? DP_FRAMER_SP_HSP : 0;
val |= video->v_sync_polarity ? DP_FRAMER_SP_VSP : 0;
ret = cdn_dp_reg_write(dp, DP_FRAMER_SP, val);
if (ret)
goto err_config_video;
val = (mode->hsync_start - mode->hdisplay) << 16;
val |= mode->htotal - mode->hsync_end;
ret = cdn_dp_reg_write(dp, DP_FRONT_BACK_PORCH, val);
if (ret)
goto err_config_video;
val = mode->hdisplay * bit_per_pix / 8;
ret = cdn_dp_reg_write(dp, DP_BYTE_COUNT, val);
if (ret)
goto err_config_video;
val = mode->htotal | ((mode->htotal - mode->hsync_start) << 16);
ret = cdn_dp_reg_write(dp, MSA_HORIZONTAL_0, val);
if (ret)
goto err_config_video;
val = mode->hsync_end - mode->hsync_start;
val |= (mode->hdisplay << 16) | (video->h_sync_polarity << 15);
ret = cdn_dp_reg_write(dp, MSA_HORIZONTAL_1, val);
if (ret)
goto err_config_video;
val = mode->vtotal;
val |= (mode->vtotal - mode->vsync_start) << 16;
ret = cdn_dp_reg_write(dp, MSA_VERTICAL_0, val);
if (ret)
goto err_config_video;
val = mode->vsync_end - mode->vsync_start;
val |= (mode->vdisplay << 16) | (video->v_sync_polarity << 15);
ret = cdn_dp_reg_write(dp, MSA_VERTICAL_1, val);
if (ret)
goto err_config_video;
val = cdn_dp_get_msa_misc(video, mode);
ret = cdn_dp_reg_write(dp, MSA_MISC, val);
if (ret)
goto err_config_video;
ret = cdn_dp_reg_write(dp, STREAM_CONFIG, 1);
if (ret)
goto err_config_video;
val = mode->hsync_end - mode->hsync_start;
val |= mode->hdisplay << 16;
ret = cdn_dp_reg_write(dp, DP_HORIZONTAL, val);
if (ret)
goto err_config_video;
val = mode->vdisplay;
val |= (mode->vtotal - mode->vsync_start) << 16;
ret = cdn_dp_reg_write(dp, DP_VERTICAL_0, val);
if (ret)
goto err_config_video;
val = mode->vtotal;
ret = cdn_dp_reg_write(dp, DP_VERTICAL_1, val);
if (ret)
goto err_config_video;
ret = cdn_dp_reg_write_bit(dp, DP_VB_ID, 2, 1, 0);
err_config_video:
if (ret)
DRM_DEV_ERROR(dp->dev, "config video failed: %d\n", ret);
return ret;
}
int cdn_dp_audio_stop(struct cdn_dp_device *dp, struct audio_info *audio)
{
u32 val;
int ret;
ret = cdn_dp_reg_write(dp, AUDIO_PACK_CONTROL, 0);
if (ret) {
DRM_DEV_ERROR(dp->dev, "audio stop failed: %d\n", ret);
return ret;
}
val = SPDIF_AVG_SEL | SPDIF_JITTER_BYPASS;
val |= SPDIF_FIFO_MID_RANGE(0xe0);
val |= SPDIF_JITTER_THRSH(0xe0);
val |= SPDIF_JITTER_AVG_WIN(7);
writel(val, dp->regs + SPDIF_CTRL_ADDR);
/* clearn the audio config and reset */
writel(0, dp->regs + AUDIO_SRC_CNTL);
writel(0, dp->regs + AUDIO_SRC_CNFG);
writel(AUDIO_SW_RST, dp->regs + AUDIO_SRC_CNTL);
writel(0, dp->regs + AUDIO_SRC_CNTL);
/* reset smpl2pckt component */
writel(0, dp->regs + SMPL2PKT_CNTL);
writel(AUDIO_SW_RST, dp->regs + SMPL2PKT_CNTL);
writel(0, dp->regs + SMPL2PKT_CNTL);
/* reset FIFO */
writel(AUDIO_SW_RST, dp->regs + FIFO_CNTL);
writel(0, dp->regs + FIFO_CNTL);
if (audio->format == AFMT_SPDIF)
clk_disable_unprepare(dp->spdif_clk);
return 0;
}
int cdn_dp_audio_mute(struct cdn_dp_device *dp, bool enable)
{
int ret;
ret = cdn_dp_reg_write_bit(dp, DP_VB_ID, 4, 1, enable);
if (ret)
DRM_DEV_ERROR(dp->dev, "audio mute failed: %d\n", ret);
return ret;
}
static void cdn_dp_audio_config_i2s(struct cdn_dp_device *dp,
struct audio_info *audio)
{
int sub_pckt_num = 1, i2s_port_en_val = 0xf, i;
u32 val;
if (audio->channels == 2) {
if (dp->link.num_lanes == 1)
sub_pckt_num = 2;
else
sub_pckt_num = 4;
i2s_port_en_val = 1;
} else if (audio->channels == 4) {
i2s_port_en_val = 3;
}
writel(0x0, dp->regs + SPDIF_CTRL_ADDR);
writel(SYNC_WR_TO_CH_ZERO, dp->regs + FIFO_CNTL);
val = MAX_NUM_CH(audio->channels);
val |= NUM_OF_I2S_PORTS(audio->channels);
val |= AUDIO_TYPE_LPCM;
val |= CFG_SUB_PCKT_NUM(sub_pckt_num);
writel(val, dp->regs + SMPL2PKT_CNFG);
if (audio->sample_width == 16)
val = 0;
else if (audio->sample_width == 24)
val = 1 << 9;
else
val = 2 << 9;
val |= AUDIO_CH_NUM(audio->channels);
val |= I2S_DEC_PORT_EN(i2s_port_en_val);
val |= TRANS_SMPL_WIDTH_32;
writel(val, dp->regs + AUDIO_SRC_CNFG);
for (i = 0; i < (audio->channels + 1) / 2; i++) {
if (audio->sample_width == 16)
val = (0x02 << 8) | (0x02 << 20);
else if (audio->sample_width == 24)
val = (0x0b << 8) | (0x0b << 20);
val |= ((2 * i) << 4) | ((2 * i + 1) << 16);
writel(val, dp->regs + STTS_BIT_CH(i));
}
switch (audio->sample_rate) {
case 32000:
val = SAMPLING_FREQ(3) |
ORIGINAL_SAMP_FREQ(0xc);
break;
case 44100:
val = SAMPLING_FREQ(0) |
ORIGINAL_SAMP_FREQ(0xf);
break;
case 48000:
val = SAMPLING_FREQ(2) |
ORIGINAL_SAMP_FREQ(0xd);
break;
case 88200:
val = SAMPLING_FREQ(8) |
ORIGINAL_SAMP_FREQ(0x7);
break;
case 96000:
val = SAMPLING_FREQ(0xa) |
ORIGINAL_SAMP_FREQ(5);
break;
case 176400:
val = SAMPLING_FREQ(0xc) |
ORIGINAL_SAMP_FREQ(3);
break;
case 192000:
val = SAMPLING_FREQ(0xe) |
ORIGINAL_SAMP_FREQ(1);
break;
}
val |= 4;
writel(val, dp->regs + COM_CH_STTS_BITS);
writel(SMPL2PKT_EN, dp->regs + SMPL2PKT_CNTL);
writel(I2S_DEC_START, dp->regs + AUDIO_SRC_CNTL);
}
static void cdn_dp_audio_config_spdif(struct cdn_dp_device *dp)
{
u32 val;
val = SPDIF_AVG_SEL | SPDIF_JITTER_BYPASS;
val |= SPDIF_FIFO_MID_RANGE(0xe0);
val |= SPDIF_JITTER_THRSH(0xe0);
val |= SPDIF_JITTER_AVG_WIN(7);
writel(val, dp->regs + SPDIF_CTRL_ADDR);
writel(SYNC_WR_TO_CH_ZERO, dp->regs + FIFO_CNTL);
val = MAX_NUM_CH(2) | AUDIO_TYPE_LPCM | CFG_SUB_PCKT_NUM(4);
writel(val, dp->regs + SMPL2PKT_CNFG);
writel(SMPL2PKT_EN, dp->regs + SMPL2PKT_CNTL);
val = SPDIF_ENABLE | SPDIF_AVG_SEL | SPDIF_JITTER_BYPASS;
val |= SPDIF_FIFO_MID_RANGE(0xe0);
val |= SPDIF_JITTER_THRSH(0xe0);
val |= SPDIF_JITTER_AVG_WIN(7);
writel(val, dp->regs + SPDIF_CTRL_ADDR);
clk_prepare_enable(dp->spdif_clk);
clk_set_rate(dp->spdif_clk, CDN_DP_SPDIF_CLK);
}
int cdn_dp_audio_config(struct cdn_dp_device *dp, struct audio_info *audio)
{
int ret;
/* reset the spdif clk before config */
if (audio->format == AFMT_SPDIF) {
reset_control_assert(dp->spdif_rst);
reset_control_deassert(dp->spdif_rst);
}
ret = cdn_dp_reg_write(dp, CM_LANE_CTRL, LANE_REF_CYC);
if (ret)
goto err_audio_config;
ret = cdn_dp_reg_write(dp, CM_CTRL, 0);
if (ret)
goto err_audio_config;
if (audio->format == AFMT_I2S)
cdn_dp_audio_config_i2s(dp, audio);
else if (audio->format == AFMT_SPDIF)
cdn_dp_audio_config_spdif(dp);
ret = cdn_dp_reg_write(dp, AUDIO_PACK_CONTROL, AUDIO_PACK_EN);
err_audio_config:
if (ret)
DRM_DEV_ERROR(dp->dev, "audio config failed: %d\n", ret);
return ret;
}

483
drivers/gpu/drm/rockchip/cdn-dp-reg.h Normal file
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@ -0,0 +1,483 @@
/*
* Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
* Author: Chris Zhong <zyw@rock-chips.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _CDN_DP_REG_H
#define _CDN_DP_REG_H
#include <linux/bitops.h>
#define ADDR_IMEM 0x10000
#define ADDR_DMEM 0x20000
/* APB CFG addr */
#define APB_CTRL 0
#define XT_INT_CTRL 0x04
#define MAILBOX_FULL_ADDR 0x08
#define MAILBOX_EMPTY_ADDR 0x0c
#define MAILBOX0_WR_DATA 0x10
#define MAILBOX0_RD_DATA 0x14
#define KEEP_ALIVE 0x18
#define VER_L 0x1c
#define VER_H 0x20
#define VER_LIB_L_ADDR 0x24
#define VER_LIB_H_ADDR 0x28
#define SW_DEBUG_L 0x2c
#define SW_DEBUG_H 0x30
#define MAILBOX_INT_MASK 0x34
#define MAILBOX_INT_STATUS 0x38
#define SW_CLK_L 0x3c
#define SW_CLK_H 0x40
#define SW_EVENTS0 0x44
#define SW_EVENTS1 0x48
#define SW_EVENTS2 0x4c
#define SW_EVENTS3 0x50
#define XT_OCD_CTRL 0x60
#define APB_INT_MASK 0x6c
#define APB_STATUS_MASK 0x70
/* audio decoder addr */
#define AUDIO_SRC_CNTL 0x30000
#define AUDIO_SRC_CNFG 0x30004
#define COM_CH_STTS_BITS 0x30008
#define STTS_BIT_CH(x) (0x3000c + ((x) << 2))
#define SPDIF_CTRL_ADDR 0x3004c
#define SPDIF_CH1_CS_3100_ADDR 0x30050
#define SPDIF_CH1_CS_6332_ADDR 0x30054
#define SPDIF_CH1_CS_9564_ADDR 0x30058
#define SPDIF_CH1_CS_12796_ADDR 0x3005c
#define SPDIF_CH1_CS_159128_ADDR 0x30060
#define SPDIF_CH1_CS_191160_ADDR 0x30064
#define SPDIF_CH2_CS_3100_ADDR 0x30068
#define SPDIF_CH2_CS_6332_ADDR 0x3006c
#define SPDIF_CH2_CS_9564_ADDR 0x30070
#define SPDIF_CH2_CS_12796_ADDR 0x30074
#define SPDIF_CH2_CS_159128_ADDR 0x30078
#define SPDIF_CH2_CS_191160_ADDR 0x3007c
#define SMPL2PKT_CNTL 0x30080
#define SMPL2PKT_CNFG 0x30084
#define FIFO_CNTL 0x30088
#define FIFO_STTS 0x3008c
/* source pif addr */
#define SOURCE_PIF_WR_ADDR 0x30800
#define SOURCE_PIF_WR_REQ 0x30804
#define SOURCE_PIF_RD_ADDR 0x30808
#define SOURCE_PIF_RD_REQ 0x3080c
#define SOURCE_PIF_DATA_WR 0x30810
#define SOURCE_PIF_DATA_RD 0x30814
#define SOURCE_PIF_FIFO1_FLUSH 0x30818
#define SOURCE_PIF_FIFO2_FLUSH 0x3081c
#define SOURCE_PIF_STATUS 0x30820
#define SOURCE_PIF_INTERRUPT_SOURCE 0x30824
#define SOURCE_PIF_INTERRUPT_MASK 0x30828
#define SOURCE_PIF_PKT_ALLOC_REG 0x3082c
#define SOURCE_PIF_PKT_ALLOC_WR_EN 0x30830
#define SOURCE_PIF_SW_RESET 0x30834
/* bellow registers need access by mailbox */
/* source car addr */
#define SOURCE_HDTX_CAR 0x0900
#define SOURCE_DPTX_CAR 0x0904
#define SOURCE_PHY_CAR 0x0908
#define SOURCE_CEC_CAR 0x090c
#define SOURCE_CBUS_CAR 0x0910
#define SOURCE_PKT_CAR 0x0918
#define SOURCE_AIF_CAR 0x091c
#define SOURCE_CIPHER_CAR 0x0920
#define SOURCE_CRYPTO_CAR 0x0924
/* clock meters addr */
#define CM_CTRL 0x0a00
#define CM_I2S_CTRL 0x0a04
#define CM_SPDIF_CTRL 0x0a08
#define CM_VID_CTRL 0x0a0c
#define CM_LANE_CTRL 0x0a10
#define I2S_NM_STABLE 0x0a14
#define I2S_NCTS_STABLE 0x0a18
#define SPDIF_NM_STABLE 0x0a1c
#define SPDIF_NCTS_STABLE 0x0a20
#define NMVID_MEAS_STABLE 0x0a24
#define I2S_MEAS 0x0a40
#define SPDIF_MEAS 0x0a80
#define NMVID_MEAS 0x0ac0
/* source vif addr */
#define BND_HSYNC2VSYNC 0x0b00
#define HSYNC2VSYNC_F1_L1 0x0b04
#define HSYNC2VSYNC_F2_L1 0x0b08
#define HSYNC2VSYNC_STATUS 0x0b0c
#define HSYNC2VSYNC_POL_CTRL 0x0b10
/* dptx phy addr */
#define DP_TX_PHY_CONFIG_REG 0x2000
#define DP_TX_PHY_STATUS_REG 0x2004
#define DP_TX_PHY_SW_RESET 0x2008
#define DP_TX_PHY_SCRAMBLER_SEED 0x200c
#define DP_TX_PHY_TRAINING_01_04 0x2010
#define DP_TX_PHY_TRAINING_05_08 0x2014
#define DP_TX_PHY_TRAINING_09_10 0x2018
#define TEST_COR 0x23fc
/* dptx hpd addr */
#define HPD_IRQ_DET_MIN_TIMER 0x2100
#define HPD_IRQ_DET_MAX_TIMER 0x2104
#define HPD_UNPLGED_DET_MIN_TIMER 0x2108
#define HPD_STABLE_TIMER 0x210c
#define HPD_FILTER_TIMER 0x2110
#define HPD_EVENT_MASK 0x211c
#define HPD_EVENT_DET 0x2120
/* dpyx framer addr */
#define DP_FRAMER_GLOBAL_CONFIG 0x2200
#define DP_SW_RESET 0x2204
#define DP_FRAMER_TU 0x2208
#define DP_FRAMER_PXL_REPR 0x220c
#define DP_FRAMER_SP 0x2210
#define AUDIO_PACK_CONTROL 0x2214
#define DP_VC_TABLE(x) (0x2218 + ((x) << 2))
#define DP_VB_ID 0x2258
#define DP_MTPH_LVP_CONTROL 0x225c
#define DP_MTPH_SYMBOL_VALUES 0x2260
#define DP_MTPH_ECF_CONTROL 0x2264
#define DP_MTPH_ACT_CONTROL 0x2268
#define DP_MTPH_STATUS 0x226c
#define DP_INTERRUPT_SOURCE 0x2270
#define DP_INTERRUPT_MASK 0x2274
#define DP_FRONT_BACK_PORCH 0x2278
#define DP_BYTE_COUNT 0x227c
/* dptx stream addr */
#define MSA_HORIZONTAL_0 0x2280
#define MSA_HORIZONTAL_1 0x2284
#define MSA_VERTICAL_0 0x2288
#define MSA_VERTICAL_1 0x228c
#define MSA_MISC 0x2290
#define STREAM_CONFIG 0x2294
#define AUDIO_PACK_STATUS 0x2298
#define VIF_STATUS 0x229c
#define PCK_STUFF_STATUS_0 0x22a0
#define PCK_STUFF_STATUS_1 0x22a4
#define INFO_PACK_STATUS 0x22a8
#define RATE_GOVERNOR_STATUS 0x22ac
#define DP_HORIZONTAL 0x22b0
#define DP_VERTICAL_0 0x22b4
#define DP_VERTICAL_1 0x22b8
#define DP_BLOCK_SDP 0x22bc
/* dptx glbl addr */
#define DPTX_LANE_EN 0x2300
#define DPTX_ENHNCD 0x2304
#define DPTX_INT_MASK 0x2308
#define DPTX_INT_STATUS 0x230c
/* dp aux addr */
#define DP_AUX_HOST_CONTROL 0x2800
#define DP_AUX_INTERRUPT_SOURCE 0x2804
#define DP_AUX_INTERRUPT_MASK 0x2808
#define DP_AUX_SWAP_INVERSION_CONTROL 0x280c
#define DP_AUX_SEND_NACK_TRANSACTION 0x2810
#define DP_AUX_CLEAR_RX 0x2814
#define DP_AUX_CLEAR_TX 0x2818
#define DP_AUX_TIMER_STOP 0x281c
#define DP_AUX_TIMER_CLEAR 0x2820
#define DP_AUX_RESET_SW 0x2824
#define DP_AUX_DIVIDE_2M 0x2828
#define DP_AUX_TX_PREACHARGE_LENGTH 0x282c
#define DP_AUX_FREQUENCY_1M_MAX 0x2830
#define DP_AUX_FREQUENCY_1M_MIN 0x2834
#define DP_AUX_RX_PRE_MIN 0x2838
#define DP_AUX_RX_PRE_MAX 0x283c
#define DP_AUX_TIMER_PRESET 0x2840
#define DP_AUX_NACK_FORMAT 0x2844
#define DP_AUX_TX_DATA 0x2848
#define DP_AUX_RX_DATA 0x284c
#define DP_AUX_TX_STATUS 0x2850
#define DP_AUX_RX_STATUS 0x2854
#define DP_AUX_RX_CYCLE_COUNTER 0x2858
#define DP_AUX_MAIN_STATES 0x285c
#define DP_AUX_MAIN_TIMER 0x2860
#define DP_AUX_AFE_OUT 0x2864
/* crypto addr */
#define CRYPTO_HDCP_REVISION 0x5800
#define HDCP_CRYPTO_CONFIG 0x5804
#define CRYPTO_INTERRUPT_SOURCE 0x5808
#define CRYPTO_INTERRUPT_MASK 0x580c
#define CRYPTO22_CONFIG 0x5818
#define CRYPTO22_STATUS 0x581c
#define SHA_256_DATA_IN 0x583c
#define SHA_256_DATA_OUT_(x) (0x5850 + ((x) << 2))
#define AES_32_KEY_(x) (0x5870 + ((x) << 2))
#define AES_32_DATA_IN 0x5880
#define AES_32_DATA_OUT_(x) (0x5884 + ((x) << 2))
#define CRYPTO14_CONFIG 0x58a0
#define CRYPTO14_STATUS 0x58a4
#define CRYPTO14_PRNM_OUT 0x58a8
#define CRYPTO14_KM_0 0x58ac
#define CRYPTO14_KM_1 0x58b0
#define CRYPTO14_AN_0 0x58b4
#define CRYPTO14_AN_1 0x58b8
#define CRYPTO14_YOUR_KSV_0 0x58bc
#define CRYPTO14_YOUR_KSV_1 0x58c0
#define CRYPTO14_MI_0 0x58c4
#define CRYPTO14_MI_1 0x58c8
#define CRYPTO14_TI_0 0x58cc
#define CRYPTO14_KI_0 0x58d0
#define CRYPTO14_KI_1 0x58d4
#define CRYPTO14_BLOCKS_NUM 0x58d8
#define CRYPTO14_KEY_MEM_DATA_0 0x58dc
#define CRYPTO14_KEY_MEM_DATA_1 0x58e0
#define CRYPTO14_SHA1_MSG_DATA 0x58e4
#define CRYPTO14_SHA1_V_VALUE_(x) (0x58e8 + ((x) << 2))
#define TRNG_CTRL 0x58fc
#define TRNG_DATA_RDY 0x5900
#define TRNG_DATA 0x5904
/* cipher addr */
#define HDCP_REVISION 0x60000
#define INTERRUPT_SOURCE 0x60004
#define INTERRUPT_MASK 0x60008
#define HDCP_CIPHER_CONFIG 0x6000c
#define AES_128_KEY_0 0x60010
#define AES_128_KEY_1 0x60014
#define AES_128_KEY_2 0x60018
#define AES_128_KEY_3 0x6001c
#define AES_128_RANDOM_0 0x60020
#define AES_128_RANDOM_1 0x60024
#define CIPHER14_KM_0 0x60028
#define CIPHER14_KM_1 0x6002c
#define CIPHER14_STATUS 0x60030
#define CIPHER14_RI_PJ_STATUS 0x60034
#define CIPHER_MODE 0x60038
#define CIPHER14_AN_0 0x6003c
#define CIPHER14_AN_1 0x60040
#define CIPHER22_AUTH 0x60044
#define CIPHER14_R0_DP_STATUS 0x60048
#define CIPHER14_BOOTSTRAP 0x6004c
#define DPTX_FRMR_DATA_CLK_RSTN_EN BIT(11)
#define DPTX_FRMR_DATA_CLK_EN BIT(10)
#define DPTX_PHY_DATA_RSTN_EN BIT(9)
#define DPTX_PHY_DATA_CLK_EN BIT(8)
#define DPTX_PHY_CHAR_RSTN_EN BIT(7)
#define DPTX_PHY_CHAR_CLK_EN BIT(6)
#define SOURCE_AUX_SYS_CLK_RSTN_EN BIT(5)
#define SOURCE_AUX_SYS_CLK_EN BIT(4)
#define DPTX_SYS_CLK_RSTN_EN BIT(3)
#define DPTX_SYS_CLK_EN BIT(2)
#define CFG_DPTX_VIF_CLK_RSTN_EN BIT(1)
#define CFG_DPTX_VIF_CLK_EN BIT(0)
#define SOURCE_PHY_RSTN_EN BIT(1)
#define SOURCE_PHY_CLK_EN BIT(0)
#define SOURCE_PKT_SYS_RSTN_EN BIT(3)
#define SOURCE_PKT_SYS_CLK_EN BIT(2)
#define SOURCE_PKT_DATA_RSTN_EN BIT(1)
#define SOURCE_PKT_DATA_CLK_EN BIT(0)
#define SPDIF_CDR_CLK_RSTN_EN BIT(5)
#define SPDIF_CDR_CLK_EN BIT(4)
#define SOURCE_AIF_SYS_RSTN_EN BIT(3)
#define SOURCE_AIF_SYS_CLK_EN BIT(2)
#define SOURCE_AIF_CLK_RSTN_EN BIT(1)
#define SOURCE_AIF_CLK_EN BIT(0)
#define SOURCE_CIPHER_SYSTEM_CLK_RSTN_EN BIT(3)
#define SOURCE_CIPHER_SYS_CLK_EN BIT(2)
#define SOURCE_CIPHER_CHAR_CLK_RSTN_EN BIT(1)
#define SOURCE_CIPHER_CHAR_CLK_EN BIT(0)
#define SOURCE_CRYPTO_SYS_CLK_RSTN_EN BIT(1)
#define SOURCE_CRYPTO_SYS_CLK_EN BIT(0)
#define APB_IRAM_PATH BIT(2)
#define APB_DRAM_PATH BIT(1)
#define APB_XT_RESET BIT(0)
#define MAILBOX_INT_MASK_BIT BIT(1)
#define PIF_INT_MASK_BIT BIT(0)
#define ALL_INT_MASK 3
/* mailbox */
#define MB_OPCODE_ID 0
#define MB_MODULE_ID 1
#define MB_SIZE_MSB_ID 2
#define MB_SIZE_LSB_ID 3
#define MB_DATA_ID 4
#define MB_MODULE_ID_DP_TX 0x01
#define MB_MODULE_ID_HDCP_TX 0x07
#define MB_MODULE_ID_HDCP_RX 0x08
#define MB_MODULE_ID_HDCP_GENERAL 0x09
#define MB_MODULE_ID_GENERAL 0x0a
/* general opcode */
#define GENERAL_MAIN_CONTROL 0x01
#define GENERAL_TEST_ECHO 0x02
#define GENERAL_BUS_SETTINGS 0x03
#define GENERAL_TEST_ACCESS 0x04
#define DPTX_SET_POWER_MNG 0x00
#define DPTX_SET_HOST_CAPABILITIES 0x01
#define DPTX_GET_EDID 0x02
#define DPTX_READ_DPCD 0x03
#define DPTX_WRITE_DPCD 0x04
#define DPTX_ENABLE_EVENT 0x05
#define DPTX_WRITE_REGISTER 0x06
#define DPTX_READ_REGISTER 0x07
#define DPTX_WRITE_FIELD 0x08
#define DPTX_TRAINING_CONTROL 0x09
#define DPTX_READ_EVENT 0x0a
#define DPTX_READ_LINK_STAT 0x0b
#define DPTX_SET_VIDEO 0x0c
#define DPTX_SET_AUDIO 0x0d
#define DPTX_GET_LAST_AUX_STAUS 0x0e
#define DPTX_SET_LINK_BREAK_POINT 0x0f
#define DPTX_FORCE_LANES 0x10
#define DPTX_HPD_STATE 0x11
#define FW_STANDBY 0
#define FW_ACTIVE 1
#define DPTX_EVENT_ENABLE_HPD BIT(0)
#define DPTX_EVENT_ENABLE_TRAINING BIT(1)
#define LINK_TRAINING_NOT_ACTIVE 0
#define LINK_TRAINING_RUN 1
#define LINK_TRAINING_RESTART 2
#define CONTROL_VIDEO_IDLE 0
#define CONTROL_VIDEO_VALID 1
#define TU_CNT_RST_EN BIT(15)
#define VIF_BYPASS_INTERLACE BIT(13)
#define INTERLACE_FMT_DET BIT(12)
#define INTERLACE_DTCT_WIN 0x20
#define DP_FRAMER_SP_INTERLACE_EN BIT(2)
#define DP_FRAMER_SP_HSP BIT(1)
#define DP_FRAMER_SP_VSP BIT(0)
/* capability */
#define AUX_HOST_INVERT 3
#define FAST_LT_SUPPORT 1
#define FAST_LT_NOT_SUPPORT 0
#define LANE_MAPPING_NORMAL 0x1b
#define LANE_MAPPING_FLIPPED 0xe4
#define ENHANCED 1
#define SCRAMBLER_EN BIT(4)
#define FULL_LT_STARTED BIT(0)
#define FASE_LT_STARTED BIT(1)
#define CLK_RECOVERY_FINISHED BIT(2)
#define EQ_PHASE_FINISHED BIT(3)
#define FASE_LT_START_FINISHED BIT(4)
#define CLK_RECOVERY_FAILED BIT(5)
#define EQ_PHASE_FAILED BIT(6)
#define FASE_LT_FAILED BIT(7)
#define DPTX_HPD_EVENT BIT(0)
#define DPTX_TRAINING_EVENT BIT(1)
#define HDCP_TX_STATUS_EVENT BIT(4)
#define HDCP2_TX_IS_KM_STORED_EVENT BIT(5)
#define HDCP2_TX_STORE_KM_EVENT BIT(6)
#define HDCP_TX_IS_RECEIVER_ID_VALID_EVENT BIT(7)
#define TU_SIZE 30
#define CDN_DP_MAX_LINK_RATE DP_LINK_BW_5_4
/* audio */
#define AUDIO_PACK_EN BIT(8)
#define SAMPLING_FREQ(x) (((x) & 0xf) << 16)
#define ORIGINAL_SAMP_FREQ(x) (((x) & 0xf) << 24)
#define SYNC_WR_TO_CH_ZERO BIT(1)
#define I2S_DEC_START BIT(1)
#define AUDIO_SW_RST BIT(0)
#define SMPL2PKT_EN BIT(1)
#define MAX_NUM_CH(x) (((x) & 0x1f) - 1)
#define NUM_OF_I2S_PORTS(x) ((((x) / 2 - 1) & 0x3) << 5)
#define AUDIO_TYPE_LPCM (2 << 7)
#define CFG_SUB_PCKT_NUM(x) ((((x) - 1) & 0x7) << 11)
#define AUDIO_CH_NUM(x) ((((x) - 1) & 0x1f) << 2)
#define TRANS_SMPL_WIDTH_16 0
#define TRANS_SMPL_WIDTH_24 BIT(11)
#define TRANS_SMPL_WIDTH_32 (2 << 11)
#define I2S_DEC_PORT_EN(x) (((x) & 0xf) << 17)
#define SPDIF_ENABLE BIT(21)
#define SPDIF_AVG_SEL BIT(20)
#define SPDIF_JITTER_BYPASS BIT(19)
#define SPDIF_FIFO_MID_RANGE(x) (((x) & 0xff) << 11)
#define SPDIF_JITTER_THRSH(x) (((x) & 0xff) << 3)
#define SPDIF_JITTER_AVG_WIN(x) ((x) & 0x7)
/* Reference cycles when using lane clock as reference */
#define LANE_REF_CYC 0x8000
enum voltage_swing_level {
VOLTAGE_LEVEL_0,
VOLTAGE_LEVEL_1,
VOLTAGE_LEVEL_2,
VOLTAGE_LEVEL_3,
};
enum pre_emphasis_level {
PRE_EMPHASIS_LEVEL_0,
PRE_EMPHASIS_LEVEL_1,
PRE_EMPHASIS_LEVEL_2,
PRE_EMPHASIS_LEVEL_3,
};
enum pattern_set {
PTS1 = BIT(0),
PTS2 = BIT(1),
PTS3 = BIT(2),
PTS4 = BIT(3),
DP_NONE = BIT(4)
};
enum vic_color_depth {
BCS_6 = 0x1,
BCS_8 = 0x2,
BCS_10 = 0x4,
BCS_12 = 0x8,
BCS_16 = 0x10,
};
enum vic_bt_type {
BT_601 = 0x0,
BT_709 = 0x1,
};
void cdn_dp_clock_reset(struct cdn_dp_device *dp);
void cdn_dp_set_fw_clk(struct cdn_dp_device *dp, u32 clk);
int cdn_dp_load_firmware(struct cdn_dp_device *dp, const u32 *i_mem,
u32 i_size, const u32 *d_mem, u32 d_size);
int cdn_dp_set_firmware_active(struct cdn_dp_device *dp, bool enable);
int cdn_dp_set_host_cap(struct cdn_dp_device *dp, u8 lanes, bool flip);
int cdn_dp_event_config(struct cdn_dp_device *dp);
u32 cdn_dp_get_event(struct cdn_dp_device *dp);
int cdn_dp_get_hpd_status(struct cdn_dp_device *dp);
int cdn_dp_dpcd_write(struct cdn_dp_device *dp, u32 addr, u8 value);
int cdn_dp_dpcd_read(struct cdn_dp_device *dp, u32 addr, u8 *data, u16 len);
int cdn_dp_get_edid_block(void *dp, u8 *edid,
unsigned int block, size_t length);
int cdn_dp_train_link(struct cdn_dp_device *dp);
int cdn_dp_set_video_status(struct cdn_dp_device *dp, int active);
int cdn_dp_config_video(struct cdn_dp_device *dp);
int cdn_dp_audio_stop(struct cdn_dp_device *dp, struct audio_info *audio);
int cdn_dp_audio_mute(struct cdn_dp_device *dp, bool enable);
int cdn_dp_audio_config(struct cdn_dp_device *dp, struct audio_info *audio);
#endif /* _CDN_DP_REG_H */

2
drivers/gpu/drm/rockchip/rockchip_drm_fb.c
View File

@ -213,7 +213,7 @@ rockchip_drm_framebuffer_init(struct drm_device *dev,
rockchip_fb = rockchip_fb_alloc(dev, mode_cmd, &obj, 1);
if (IS_ERR(rockchip_fb))
return NULL;
return ERR_CAST(rockchip_fb);
return &rockchip_fb->fb;
}

17
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
View File

@ -531,6 +531,8 @@ static int vop_enable(struct drm_crtc *crtc)
}
memcpy(vop->regs, vop->regsbak, vop->len);
vop_cfg_done(vop);
/*
* At here, vop clock & iommu is enable, R/W vop regs would be safe.
*/
@ -582,6 +584,8 @@ static void vop_crtc_disable(struct drm_crtc *crtc)
spin_unlock(&vop->reg_lock);
}
vop_cfg_done(vop);
drm_crtc_vblank_off(crtc);
/*
@ -932,9 +936,11 @@ static void vop_crtc_enable(struct drm_crtc *crtc)
vop_dsp_hold_valid_irq_disable(vop);
}
pin_pol = 0x8;
pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
pin_pol = BIT(DCLK_INVERT);
pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ?
0 : BIT(HSYNC_POSITIVE);
pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ?
0 : BIT(VSYNC_POSITIVE);
VOP_CTRL_SET(vop, pin_pol, pin_pol);
switch (s->output_type) {
@ -954,6 +960,11 @@ static void vop_crtc_enable(struct drm_crtc *crtc)
VOP_CTRL_SET(vop, mipi_pin_pol, pin_pol);
VOP_CTRL_SET(vop, mipi_en, 1);
break;
case DRM_MODE_CONNECTOR_DisplayPort:
pin_pol &= ~BIT(DCLK_INVERT);
VOP_CTRL_SET(vop, dp_pin_pol, pin_pol);
VOP_CTRL_SET(vop, dp_en, 1);
break;
default:
DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n",
s->output_type);

9
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
View File

@ -45,6 +45,7 @@ struct vop_ctrl {
struct vop_reg edp_en;
struct vop_reg hdmi_en;
struct vop_reg mipi_en;
struct vop_reg dp_en;
struct vop_reg out_mode;
struct vop_reg dither_down;
struct vop_reg dither_up;
@ -53,6 +54,7 @@ struct vop_ctrl {
struct vop_reg hdmi_pin_pol;
struct vop_reg edp_pin_pol;
struct vop_reg mipi_pin_pol;
struct vop_reg dp_pin_pol;
struct vop_reg htotal_pw;
struct vop_reg hact_st_end;
@ -244,6 +246,13 @@ enum scale_down_mode {
SCALE_DOWN_AVG = 0x1
};
enum vop_pol {
HSYNC_POSITIVE = 0,
VSYNC_POSITIVE = 1,
DEN_NEGATIVE = 2,
DCLK_INVERT = 3
};
#define FRAC_16_16(mult, div) (((mult) << 16) / (div))
#define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12
#define SCL_MAX_VSKIPLINES 4

2
drivers/gpu/drm/rockchip/rockchip_vop_reg.c
View File

@ -284,6 +284,7 @@ static const struct vop_data rk3288_vop = {
static const struct vop_ctrl rk3399_ctrl_data = {
.standby = VOP_REG(RK3399_SYS_CTRL, 0x1, 22),
.gate_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 23),
.dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11),
.rgb_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 12),
.hdmi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 13),
.edp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 14),
@ -293,6 +294,7 @@ static const struct vop_ctrl rk3399_ctrl_data = {
.data_blank = VOP_REG(RK3399_DSP_CTRL0, 0x1, 19),
.out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0),
.rgb_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16),
.dp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16),
.hdmi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 20),
.edp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 24),
.mipi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 28),